Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	29055862	10039	0	0
attest_sw_binding_0_rd_A	29055862	2929	0	0
attest_sw_binding_1_rd_A	29055862	2940	0	0
attest_sw_binding_2_rd_A	29055862	2894	0	0
attest_sw_binding_3_rd_A	29055862	2902	0	0
attest_sw_binding_4_rd_A	29055862	2845	0	0
attest_sw_binding_5_rd_A	29055862	2988	0	0
attest_sw_binding_6_rd_A	29055862	2840	0	0
attest_sw_binding_7_rd_A	29055862	2891	0	0
intr_enable_rd_A	29055862	3688	0	0
key_version_rd_A	29055862	3178	0	0
max_creator_key_ver_regwen_rd_A	29055862	2998	0	0
max_owner_int_key_ver_regwen_rd_A	29055862	2939	0	0
max_owner_key_ver_regwen_rd_A	29055862	3029	0	0
reseed_interval_regwen_rd_A	29055862	3034	0	0
salt_0_rd_A	29055862	2913	0	0
salt_1_rd_A	29055862	3000	0	0
salt_2_rd_A	29055862	3097	0	0
salt_3_rd_A	29055862	3094	0	0
salt_4_rd_A	29055862	3027	0	0
salt_5_rd_A	29055862	3116	0	0
salt_6_rd_A	29055862	3008	0	0
salt_7_rd_A	29055862	2990	0	0
sealing_sw_binding_0_rd_A	29055862	3102	0	0
sealing_sw_binding_1_rd_A	29055862	3102	0	0
sealing_sw_binding_2_rd_A	29055862	3080	0	0
sealing_sw_binding_3_rd_A	29055862	3132	0	0
sealing_sw_binding_4_rd_A	29055862	3008	0	0
sealing_sw_binding_5_rd_A	29055862	2932	0	0
sealing_sw_binding_6_rd_A	29055862	2936	0	0
sealing_sw_binding_7_rd_A	29055862	2920	0	0
sideload_clear_rd_A	29055862	3025	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	10039	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	207	0	0
T60	0	50	0	0
T61	0	814	0	0
T70	0	20	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T124	0	461	0	0
T125	0	98	0	0
T126	0	490	0	0
T127	0	480	0	0
T128	0	145	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T176	0	1	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	2929	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	35	0	0
T60	0	71	0	0
T70	0	13	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	48	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	16	0	0
T136	0	8	0	0
T177	0	44	0	0
T178	0	26	0	0
T179	0	1	0	0
T180	0	9	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	2940	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	42	0	0
T60	0	30	0	0
T70	0	8	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	59	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	34	0	0
T136	0	6	0	0
T177	0	47	0	0
T178	0	41	0	0
T179	0	10	0	0
T180	0	31	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	2894	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	21	0	0
T60	0	65	0	0
T70	0	16	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	26	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	48	0	0
T136	0	3	0	0
T177	0	34	0	0
T178	0	82	0	0
T179	0	15	0	0
T180	0	20	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	2902	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	31	0	0
T60	0	43	0	0
T70	0	20	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	77	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	22	0	0
T136	0	2	0	0
T177	0	43	0	0
T178	0	63	0	0
T179	0	17	0	0
T180	0	20	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	2845	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	36	0	0
T60	0	50	0	0
T70	0	15	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	62	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	22	0	0
T136	0	9	0	0
T177	0	18	0	0
T178	0	41	0	0
T179	0	16	0	0
T180	0	20	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	2988	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	18	0	0
T60	0	67	0	0
T70	0	7	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	94	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	24	0	0
T177	0	27	0	0
T178	0	59	0	0
T179	0	23	0	0
T180	0	23	0	0
T181	0	37	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	2840	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	43	0	0
T60	0	50	0	0
T70	0	5	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	44	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	51	0	0
T136	0	9	0	0
T177	0	35	0	0
T178	0	41	0	0
T179	0	19	0	0
T180	0	19	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	2891	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	29	0	0
T60	0	84	0	0
T70	0	11	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	60	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	24	0	0
T136	0	2	0	0
T140	0	2	0	0
T177	0	47	0	0
T178	0	78	0	0
T180	0	22	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	3688	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	27	0	0
T60	0	81	0	0
T70	0	11	0	0
T72	0	12	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	80	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	63	0	0
T182	0	5	0	0
T183	0	50	0	0
T184	0	32	0	0
T185	0	22	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	3178	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	23	0	0
T60	0	52	0	0
T70	0	17	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	39	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	32	0	0
T136	0	4	0	0
T177	0	33	0	0
T178	0	78	0	0
T179	0	5	0	0
T180	0	29	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	2998	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	27	0	0
T60	0	46	0	0
T70	0	17	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	64	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	35	0	0
T136	0	4	0	0
T177	0	53	0	0
T178	0	55	0	0
T179	0	22	0	0
T180	0	24	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	2939	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	21	0	0
T60	0	29	0	0
T70	0	16	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	58	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	16	0	0
T136	0	1	0	0
T177	0	69	0	0
T178	0	84	0	0
T179	0	16	0	0
T180	0	32	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	3029	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	17	0	0
T60	0	55	0	0
T70	0	9	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	70	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	36	0	0
T136	0	7	0	0
T177	0	13	0	0
T178	0	49	0	0
T179	0	26	0	0
T180	0	27	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	3034	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	18	0	0
T60	0	69	0	0
T70	0	19	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	61	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	23	0	0
T136	0	8	0	0
T177	0	46	0	0
T178	0	56	0	0
T179	0	19	0	0
T180	0	29	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	2913	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	56	0	0
T60	0	54	0	0
T70	0	14	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	69	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	11	0	0
T136	0	1	0	0
T177	0	26	0	0
T178	0	54	0	0
T179	0	3	0	0
T180	0	14	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	3000	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	37	0	0
T60	0	66	0	0
T70	0	12	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	50	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	23	0	0
T136	0	2	0	0
T177	0	28	0	0
T178	0	85	0	0
T179	0	6	0	0
T180	0	36	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	3097	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	28	0	0
T60	0	44	0	0
T70	0	19	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	67	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	34	0	0
T140	0	4	0	0
T177	0	17	0	0
T178	0	90	0	0
T179	0	13	0	0
T180	0	18	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	3094	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	22	0	0
T60	0	57	0	0
T70	0	10	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	59	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	32	0	0
T136	0	3	0	0
T177	0	59	0	0
T178	0	48	0	0
T179	0	2	0	0
T180	0	20	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	3027	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	27	0	0
T60	0	48	0	0
T70	0	17	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	84	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	45	0	0
T136	0	9	0	0
T177	0	44	0	0
T178	0	39	0	0
T179	0	30	0	0
T180	0	15	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	3116	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	38	0	0
T60	0	50	0	0
T70	0	15	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	75	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	39	0	0
T136	0	5	0	0
T177	0	30	0	0
T178	0	36	0	0
T179	0	12	0	0
T180	0	23	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	3008	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	23	0	0
T60	0	69	0	0
T70	0	21	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	70	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	24	0	0
T177	0	20	0	0
T178	0	41	0	0
T179	0	23	0	0
T180	0	24	0	0
T186	0	3	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	2990	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	19	0	0
T60	0	49	0	0
T70	0	14	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	58	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	53	0	0
T136	0	1	0	0
T177	0	29	0	0
T178	0	58	0	0
T179	0	25	0	0
T180	0	21	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	3102	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	26	0	0
T60	0	72	0	0
T70	0	12	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	56	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	17	0	0
T136	0	2	0	0
T177	0	16	0	0
T178	0	40	0	0
T179	0	27	0	0
T180	0	26	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	3102	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	35	0	0
T60	0	60	0	0
T70	0	23	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	48	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	27	0	0
T136	0	5	0	0
T177	0	24	0	0
T178	0	54	0	0
T179	0	31	0	0
T180	0	27	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	3080	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	29	0	0
T60	0	84	0	0
T70	0	6	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	70	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	39	0	0
T136	0	5	0	0
T177	0	41	0	0
T178	0	46	0	0
T179	0	12	0	0
T180	0	20	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	3132	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	36	0	0
T60	0	47	0	0
T70	0	5	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	51	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	44	0	0
T136	0	5	0	0
T177	0	44	0	0
T178	0	79	0	0
T179	0	23	0	0
T180	0	21	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	3008	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	16	0	0
T60	0	39	0	0
T70	0	11	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	64	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	27	0	0
T136	0	3	0	0
T177	0	27	0	0
T178	0	36	0	0
T179	0	7	0	0
T180	0	24	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	2932	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	21	0	0
T60	0	59	0	0
T70	0	3	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	58	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	27	0	0
T136	0	3	0	0
T177	0	29	0	0
T178	0	67	0	0
T179	0	23	0	0
T180	0	28	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	2936	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	28	0	0
T60	0	54	0	0
T70	0	12	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	46	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	26	0	0
T136	0	1	0	0
T177	0	30	0	0
T178	0	57	0	0
T179	0	12	0	0
T180	0	29	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	2920	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	28	0	0
T60	0	40	0	0
T70	0	3	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	80	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	43	0	0
T136	0	3	0	0
T177	0	30	0	0
T178	0	38	0	0
T179	0	18	0	0
T180	0	24	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29055862	3025	0	0
T41	8568	0	0	0
T52	14018	0	0	0
T56	61904	38	0	0
T60	0	61	0	0
T70	0	22	0	0
T77	27627	0	0	0
T78	6976	0	0	0
T79	5938	0	0	0
T80	60833	0	0	0
T127	0	42	0	0
T129	5747	0	0	0
T130	4882	0	0	0
T131	5334	0	0	0
T133	0	12	0	0
T177	0	47	0	0
T178	0	58	0	0
T179	0	20	0	0
T180	0	39	0	0
T181	0	42	0	0