KEYMGR Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: `f7fc348358`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	1.022m	18.341ms	50	50	100.00
V1	random	keymgr_random	1.246m	2.242ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.390s	54.943us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.700s	31.000us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	18.710s	3.995ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	9.220s	1.252ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.560s	71.944us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.700s	31.000us	20	20	100.00
		keymgr_csr_aliasing	9.220s	1.252ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	59.640s	4.388ms	50	50	100.00
V2	sideload	keymgr_sideload	48.140s	2.366ms	50	50	100.00
		keymgr_sideload_kmac	56.550s	3.036ms	50	50	100.00
		keymgr_sideload_aes	41.390s	1.322ms	50	50	100.00
		keymgr_sideload_otbn	31.850s	967.393us	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	24.710s	1.206ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	13.330s	929.233us	48	50	96.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.170m	2.623ms	46	50	92.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.100m	6.460ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.044m	15.117ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	15.090s	587.520us	50	50	100.00
V2	stress_all	keymgr_stress_all	12.341m	23.092ms	49	50	98.00
V2	intr_test	keymgr_intr_test	0.930s	15.199us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.070s	82.670us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.460s	750.825us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.460s	750.825us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.390s	54.943us	5	5	100.00
		keymgr_csr_rw	1.700s	31.000us	20	20	100.00
		keymgr_csr_aliasing	9.220s	1.252ms	5	5	100.00
		keymgr_same_csr_outstanding	3.000s	97.598us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.390s	54.943us	5	5	100.00
		keymgr_csr_rw	1.700s	31.000us	20	20	100.00
		keymgr_csr_aliasing	9.220s	1.252ms	5	5	100.00
		keymgr_same_csr_outstanding	3.000s	97.598us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	sec_cm_additional_check	keymgr_sec_cm	44.000s	6.856ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	44.000s	6.856ms	5	5	100.00
		keymgr_tl_intg_err	1.265m	12.332ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	8.150s	445.687us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	8.150s	445.687us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	8.150s	445.687us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	8.150s	445.687us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	18.320s	611.490us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	44.000s	6.856ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	44.000s	6.856ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	1.265m	12.332ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	8.150s	445.687us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	59.640s	4.388ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.246m	2.242ms	50	50	100.00
		keymgr_csr_rw	1.700s	31.000us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.246m	2.242ms	50	50	100.00
		keymgr_csr_rw	1.700s	31.000us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.246m	2.242ms	50	50	100.00
		keymgr_csr_rw	1.700s	31.000us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	13.330s	929.233us	48	50	96.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.044m	15.117ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.044m	15.117ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.246m	2.242ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	29.240s	2.787ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	44.000s	6.856ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	44.000s	6.856ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	44.000s	6.856ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	54.770s	7.141ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	13.330s	929.233us	48	50	96.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	44.000s	6.856ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	44.000s	6.856ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	44.000s	6.856ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	54.770s	7.141ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	54.770s	7.141ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	44.000s	6.856ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	54.770s	7.141ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	44.000s	6.856ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	54.770s	7.141ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	29.590s	2.447ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1075	1110	96.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.85	99.07	98.14	98.60	100.00	99.11	98.41	91.63

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test keymgr_stress_all_with_rand_reset has 23 failures.
  - 1.keymgr_stress_all_with_rand_reset.33476731715720261852054070207309325798719481816215871419665297003577548399866
    Line 1073, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 241529065 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 241529065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.keymgr_stress_all_with_rand_reset.101940052687594391155593572620258867179381692793297552113911817903519928047117
    Line 267, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 242675238 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 242675238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.

UVM_ERROR (keymgr_scoreboard.sv:1013) [scoreboard] Check failed act != exp (* [*] vs * [*]) cdi_type: Attestation has 4 failures:

Test keymgr_kmac_rsp_err has 4 failures.

14.keymgr_kmac_rsp_err.100418725343508057949487009386829584526909710345432244297282120562237083379782
Line 530, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/14.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  56644023 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (1371331013344855778839361569560181171174222308409491196065480799655667951474503445472993630582648956010639806883499852927457898712717193885121879639796199580226145295326426489930898696526969053606038324232706349227447707912911556795657434633880643116664092571361676964932616406298874643771420174941200866615105206287190906887912406621680211458960235327863147884226706592680551195537869958321360198361171927267004535988767338 [0x318fdbd4317be4318d681e1d1b8bd2b01ba51c0e09910fc067e26eed5fbc2eb33a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9fe75e95181d991b0b44a8243d16cce27bede44df2026f78a55650ce27db02df3397b258cc8945b07ed769a5e373f6f3191bbf7acdac828f1b113c64a9df18f56192f786f7969c252fc3e16b8b8aa06c6a9990628c4dcccec701696fad461c2417baeddcfde8e9e16b77724744a034a6a] vs 1371331013344855778839361569560181171174222308409491196065480799655667951474503445472993630582648956010639806883499852927457898712717193885121879639796199580226145295326426489930898696526969053606038324232706349227447707912911556795657434633880643116664092571361676964932616406298874643771420174941200866615105206287190906887912406621680211458960235327863147884226706592680551195537869958321360198361171927267004535988767338 [0x318fdbd4317be4318d681e1d1b8bd2b01ba51c0e09910fc067e26eed5fbc2eb33a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9fe75e95181d991b0b44a8243d16cce27bede44df2026f78a55650ce27db02df3397b258cc8945b07ed769a5e373f6f3191bbf7acdac828f1b113c64a9df18f56192f786f7969c252fc3e16b8b8aa06c6a9990628c4dcccec701696fad461c2417baeddcfde8e9e16b77724744a034a6a]) cdi_type: Attestation
  
   DiversificationKey act: 0xa9990628c4dcccec701696fad461c2417baeddcfde8e9e16b77724744a034a6a, exp: 0xa9990628c4dcccec701696fad461c2417baeddcfde8e9e16b77724744a034a6a
   RomDigest act: 0x91bbf7acdac828f1b113c64a9df18f56192f786f7969c252fc3e16b8b8aa06c6, exp: 0x91bbf7acdac828f1b113c64a9df18f56192f786f7969c252fc3e16b8b8aa06c6
   HealthMeasurement act: 0x397b258cc8945b07ed769a5e373f6f31, exp: 0x397b258cc8945b07ed769a5e373f6f31

20.keymgr_kmac_rsp_err.39267751115695687267828140088912960187229196279571756576325968643582675029080
Line 328, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/20.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @ 137596009 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (5852701700183046867951212721641755090383714833284802022318495018227889495433527093263717015750073403139932089919340694499943567554269461272241076940588121932547303474159034944206942150635502698469072841566653680896987203485214042031176522741682117143044437319228779393500076901791348331974091725063895283298409034847760960729088110622960872594684664946314509038407612236920230249183047605329886235690762620660097017657562491 [0xd3867e8a8ace37165b4188d7ab9f95d08d75e0ea0000000005dd1f1092b924c23a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f995321fab45703129ecd53da8a56bc46f969c46c43d6883be74fdd343841d9a30152b126c2f90aa7b15c407e5429767642967181c071f4a101a8a45b003a485823ff064d88e8857adc1e9c04365a2c6dea7fb9d68cff48b8503d0748e12a92fc8c3759beb6baf03db9c91bc17f736157b] vs 5852701700183046867951212721641755090383714833284802022318495018227889495433527093263717015750073403139932089919340694499943567554269461272241076940588121932547303474159034944206942150635502698469072841566653680896987203485214042031176522741682117143044437319228779393500076901791348331974091725063895283298409034847760960729088110622960872594684664946314509038407612236920230249183047605329886235690762620660097017657562491 [0xd3867e8a8ace37165b4188d7ab9f95d08d75e0ea0000000005dd1f1092b924c23a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f995321fab45703129ecd53da8a56bc46f969c46c43d6883be74fdd343841d9a30152b126c2f90aa7b15c407e5429767642967181c071f4a101a8a45b003a485823ff064d88e8857adc1e9c04365a2c6dea7fb9d68cff48b8503d0748e12a92fc8c3759beb6baf03db9c91bc17f736157b]) cdi_type: Attestation
  
   DiversificationKey act: 0xa7fb9d68cff48b8503d0748e12a92fc8c3759beb6baf03db9c91bc17f736157b, exp: 0xa7fb9d68cff48b8503d0748e12a92fc8c3759beb6baf03db9c91bc17f736157b
   RomDigest act: 0x2967181c071f4a101a8a45b003a485823ff064d88e8857adc1e9c04365a2c6de, exp: 0x2967181c071f4a101a8a45b003a485823ff064d88e8857adc1e9c04365a2c6de
   HealthMeasurement act: 0x152b126c2f90aa7b15c407e542976764, exp: 0x152b126c2f90aa7b15c407e542976764

... and 2 more failures.

UVM_ERROR (keymgr_scoreboard.sv:736) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * [])` has 3 failures:
- Test keymgr_stress_all_with_rand_reset has 3 failures.
  - 24.keymgr_stress_all_with_rand_reset.75402669136616074027401697604277953712509175264297139713988716337090412467132
    Line 912, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/24.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 107341544 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3638322442 [0xd8dc650a] vs 3638322442 [0xd8dc650a])
  UVM_INFO @ 107341544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.keymgr_stress_all_with_rand_reset.11871338215029570657673554361378107344861458793371646711382388045630378042079
    Line 915, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/38.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 415211857 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (1531400661 [0x5b4751d5] vs 1531400661 [0x5b4751d5])
  UVM_INFO @ 415211857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (keymgr_scoreboard.sv:633) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*]) has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 4.keymgr_lc_disable.95949020242559734599293230166592699757937453129833533604352988207570421328160
    Line 258, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @   2869678 ps: (keymgr_scoreboard.sv:633) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (1 [0x1] vs 6 [0x6])
  UVM_INFO @   2869678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 6.keymgr_lc_disable.48165543456899622619022490753418637189637073588010242105064706462181581374725
    Line 526, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @ 267519170 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (1233297557 [0x4982a095] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_3
  UVM_INFO @ 267519170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 7.keymgr_stress_all.59171371224203626223704456836535566286632839064898496036977079634749268392607
    Line 1340, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/7.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 660793963 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 660793963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_scoreboard.sv:1011) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation has 1 failures:

Test keymgr_stress_all_with_rand_reset has 1 failures.

21.keymgr_stress_all_with_rand_reset.26633325593887680181213793558148985312293650591597873058104473621988951354652
Line 1226, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/21.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 554925683 ps: (keymgr_scoreboard.sv:1011) [uvm_test_top.env.scoreboard] Check failed act == exp (166291375697036804321211313728673800054308707002092629348716765147872328728250379803923228250080524138854107953228305607399725646482131357169156262743326491989949931518559971245865365973475563496837732382333542072158792450041076748892979737610293860301045780509746118616180397736892288222879701123128964712534330611574334037929497624789706887575965093221199535080623697138363687548549703410374661090870978 [0x6edd825600000000000000000000000000000000594538223a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f91ec71393772d7792504a793f8e3aa90f9231bc20776b31db6a839a2a9689189383ea177722f128f314a8648a8a14e72d638f3b76ad3fcf32cd9ca464e11051844482641cafc253c0e07dba07a0c7137a731080ab933424cbe513ea4284be1f914611d4d506fde3d4848cc4ff8fe086c2] vs 145308504278426924472778440357124330708543836311736354407696859353895671224666897140490393014749814750822655828562958324023665000796561407758432200637891572852410484792781646545077374570519531835700342874847097787517138436664414962195703240116948761852245348085456544081855696764336961311389837825797895501660199145153356869986017372838155839550695827681025121303924894385603573679784930345878971735901890 [0x60e04ab3000000000000000000000000bfdec04f000000003a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f91ec71393772d7792504a793f8e3aa90f9231bc20776b31db6a839a2a9689189383ea177722f128f314a8648a8a14e72d638f3b76ad3fcf32cd9ca464e11051844482641cafc253c0e07dba07a0c7137a731080ab933424cbe513ea4284be1f914611d4d506fde3d4848cc4ff8fe086c2]) cdi_type: Attestation
  
   DiversificationKey act: 0x731080ab933424cbe513ea4284be1f914611d4d506fde3d4848cc4ff8fe086c2, exp: 0x731080ab933424cbe513ea4284be1f914611d4d506fde3d4848cc4ff8fe086c2
   RomDigest act: 0x638f3b76ad3fcf32cd9ca464e11051844482641cafc253c0e07dba07a0c7137a, exp: 0x638f3b76ad3fcf32cd9ca464e11051844482641cafc253c0e07dba07a0c7137a
   HealthMeasurement act: 0x83ea177722f128f314a8648a8a14e72d, exp: 0x83ea177722f128f314a8648a8a14e72d

UVM_ERROR (keymgr_scoreboard.sv:674) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 34.keymgr_stress_all_with_rand_reset.103512138800916953788685483120055160183265299603931051411379818406759751660051
    Line 594, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/34.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 171143431 ps: (keymgr_scoreboard.sv:674) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (2 [0x2] vs 3 [0x3])
  UVM_INFO @ 171143431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```