KEYMGR Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: `36c168c253`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	35.220s	8.502ms	50	50	100.00
V1	random	keymgr_random	49.730s	5.478ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.520s	132.603us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.550s	26.071us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	17.180s	876.987us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	11.830s	468.335us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.540s	51.016us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.550s	26.071us	20	20	100.00
		keymgr_csr_aliasing	11.830s	468.335us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.826m	4.059ms	50	50	100.00
V2	sideload	keymgr_sideload	49.620s	2.766ms	50	50	100.00
		keymgr_sideload_kmac	1.147m	6.605ms	49	50	98.00
		keymgr_sideload_aes	45.900s	1.835ms	50	50	100.00
		keymgr_sideload_otbn	1.030m	1.987ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	38.250s	3.903ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	33.780s	2.097ms	48	50	96.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.493m	24.897ms	45	50	90.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.711m	10.388ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.843m	9.488ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	9.650s	1.558ms	50	50	100.00
V2	stress_all	keymgr_stress_all	14.733m	84.778ms	47	50	94.00
V2	intr_test	keymgr_intr_test	1.010s	19.024us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.070s	14.982us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.250s	515.189us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.250s	515.189us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.520s	132.603us	5	5	100.00
		keymgr_csr_rw	1.550s	26.071us	20	20	100.00
		keymgr_csr_aliasing	11.830s	468.335us	5	5	100.00
		keymgr_same_csr_outstanding	4.310s	103.569us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.520s	132.603us	5	5	100.00
		keymgr_csr_rw	1.550s	26.071us	20	20	100.00
		keymgr_csr_aliasing	11.830s	468.335us	5	5	100.00
		keymgr_same_csr_outstanding	4.310s	103.569us	20	20	100.00
V2		TOTAL			729	740	98.51
V2S	sec_cm_additional_check	keymgr_sec_cm	20.420s	833.724us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	20.420s	833.724us	5	5	100.00
		keymgr_tl_intg_err	33.160s	1.405ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	23.250s	4.067ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	23.250s	4.067ms	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	23.250s	4.067ms	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	23.250s	4.067ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.730s	512.623us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	20.420s	833.724us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	20.420s	833.724us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	33.160s	1.405ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	23.250s	4.067ms	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.826m	4.059ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	49.730s	5.478ms	50	50	100.00
		keymgr_csr_rw	1.550s	26.071us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	49.730s	5.478ms	50	50	100.00
		keymgr_csr_rw	1.550s	26.071us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	49.730s	5.478ms	50	50	100.00
		keymgr_csr_rw	1.550s	26.071us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	33.780s	2.097ms	48	50	96.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.843m	9.488ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.843m	9.488ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	49.730s	5.478ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	31.920s	6.892ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	20.420s	833.724us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	20.420s	833.724us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	20.420s	833.724us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	34.930s	2.489ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	33.780s	2.097ms	48	50	96.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	20.420s	833.724us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	20.420s	833.724us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	20.420s	833.724us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	34.930s	2.489ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	34.930s	2.489ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	20.420s	833.724us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	34.930s	2.489ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	20.420s	833.724us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	34.930s	2.489ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	23.130s	2.293ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			1068	1110	96.22

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	12	75.00
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.74	99.07	97.71	98.38	100.00	99.11	98.41	91.51

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test keymgr_stress_all_with_rand_reset has 21 failures.
  - 0.keymgr_stress_all_with_rand_reset.48409222641159522079924239663471484445013836733729467333174127030970525759401
    Line 468, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 142526889 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 142526889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.keymgr_stress_all_with_rand_reset.114768302905981919587348305417505458454208890046671274594343168355846970554087
    Line 1308, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2261944433 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2261944433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.
UVM_ERROR (keymgr_scoreboard.sv:736) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * [])` has 7 failures:
- Test keymgr_stress_all_with_rand_reset has 7 failures.
  - 10.keymgr_stress_all_with_rand_reset.65958334808665945830747685091616734244966254245182583699891602362179816646525
    Line 1323, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 442839513 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (840186433 [0x32143a41] vs 840186433 [0x32143a41])
  UVM_INFO @ 442839513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.keymgr_stress_all_with_rand_reset.6127325009719629412630325254478416251908915970347994011702855499266839373120
    Line 1770, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/20.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 863013620 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (2080675383 [0x7c049637] vs 2080675383 [0x7c049637])
  UVM_INFO @ 863013620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (keymgr_scoreboard.sv:1013) [scoreboard] Check failed act != exp (* [*] vs * [*]) cdi_type: Attestation has 5 failures:

Test keymgr_kmac_rsp_err has 5 failures.

2.keymgr_kmac_rsp_err.1060014297570104449005107227077053207228597501185950764636684697093740421302
Line 527, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @ 2687591280 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (6938975457274151898599221200894119174764607639093258569554072343397339906980461065017618952935001590981332517765966210326633957847088225401735972371668810058165943660000673124225965874142640350364895318301730792265079132970712360630065432763122220343324282955407410276879054567536240806969373167449788854553851404917499073780023211517868841755674117315263956183007544271028090352896239402583736910195980485190909457816980863 [0xfac8f0a6d157a020ed89b6b81072ff661f038d45d4a136036a46e17bfd0372e33a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f93de168236f624d2ccf3680d1979eacbf08801a90cef528eb2c676bebc82c62603d8b900dce70c42af1ac03ee6b57b71f54f2623e7a17fde8aa9f8e6392fdf63b37b974bd2e3711f83f1a173db3f48e6dbb3e3eaf894a13138f68007639e5517462cc37b789f537fad62d6a58a1658d7f] vs 6938975457274151898599221200894119174764607639093258569554072343397339906980461065017618952935001590981332517765966210326633957847088225401735972371668810058165943660000673124225965874142640350364895318301730792265079132970712360630065432763122220343324282955407410276879054567536240806969373167449788854553851404917499073780023211517868841755674117315263956183007544271028090352896239402583736910195980485190909457816980863 [0xfac8f0a6d157a020ed89b6b81072ff661f038d45d4a136036a46e17bfd0372e33a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f93de168236f624d2ccf3680d1979eacbf08801a90cef528eb2c676bebc82c62603d8b900dce70c42af1ac03ee6b57b71f54f2623e7a17fde8aa9f8e6392fdf63b37b974bd2e3711f83f1a173db3f48e6dbb3e3eaf894a13138f68007639e5517462cc37b789f537fad62d6a58a1658d7f]) cdi_type: Attestation
  
   DiversificationKey act: 0xbb3e3eaf894a13138f68007639e5517462cc37b789f537fad62d6a58a1658d7f, exp: 0xbb3e3eaf894a13138f68007639e5517462cc37b789f537fad62d6a58a1658d7f
   RomDigest act: 0x54f2623e7a17fde8aa9f8e6392fdf63b37b974bd2e3711f83f1a173db3f48e6d, exp: 0x54f2623e7a17fde8aa9f8e6392fdf63b37b974bd2e3711f83f1a173db3f48e6d
   HealthMeasurement act: 0x3d8b900dce70c42af1ac03ee6b57b71f, exp: 0x3d8b900dce70c42af1ac03ee6b57b71f

3.keymgr_kmac_rsp_err.62014347256982883718131209058790158047961920833299171480800905214445526921050
Line 364, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  56737200 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (52140057998489840148653011005703490350939319890447554486633366491673748264814371362703298735784250410939989355857914153525137759020197562785834448421489451019490653463596352510638009953504066450420136046711745427105678132420904211601695440166134371609813566162630447678145229984866890844079086596114203799694374399801842397991336917331236957950229449323723580217259822666140678747316217442552287653162134952597362 [0x817f0ec69aacffc71e7826572f4a35800000000745f4da5cdff0dd93a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f987fa7b79126ff93f559bb06d57473586f28c3efbadf1b3a5b4894e529ddde53d11005f28cc018e29248ea1c70d422e580d800db8149a55a8559b1bab349f8d6cbf7533fdcdc8a4ac2f61edf22f24f63fc2c1b492b981b725d42d8d0d37e14a783c44b5913946ddd40557592e9eb1d772] vs 52140057998489840148653011005703490350939319890447554486633366491673748264814371362703298735784250410939989355857914153525137759020197562785834448421489451019490653463596352510638009953504066450420136046711745427105678132420904211601695440166134371609813566162630447678145229984866890844079086596114203799694374399801842397991336917331236957950229449323723580217259822666140678747316217442552287653162134952597362 [0x817f0ec69aacffc71e7826572f4a35800000000745f4da5cdff0dd93a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f987fa7b79126ff93f559bb06d57473586f28c3efbadf1b3a5b4894e529ddde53d11005f28cc018e29248ea1c70d422e580d800db8149a55a8559b1bab349f8d6cbf7533fdcdc8a4ac2f61edf22f24f63fc2c1b492b981b725d42d8d0d37e14a783c44b5913946ddd40557592e9eb1d772]) cdi_type: Attestation
  
   DiversificationKey act: 0xc2c1b492b981b725d42d8d0d37e14a783c44b5913946ddd40557592e9eb1d772, exp: 0xc2c1b492b981b725d42d8d0d37e14a783c44b5913946ddd40557592e9eb1d772
   RomDigest act: 0xd800db8149a55a8559b1bab349f8d6cbf7533fdcdc8a4ac2f61edf22f24f63f, exp: 0xd800db8149a55a8559b1bab349f8d6cbf7533fdcdc8a4ac2f61edf22f24f63f
   HealthMeasurement act: 0x11005f28cc018e29248ea1c70d422e58, exp: 0x11005f28cc018e29248ea1c70d422e58

... and 3 more failures.

UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:

Test keymgr_sideload_kmac has 1 failures.

15.keymgr_sideload_kmac.113537701291988775919059815518190292406925876306581546461307034917157605244702
Line 263, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/15.keymgr_sideload_kmac/latest/run.log

  UVM_ERROR @   2437979 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   2437979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all has 2 failures.

19.keymgr_stress_all.87186032396112531485744667458928982730280143414652981654439230286974443512248
Line 4290, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/19.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 2161912935 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 2161912935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.keymgr_stress_all.36469641072744305531699685723282130090158051858617525654970056457584835735747
Line 1442, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/40.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 575933781 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @ 575933781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:674) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 6.keymgr_stress_all_with_rand_reset.57202046201092679588946258996295103511839397492743412686261901063739618392601
    Line 737, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 419078602 ps: (keymgr_scoreboard.sv:674) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 419078602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:753) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 11.keymgr_stress_all_with_rand_reset.15855150913157158979261279306315249263657705213647167699554496499429308904396
    Line 271, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 936078490 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 936078490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:671) [scoreboard] Check failed edn_fifos[*].used() == * (* [*] vs * [*]) has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 16.keymgr_lc_disable.58598966814078981375705322668003554311703682607361709081978281378533416831103
    Line 460, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/16.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  36837220 ps: (keymgr_scoreboard.sv:671) [uvm_test_top.env.scoreboard] Check failed edn_fifos[0].used() == 2 (0 [0x0] vs 2 [0x2])
  UVM_INFO @  36837220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 31.keymgr_lc_disable.38330445434069453434416681906905926446448278002022625431849038641579136596310
    Line 557, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/31.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @ 350059483 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (270363876 [0x101d6ce4] vs 550020621 [0x20c8a60d]) reg name: keymgr_reg_block.sw_share1_output_5
  UVM_INFO @ 350059483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:633) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 34.keymgr_stress_all.62195146305291706861717395221169010650995585636460188912300815949219642503383
    Line 2188, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/34.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 240863125 ps: (keymgr_scoreboard.sv:633) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (1 [0x1] vs 6 [0x6])
  UVM_INFO @ 240863125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 36.keymgr_stress_all_with_rand_reset.56620145617259660514592090074658552570796629023671926889626943221561177739817
    Line 512, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/36.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 226921262 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (714209737 [0x2a91f9c9] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_7
  UVM_INFO @ 226921262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```