Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4462997	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

618281

1

T1

209

T2

392

T3

333

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4686615	1			T1	755		T2	1563		T3	362
values[0x0]	196028	1			T1	43		T2	157		T3	142
values[0x1]	198635	1			T1	50		T2	169		T3	150

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3037422	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2043856

1

T1

391

T2

837

T3

398

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15826	1			T1	5		T2	5		T3	2
valid_sources[0x01]	15710	1			T1	6		T2	10		T3	4
valid_sources[0x02]	20228	1			T1	3		T2	10		T3	3
valid_sources[0x03]	15858	1			T1	3		T2	16		T3	3
valid_sources[0x04]	16254	1			T1	3		T2	2		T15	4
valid_sources[0x05]	15240	1			T1	7		T2	13		T3	4
valid_sources[0x06]	16494	1			T1	2		T2	10		T3	10
valid_sources[0x07]	15739	1			T1	5		T2	1		T3	3
valid_sources[0x08]	18306	1			T1	2		T2	15		T16	11
valid_sources[0x09]	17192	1			T1	4		T2	3		T3	1
valid_sources[0x0a]	20167	1			T1	2		T2	20		T3	3
valid_sources[0x0b]	15952	1			T1	7		T2	3		T3	1
valid_sources[0x0c]	27162	1			T1	2		T2	11		T3	1
valid_sources[0x0d]	16177	1			T1	4		T2	7		T3	2
valid_sources[0x0e]	16917	1			T1	1		T2	7		T3	2
valid_sources[0x0f]	111316	1			T1	1		T2	10		T3	1
valid_sources[0x10]	16691	1			T1	5		T2	7		T3	2
valid_sources[0x11]	17807	1			T1	7		T2	4		T3	3
valid_sources[0x12]	18703	1			T1	3		T2	6		T3	6
valid_sources[0x13]	16086	1			T1	7		T2	10		T3	2
valid_sources[0x14]	15918	1			T1	1		T2	13		T3	1
valid_sources[0x15]	15690	1			T1	5		T2	10		T15	2
valid_sources[0x16]	16645	1			T1	3		T2	5		T3	4
valid_sources[0x17]	24495	1			T1	5		T2	10		T3	2
valid_sources[0x18]	16606	1			T1	2		T2	6		T3	1
valid_sources[0x19]	15807	1			T1	2		T2	3		T3	4
valid_sources[0x1a]	20189	1			T1	3		T2	7		T3	1
valid_sources[0x1b]	19257	1			T1	3		T2	11		T15	4
valid_sources[0x1c]	17987	1			T1	5		T2	20		T3	2
valid_sources[0x1d]	23399	1			T1	5		T2	8		T3	3
valid_sources[0x1e]	17451	1			T1	4		T2	5		T3	4
valid_sources[0x1f]	16787	1			T1	3		T2	1		T3	5
valid_sources[0x20]	15419	1			T2	8		T15	2		T16	15
valid_sources[0x21]	20946	1			T1	4		T2	2		T3	3
valid_sources[0x22]	24073	1			T1	2		T2	5		T3	3
valid_sources[0x23]	18857	1			T1	2		T2	8		T3	2
valid_sources[0x24]	15859	1			T1	5		T2	3		T15	4
valid_sources[0x25]	19801	1			T1	3		T2	8		T3	2
valid_sources[0x26]	21227	1			T1	4		T2	9		T3	2
valid_sources[0x27]	20867	1			T1	1		T2	5		T3	2
valid_sources[0x28]	17485	1			T1	3		T2	6		T3	2
valid_sources[0x29]	16030	1			T1	2		T2	4		T3	8
valid_sources[0x2a]	16425	1			T1	2		T2	8		T15	2
valid_sources[0x2b]	16697	1			T1	3		T2	1		T15	2
valid_sources[0x2c]	15670	1			T1	3		T2	4		T3	8
valid_sources[0x2d]	17086	1			T1	6		T2	14		T3	6
valid_sources[0x2e]	22500	1			T1	4		T2	3		T3	1
valid_sources[0x2f]	16056	1			T1	5		T2	10		T3	2
valid_sources[0x30]	15930	1			T1	3		T2	8		T3	2
valid_sources[0x31]	24313	1			T1	5		T2	7		T3	2
valid_sources[0x32]	20219	1			T1	3		T2	4		T15	1
valid_sources[0x33]	37587	1			T1	3		T2	6		T3	3
valid_sources[0x34]	18327	1			T1	6		T2	11		T3	3
valid_sources[0x35]	15716	1			T2	3		T3	3		T15	2
valid_sources[0x36]	15424	1			T1	4		T2	5		T15	5
valid_sources[0x37]	16085	1			T1	4		T2	10		T3	10
valid_sources[0x38]	17283	1			T1	3		T2	5		T3	4
valid_sources[0x39]	16334	1			T2	8		T15	1		T16	13
valid_sources[0x3a]	16807	1			T1	3		T2	2		T3	4
valid_sources[0x3b]	23506	1			T1	4		T2	6		T15	4
valid_sources[0x3c]	17520	1			T1	4		T2	4		T3	2
valid_sources[0x3d]	17082	1			T1	3		T2	5		T3	1
valid_sources[0x3e]	15869	1			T1	6		T2	3		T3	8
valid_sources[0x3f]	22396	1			T2	9		T3	3		T15	2
valid_sources[0x40]	15765	1			T1	1		T2	9		T3	6
valid_sources[0x41]	18455	1			T1	1		T2	14		T3	3
valid_sources[0x42]	21793	1			T1	4		T2	9		T15	4
valid_sources[0x43]	16068	1			T1	2		T2	2		T3	8
valid_sources[0x44]	19779	1			T1	4		T2	8		T3	6
valid_sources[0x45]	15735	1			T1	1		T2	5		T15	3
valid_sources[0x46]	18397	1			T1	3		T2	8		T3	2
valid_sources[0x47]	17645	1			T1	3		T2	6		T3	4
valid_sources[0x48]	21989	1			T1	1		T2	8		T3	1
valid_sources[0x49]	57850	1			T1	4		T2	14		T3	4
valid_sources[0x4a]	16345	1			T1	2		T2	7		T15	3
valid_sources[0x4b]	20183	1			T1	2		T2	4		T3	4
valid_sources[0x4c]	19459	1			T1	7		T2	11		T3	1
valid_sources[0x4d]	23078	1			T1	1		T2	5		T3	1
valid_sources[0x4e]	18082	1			T1	3		T2	5		T3	1
valid_sources[0x4f]	15345	1			T1	7		T2	11		T3	1
valid_sources[0x50]	16338	1			T1	5		T2	14		T3	8
valid_sources[0x51]	22284	1			T1	1		T2	7		T15	6
valid_sources[0x52]	15545	1			T1	3		T2	7		T3	1
valid_sources[0x53]	16386	1			T1	2		T2	7		T3	6
valid_sources[0x54]	16075	1			T1	1		T2	6		T3	6
valid_sources[0x55]	17184	1			T1	4		T2	14		T3	4
valid_sources[0x56]	23294	1			T1	3		T2	8		T3	4
valid_sources[0x57]	21055	1			T1	4		T2	10		T3	1
valid_sources[0x58]	17806	1			T1	4		T2	17		T3	1
valid_sources[0x59]	15885	1			T1	5		T2	7		T3	4
valid_sources[0x5a]	25304	1			T1	6		T2	3		T3	4
valid_sources[0x5b]	15929	1			T1	5		T2	6		T3	4
valid_sources[0x5c]	20345	1			T1	6		T2	7		T3	3
valid_sources[0x5d]	16299	1			T1	6		T2	7		T3	3
valid_sources[0x5e]	18769	1			T1	1		T2	8		T3	4
valid_sources[0x5f]	17140	1			T1	8		T2	1		T3	1
valid_sources[0x60]	16889	1			T1	3		T2	9		T3	1
valid_sources[0x61]	15985	1			T1	7		T2	11		T3	3
valid_sources[0x62]	17900	1			T1	3		T2	9		T3	3
valid_sources[0x63]	18075	1			T1	2		T2	8		T3	5
valid_sources[0x64]	17273	1			T1	3		T2	14		T3	3
valid_sources[0x65]	20750	1			T1	2		T2	8		T3	2
valid_sources[0x66]	15842	1			T1	2		T2	9		T3	8
valid_sources[0x67]	17078	1			T1	8		T2	5		T3	2
valid_sources[0x68]	20734	1			T1	5		T2	9		T15	2
valid_sources[0x69]	18740	1			T1	3		T2	8		T3	2
valid_sources[0x6a]	22439	1			T1	5		T2	8		T3	2
valid_sources[0x6b]	24344	1			T1	4		T2	16		T3	1
valid_sources[0x6c]	16183	1			T2	6		T15	4		T16	13
valid_sources[0x6d]	17392	1			T1	3		T2	8		T3	3
valid_sources[0x6e]	24378	1			T1	2		T2	13		T3	1
valid_sources[0x6f]	15765	1			T2	9		T15	3		T16	14
valid_sources[0x70]	21673	1			T1	5		T2	5		T3	5
valid_sources[0x71]	16046	1			T1	3		T2	10		T3	4
valid_sources[0x72]	15868	1			T1	2		T2	9		T3	2
valid_sources[0x73]	17284	1			T1	4		T2	8		T3	8
valid_sources[0x74]	25194	1			T1	7		T2	8		T3	2
valid_sources[0x75]	16765	1			T1	7		T2	12		T3	2
valid_sources[0x76]	16252	1			T1	3		T2	3		T3	2
valid_sources[0x77]	50900	1			T1	5		T2	5		T3	4
valid_sources[0x78]	16793	1			T2	6		T3	1		T15	2
valid_sources[0x79]	16212	1			T1	9		T2	28		T3	1
valid_sources[0x7a]	17016	1			T1	3		T2	7		T3	2
valid_sources[0x7b]	15860	1			T1	2		T2	6		T3	6
valid_sources[0x7c]	16786	1			T1	1		T2	6		T3	1
valid_sources[0x7d]	19761	1			T1	4		T2	6		T3	2
valid_sources[0x7e]	17628	1			T1	1		T2	10		T3	4
valid_sources[0x7f]	15557	1			T1	7		T2	6		T15	3
valid_sources[0x80]	15563	1			T1	4		T2	6		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

351291

1

T1

182

T2

145

T3

139

values[0x0]

all_enables

biggest_size

140338

1

T1

15

T2

127

T3

101

values[0x1]

all_enables

biggest_size

126652

1

T1

12

T2

120

T3

93