Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
28055203 |
27894924 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
28055203 |
27894924 |
0 |
0 |
T1 |
3226 |
3135 |
0 |
0 |
T2 |
8605 |
8539 |
0 |
0 |
T3 |
6948 |
6851 |
0 |
0 |
T4 |
93415 |
93261 |
0 |
0 |
T13 |
1196 |
1115 |
0 |
0 |
T14 |
3714 |
3660 |
0 |
0 |
T15 |
6917 |
6858 |
0 |
0 |
T16 |
19576 |
19515 |
0 |
0 |
T17 |
156035 |
155951 |
0 |
0 |
T18 |
270339 |
270289 |
0 |
0 |