Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
26556222 |
26398864 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26556222 |
26398864 |
0 |
0 |
T1 |
1939 |
1746 |
0 |
0 |
T2 |
22550 |
22397 |
0 |
0 |
T3 |
10272 |
10216 |
0 |
0 |
T13 |
145084 |
144996 |
0 |
0 |
T14 |
5902 |
5804 |
0 |
0 |
T15 |
3485 |
3405 |
0 |
0 |
T16 |
8861 |
8737 |
0 |
0 |
T17 |
3604 |
3516 |
0 |
0 |
T18 |
154645 |
154542 |
0 |
0 |
T19 |
3261 |
3200 |
0 |
0 |