Line Coverage for Module :
keymgr_ctrl
| Line No. | Total | Covered | Percent |
TOTAL | | 184 | 184 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 152 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 165 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 185 | 1 | 1 | 100.00 |
CONT_ASSIGN | 186 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
CONT_ASSIGN | 206 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 214 | 1 | 1 | 100.00 |
CONT_ASSIGN | 229 | 1 | 1 | 100.00 |
CONT_ASSIGN | 237 | 1 | 1 | 100.00 |
ALWAYS | 243 | 3 | 3 | 100.00 |
ALWAYS | 246 | 3 | 3 | 100.00 |
CONT_ASSIGN | 257 | 1 | 1 | 100.00 |
CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
CONT_ASSIGN | 263 | 1 | 1 | 100.00 |
CONT_ASSIGN | 263 | 1 | 1 | 100.00 |
CONT_ASSIGN | 270 | 1 | 1 | 100.00 |
ALWAYS | 272 | 7 | 7 | 100.00 |
CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
CONT_ASSIGN | 305 | 1 | 1 | 100.00 |
CONT_ASSIGN | 328 | 1 | 1 | 100.00 |
ALWAYS | 331 | 21 | 21 | 100.00 |
CONT_ASSIGN | 415 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 427 | 1 | 1 | 100.00 |
CONT_ASSIGN | 433 | 1 | 1 | 100.00 |
ALWAYS | 437 | 73 | 73 | 100.00 |
ALWAYS | 655 | 4 | 4 | 100.00 |
ALWAYS | 663 | 12 | 12 | 100.00 |
ALWAYS | 699 | 5 | 5 | 100.00 |
CONT_ASSIGN | 737 | 1 | 1 | 100.00 |
CONT_ASSIGN | 743 | 1 | 1 | 100.00 |
CONT_ASSIGN | 774 | 1 | 1 | 100.00 |
ALWAYS | 782 | 3 | 3 | 100.00 |
CONT_ASSIGN | 792 | 1 | 1 | 100.00 |
ROUTINE | 839 | 1 | 1 | 100.00 |
ALWAYS | 881 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
149 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
152 |
1 |
1 |
154 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
168 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
201 |
1 |
1 |
206 |
1 |
1 |
212 |
1 |
1 |
214 |
1 |
1 |
229 |
1 |
1 |
237 |
1 |
1 |
243 |
3 |
3 |
246 |
1 |
1 |
247 |
1 |
1 |
249 |
1 |
1 |
257 |
1 |
1 |
259 |
1 |
1 |
263 |
2 |
2 |
270 |
1 |
1 |
272 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
276 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
279 |
1 |
1 |
298 |
16 |
16 |
305 |
1 |
1 |
328 |
1 |
1 |
331 |
1 |
1 |
332 |
1 |
1 |
333 |
1 |
1 |
337 |
1 |
1 |
339 |
1 |
1 |
340 |
1 |
1 |
343 |
1 |
1 |
349 |
1 |
1 |
350 |
1 |
1 |
351 |
1 |
1 |
352 |
1 |
1 |
353 |
1 |
1 |
355 |
|
unreachable |
357 |
|
unreachable |
362 |
1 |
1 |
363 |
1 |
1 |
364 |
1 |
1 |
370 |
1 |
1 |
371 |
1 |
1 |
375 |
1 |
1 |
376 |
1 |
1 |
377 |
1 |
1 |
378 |
1 |
1 |
415 |
1 |
1 |
426 |
1 |
1 |
427 |
1 |
1 |
433 |
1 |
1 |
437 |
1 |
1 |
440 |
1 |
1 |
441 |
1 |
1 |
442 |
1 |
1 |
445 |
1 |
1 |
448 |
1 |
1 |
451 |
1 |
1 |
454 |
1 |
1 |
457 |
1 |
1 |
460 |
1 |
1 |
463 |
1 |
1 |
466 |
1 |
1 |
470 |
1 |
1 |
472 |
1 |
1 |
475 |
1 |
1 |
479 |
1 |
1 |
483 |
1 |
1 |
486 |
1 |
1 |
487 |
1 |
1 |
488 |
1 |
1 |
489 |
1 |
1 |
|
|
|
MISSING_ELSE |
495 |
1 |
1 |
496 |
1 |
1 |
498 |
1 |
1 |
499 |
1 |
1 |
|
|
|
MISSING_ELSE |
505 |
1 |
1 |
506 |
1 |
1 |
511 |
1 |
1 |
512 |
|
unreachable |
513 |
|
unreachable |
|
|
|
MISSING_ELSE |
519 |
1 |
1 |
520 |
1 |
1 |
521 |
1 |
1 |
528 |
1 |
1 |
531 |
1 |
1 |
532 |
1 |
1 |
534 |
1 |
1 |
535 |
1 |
1 |
536 |
1 |
1 |
537 |
1 |
1 |
538 |
1 |
1 |
539 |
1 |
1 |
|
|
|
MISSING_ELSE |
545 |
1 |
1 |
550 |
1 |
1 |
553 |
1 |
1 |
554 |
1 |
1 |
555 |
1 |
1 |
556 |
1 |
1 |
557 |
1 |
1 |
558 |
1 |
1 |
|
|
|
MISSING_ELSE |
564 |
1 |
1 |
569 |
1 |
1 |
572 |
1 |
1 |
573 |
1 |
1 |
574 |
1 |
1 |
575 |
1 |
1 |
576 |
1 |
1 |
577 |
1 |
1 |
|
|
|
MISSING_ELSE |
584 |
1 |
1 |
589 |
1 |
1 |
591 |
1 |
1 |
592 |
1 |
1 |
593 |
1 |
1 |
594 |
1 |
1 |
|
|
|
MISSING_ELSE |
603 |
1 |
1 |
605 |
1 |
1 |
606 |
1 |
1 |
615 |
1 |
1 |
616 |
1 |
1 |
|
|
|
MISSING_ELSE |
627 |
1 |
1 |
628 |
1 |
1 |
630 |
1 |
1 |
631 |
1 |
1 |
|
|
|
MISSING_ELSE |
636 |
1 |
1 |
637 |
1 |
1 |
655 |
1 |
1 |
656 |
1 |
1 |
657 |
1 |
1 |
658 |
1 |
1 |
|
|
|
MISSING_ELSE |
663 |
1 |
1 |
664 |
1 |
1 |
666 |
1 |
1 |
668 |
1 |
1 |
671 |
1 |
1 |
674 |
1 |
1 |
677 |
1 |
1 |
680 |
1 |
1 |
683 |
1 |
1 |
686 |
1 |
1 |
687 |
1 |
1 |
691 |
1 |
1 |
699 |
1 |
1 |
700 |
1 |
1 |
704 |
1 |
1 |
705 |
1 |
1 |
706 |
1 |
1 |
|
|
|
MISSING_ELSE |
737 |
1 |
1 |
743 |
1 |
1 |
774 |
1 |
1 |
782 |
1 |
1 |
783 |
1 |
1 |
785 |
1 |
1 |
792 |
1 |
1 |
839 |
1 |
1 |
881 |
3 |
3 |
Cond Coverage for Module :
keymgr_ctrl
| Total | Covered | Percent |
Conditions | 206 | 202 | 98.06 |
Logical | 206 | 202 | 98.06 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 149
EXPRESSION (op_i == OpAdvance)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 150
EXPRESSION (op_i == OpGenId)
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (op_i == OpGenSwOut)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 152
EXPRESSION (op_i == OpGenHwOut)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 154
EXPRESSION (gen_id_op | gen_sw_op | gen_hw_op)
----1---- ----2---- ----3----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T1,T2,T3 |
1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (op_start_i & adv_op & en_i)
-----1---- ---2-- --3-
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T35,T36,T37 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 165
EXPRESSION (op_start_i & gen_hw_op & en_i)
-----1---- ----2---- --3-
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T5,T6,T38 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 168
EXPRESSION ((op_start_i & dis_op) | ((!en_i)))
----------1---------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T14,T18,T39 |
LINE 168
SUB-EXPRESSION (op_start_i & dis_op)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T18,T39 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T14,T18,T39 |
LINE 184
EXPRESSION (op_req & adv_op)
---1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 185
EXPRESSION (op_req & dis_op)
---1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T18,T39 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T14,T18,T39 |
LINE 186
EXPRESSION (op_req & gen_id_op)
---1-- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 187
EXPRESSION (op_req & (gen_sw_op | gen_hw_op))
---1-- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 187
SUB-EXPRESSION (gen_sw_op | gen_hw_op)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 201
EXPRESSION (adv_req & op_ack & ( ~ (op_err | op_fault_err) ))
---1--- ---2-- --------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T13 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T2,T3,T13 |
1 | 1 | 1 | Covered | T1,T2,T13 |
LINE 201
SUB-EXPRESSION (op_err | op_fault_err)
---1-- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T1,T2,T3 |
LINE 229
EXPRESSION (wipe_req ? KeyUpdateWipe : (random_req ? KeyUpdateRandom : (init_o ? KeyUpdateRoot : op_update_sel)))
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T16 |
LINE 229
SUB-EXPRESSION (random_req ? KeyUpdateRandom : (init_o ? KeyUpdateRoot : op_update_sel))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 229
SUB-EXPRESSION (init_o ? KeyUpdateRoot : op_update_sel)
---1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 237
EXPRESSION (random_req | disabled | invalid | wipe_req)
-----1---- ----2--- ---3--- ----4---
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Covered | T1,T2,T16 |
0 | 0 | 1 | 0 | Covered | T1,T2,T16 |
0 | 1 | 0 | 0 | Covered | T2,T13,T14 |
1 | 0 | 0 | 0 | Covered | T1,T2,T3 |
LINE 259
EXPRESSION (advance_sel ? cdi_cnt : op_cdi_sel_i)
-----1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 263
EXPRESSION (invalid_stage_sel_o ? ({EntropyRounds {entropy_i[0]}}) : key_state_q[cdi_sel_o][0])
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 263
EXPRESSION (invalid_stage_sel_o ? ({EntropyRounds {entropy_i[1]}}) : key_state_q[cdi_sel_o][1])
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 315
EXPRESSION (root_key_i.creator_root_key_share0_valid && root_key_i.creator_root_key_share1_valid)
--------------------1------------------- --------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T13 |
LINE 328
EXPRESSION (op_req ? cnt[0] : '0)
---1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 371
EXPRESSION ((adv_op || dis_op) ? kmac_data_i : key_state_q[cdi_sel_o])
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T13 |
1 | Covered | T1,T2,T13 |
LINE 371
SUB-EXPRESSION (adv_op || dis_op)
---1-- ---2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T13 |
0 | 1 | Covered | T14,T18,T39 |
1 | 0 | Covered | T1,T2,T13 |
LINE 390
EXPRESSION (op_ack | random_ack)
---1-- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 390
EXPRESSION (op_update | random_req)
----1---- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 415
EXPRESSION (op_req ? op_ack : (init_o | invalid_op))
---1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 415
SUB-EXPRESSION (init_o | invalid_op)
---1-- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T16 |
1 | 0 | Covered | T1,T2,T3 |
LINE 426
EXPRESSION (op_ack & adv_req & ((~op_err)))
---1-- ---2--- -----3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T13 |
1 | 1 | 0 | Covered | T2,T3,T13 |
1 | 1 | 1 | Covered | T1,T2,T13 |
LINE 427
EXPRESSION (op_ack & dis_req)
---1-- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T18,T39 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T14,T18,T39 |
LINE 483
EXPRESSION (op_start_i & ((~advance_sel)))
-----1---- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T16 |
LINE 511
EXPRESSION (int'(cnt) == (EntropyRounds - 1))
-----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | T1,T2,T3 |
LINE 521
EXPRESSION (en_i ? StCtrlInit : StCtrlWipe)
--1-
-1- | Status | Tests |
0 | Covered | T40 |
1 | Covered | T1,T2,T3 |
LINE 531
EXPRESSION (advance_sel ? Creator : Disable)
-----1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 532
EXPRESSION (op_start_i & ( ~ (advance_sel | disable_sel) ))
-----1---- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T13 |
LINE 532
SUB-EXPRESSION (advance_sel | disable_sel)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T14,T41,T42 |
1 | 0 | Covered | T1,T2,T3 |
LINE 534
EXPRESSION (((!en_i)) || inv_state)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T16,T31,T24 |
1 | 0 | Covered | T42,T5,T43 |
LINE 550
EXPRESSION (disable_sel ? Disable : (advance_sel ? OwnerInt : Creator))
-----1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T13 |
1 | Covered | T18,T44,T42 |
LINE 550
SUB-EXPRESSION (advance_sel ? OwnerInt : Creator)
-----1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T13 |
1 | Covered | T1,T2,T13 |
LINE 553
EXPRESSION (((!en_i)) || inv_state)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T13 |
0 | 1 | Covered | T45,T46,T47 |
1 | 0 | Covered | T44,T36,T37 |
LINE 569
EXPRESSION (disable_sel ? Disable : (advance_sel ? Owner : OwnerInt))
-----1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T13 |
1 | Covered | T48,T49,T50 |
LINE 569
SUB-EXPRESSION (advance_sel ? Owner : OwnerInt)
-----1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T13 |
1 | Covered | T2,T13,T15 |
LINE 572
EXPRESSION (((!en_i)) || inv_state)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T13 |
0 | 1 | Covered | T1,T25,T32 |
1 | 0 | Covered | T51,T52,T53 |
LINE 589
EXPRESSION ((disable_sel | advance_sel) ? Disable : Owner)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T2,T13,T15 |
1 | Covered | T2,T13,T15 |
LINE 589
SUB-EXPRESSION (disable_sel | advance_sel)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T13,T15 |
0 | 1 | Covered | T2,T13,T15 |
1 | 0 | Covered | T39,T35,T41 |
LINE 591
EXPRESSION (((!en_i)) || inv_state)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T13,T15 |
0 | 1 | Covered | T54,T8,T55 |
1 | 0 | Covered | T35,T36,T56 |
LINE 593
EXPRESSION (adv_state || dis_state)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T13,T15 |
0 | 1 | Covered | T39,T41,T42 |
1 | 0 | Covered | T2,T13,T15 |
LINE 630
EXPRESSION (((!en_i)) || inv_state)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T13,T14 |
0 | 1 | Covered | T2,T4,T27 |
1 | 0 | Covered | T41,T57,T37 |
LINE 704
EXPRESSION (((|{error_o, fault_o})) ? OpDoneFail : OpDoneSuccess)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 737
EXPRESSION ((adv_en_o & ( ~ (advance_sel | disable_sel) )) | (gen_en_o & ((~gen_op))))
-----------------------1---------------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T7,T8,T58 |
1 | 0 | Covered | T4,T26,T22 |
LINE 737
SUB-EXPRESSION (adv_en_o & ( ~ (advance_sel | disable_sel) ))
----1--- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T26,T20 |
LINE 737
SUB-EXPRESSION (advance_sel | disable_sel)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 737
SUB-EXPRESSION (gen_en_o & ((~gen_op)))
----1--- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T7,T20,T8 |
LINE 743
EXPRESSION
Number Term
1 ((op_ack | op_update) & invalid) ? KeyUpdateKmac : (((op_ack | op_update) & op_fault_err) ? KeyUpdateWipe : (((op_ack | op_update) & disabled) ? KeyUpdateKmac : (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T16,T25 |
LINE 743
SUB-EXPRESSION ((op_ack | op_update) & invalid)
----------1--------- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T16,T25 |
LINE 743
SUB-EXPRESSION (op_ack | op_update)
---1-- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 743
SUB-EXPRESSION
Number Term
1 ((op_ack | op_update) & op_fault_err) ? KeyUpdateWipe : (((op_ack | op_update) & disabled) ? KeyUpdateKmac : (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T16 |
LINE 743
SUB-EXPRESSION ((op_ack | op_update) & op_fault_err)
----------1--------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T16,T25 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T16 |
LINE 743
SUB-EXPRESSION (op_ack | op_update)
---1-- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 743
SUB-EXPRESSION
Number Term
1 ((op_ack | op_update) & disabled) ? KeyUpdateKmac : (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle)))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T13,T14 |
LINE 743
SUB-EXPRESSION ((op_ack | op_update) & disabled)
----------1--------- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T13,T14 |
LINE 743
SUB-EXPRESSION (op_ack | op_update)
---1-- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 743
SUB-EXPRESSION (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle))
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T13 |
LINE 743
SUB-EXPRESSION ((op_ack | op_update) & op_err)
----------1--------- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T13 |
1 | 1 | Covered | T1,T3,T13 |
LINE 743
SUB-EXPRESSION (op_ack | op_update)
---1-- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 743
SUB-EXPRESSION ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T13 |
LINE 743
SUB-EXPRESSION (op_ack | op_update)
---1-- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T13 |
1 | 0 | Covered | T1,T2,T13 |
LINE 774
EXPRESSION ((state_d != state_q) & (state_d inside {StCtrlRootKey, StCtrlCreatorRootKey, StCtrlOwnerIntKey, StCtrlOwnerKey}))
----------1--------- --------------------------------------------2--------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T13 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 774
SUB-EXPRESSION (state_d != state_q)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 792
EXPRESSION (vld_state_change_q & ((!adv_op)))
---------1-------- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Not Covered | |
LINE 794
EXPRESSION (disabled | (initialized & ((~en_i))))
----1--- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T44,T35,T41 |
1 | 0 | Covered | T2,T13,T14 |
LINE 794
SUB-EXPRESSION (initialized & ((~en_i)))
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T44,T35,T41 |
LINE 794
EXPRESSION (state_intg_err_q | state_intg_err_d)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T10,T11,T12 |
1 | 0 | Not Covered | |
FSM Coverage for Module :
keymgr_ctrl
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
11 |
11 |
100.00 |
(Not included in score) |
Transitions |
19 |
19 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
StCtrlCreatorRootKey |
539 |
Covered |
T1,T2,T13 |
StCtrlDisabled |
537 |
Covered |
T2,T13,T14 |
StCtrlEntropyReseed |
489 |
Covered |
T1,T2,T3 |
StCtrlInit |
521 |
Covered |
T1,T2,T3 |
StCtrlInvalid |
616 |
Covered |
T1,T2,T16 |
StCtrlOwnerIntKey |
558 |
Covered |
T1,T2,T13 |
StCtrlOwnerKey |
577 |
Covered |
T2,T13,T15 |
StCtrlRandom |
499 |
Covered |
T1,T2,T3 |
StCtrlReset |
474 |
Covered |
T1,T2,T3 |
StCtrlRootKey |
513 |
Covered |
T1,T2,T3 |
StCtrlWipe |
487 |
Covered |
T1,T2,T16 |
transitions | Line No. | Covered | Tests |
StCtrlCreatorRootKey->StCtrlDisabled |
556 |
Covered |
T18,T42,T59 |
StCtrlCreatorRootKey->StCtrlOwnerIntKey |
558 |
Covered |
T1,T2,T13 |
StCtrlCreatorRootKey->StCtrlWipe |
554 |
Covered |
T44,T45,T46 |
StCtrlDisabled->StCtrlWipe |
631 |
Covered |
T2,T4,T41 |
StCtrlEntropyReseed->StCtrlRandom |
499 |
Covered |
T1,T2,T3 |
StCtrlInit->StCtrlCreatorRootKey |
539 |
Covered |
T1,T2,T13 |
StCtrlInit->StCtrlDisabled |
537 |
Covered |
T14,T41,T60 |
StCtrlInit->StCtrlWipe |
535 |
Covered |
T16,T42,T31 |
StCtrlOwnerIntKey->StCtrlDisabled |
575 |
Covered |
T48,T49,T50 |
StCtrlOwnerIntKey->StCtrlOwnerKey |
577 |
Covered |
T2,T13,T15 |
StCtrlOwnerIntKey->StCtrlWipe |
573 |
Covered |
T1,T25,T32 |
StCtrlOwnerKey->StCtrlDisabled |
594 |
Covered |
T2,T13,T15 |
StCtrlOwnerKey->StCtrlWipe |
592 |
Covered |
T35,T54,T36 |
StCtrlRandom->StCtrlRootKey |
513 |
Covered |
T1,T2,T3 |
StCtrlReset->StCtrlEntropyReseed |
489 |
Covered |
T1,T2,T3 |
StCtrlReset->StCtrlWipe |
487 |
Covered |
T10,T61,T11 |
StCtrlRootKey->StCtrlInit |
521 |
Covered |
T1,T2,T3 |
StCtrlRootKey->StCtrlWipe |
521 |
Covered |
T40 |
StCtrlWipe->StCtrlInvalid |
616 |
Covered |
T1,T2,T16 |
Branch Coverage for Module :
keymgr_ctrl
| Line No. | Total | Covered | Percent |
Branches |
|
92 |
92 |
100.00 |
TERNARY |
229 |
4 |
4 |
100.00 |
TERNARY |
259 |
2 |
2 |
100.00 |
TERNARY |
328 |
2 |
2 |
100.00 |
TERNARY |
415 |
2 |
2 |
100.00 |
TERNARY |
743 |
6 |
6 |
100.00 |
TERNARY |
263 |
2 |
2 |
100.00 |
TERNARY |
263 |
2 |
2 |
100.00 |
IF |
243 |
2 |
2 |
100.00 |
IF |
246 |
2 |
2 |
100.00 |
IF |
272 |
2 |
2 |
100.00 |
CASE |
337 |
7 |
7 |
100.00 |
CASE |
472 |
39 |
39 |
100.00 |
IF |
655 |
3 |
3 |
100.00 |
CASE |
666 |
9 |
9 |
100.00 |
IF |
700 |
4 |
4 |
100.00 |
IF |
782 |
2 |
2 |
100.00 |
IF |
881 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 229 (wipe_req) ?
-2-: 229 (random_req) ?
-3-: 229 (init_o) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T16 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 259 (advance_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 328 (op_req) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 415 (op_req) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 743 (((op_ack | op_update) & invalid)) ?
-2-: 743 (((op_ack | op_update) & op_fault_err)) ?
-3-: 743 (((op_ack | op_update) & disabled)) ?
-4-: 743 (((op_ack | op_update) & op_err)) ?
-5-: 743 ((op_ack | op_update)) ?
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T2,T16,T25 |
0 |
1 |
- |
- |
- |
Covered |
T1,T2,T16 |
0 |
0 |
1 |
- |
- |
Covered |
T2,T13,T14 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T3,T13 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T13 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 263 (invalid_stage_sel_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 263 (invalid_stage_sel_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 243 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 246 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 272 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 337 case (update_sel)
-2-: 349 if (root_key_valid_q)
-3-: 371 ((adv_op || dis_op)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
KeyUpdateRandom |
- |
- |
Covered |
T1,T2,T3 |
KeyUpdateRoot |
1 |
- |
Covered |
T1,T2,T13 |
KeyUpdateRoot |
0 |
- |
Covered |
T3,T31,T23 |
KeyUpdateKmac |
- |
1 |
Covered |
T1,T2,T13 |
KeyUpdateKmac |
- |
0 |
Covered |
T1,T2,T13 |
KeyUpdateWipe |
- |
- |
Covered |
T1,T2,T16 |
default |
- |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 472 case (state_q)
-2-: 486 if (inv_state)
-3-: 488 if (advance_sel)
-4-: 498 if (prng_reseed_ack_i)
-5-: 511 if ((int'(cnt) == (EntropyRounds - 1)))
-6-: 521 (en_i) ?
-7-: 531 (advance_sel) ?
-8-: 534 if (((!en_i) || inv_state))
-9-: 536 if (dis_state)
-10-: 538 if (adv_state)
-11-: 550 (disable_sel) ?
-12-: 550 (advance_sel) ?
-13-: 553 if (((!en_i) || inv_state))
-14-: 555 if (dis_state)
-15-: 557 if (adv_state)
-16-: 569 (disable_sel) ?
-17-: 569 (advance_sel) ?
-18-: 572 if (((!en_i) || inv_state))
-19-: 574 if (dis_state)
-20-: 576 if (adv_state)
-21-: 589 ((disable_sel | advance_sel)) ?
-22-: 591 if (((!en_i) || inv_state))
-23-: 593 if ((adv_state || dis_state))
-24-: 615 if ((!op_start_i))
-25-: 630 if (((!en_i) || inv_state))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | -17- | -18- | -19- | -20- | -21- | -22- | -23- | -24- | -25- | Status | Tests |
StCtrlReset |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T61,T11 |
StCtrlReset |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StCtrlReset |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StCtrlEntropyReseed |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StCtrlEntropyReseed |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StCtrlRandom |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
T1,T2,T3 |
StCtrlRandom |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StCtrlRootKey |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StCtrlRootKey |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T40 |
StCtrlInit |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StCtrlInit |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StCtrlInit |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T16,T42,T31 |
StCtrlInit |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T14,T41,T60 |
StCtrlInit |
- |
- |
- |
- |
- |
- |
0 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T13 |
StCtrlInit |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StCtrlCreatorRootKey |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T44,T42 |
StCtrlCreatorRootKey |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T13 |
StCtrlCreatorRootKey |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T13 |
StCtrlCreatorRootKey |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T44,T45,T46 |
StCtrlCreatorRootKey |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T42,T59 |
StCtrlCreatorRootKey |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T13 |
StCtrlCreatorRootKey |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T13 |
StCtrlOwnerIntKey |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T48,T49,T50 |
StCtrlOwnerIntKey |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T13,T15 |
StCtrlOwnerIntKey |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T13 |
StCtrlOwnerIntKey |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T25,T32 |
StCtrlOwnerIntKey |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T48,T49,T50 |
StCtrlOwnerIntKey |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
1 |
- |
- |
- |
- |
- |
Covered |
T2,T13,T15 |
StCtrlOwnerIntKey |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T13 |
StCtrlOwnerKey |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T2,T13,T15 |
StCtrlOwnerKey |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
Covered |
T2,T13,T15 |
StCtrlOwnerKey |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T35,T54,T36 |
StCtrlOwnerKey |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
Covered |
T2,T13,T15 |
StCtrlOwnerKey |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
Covered |
T2,T13,T15 |
StCtrlWipe |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T1,T2,T16 |
StCtrlWipe |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T16,T35,T4 |
StCtrlDisabled |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T2,T4,T41 |
StCtrlDisabled |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T2,T13,T14 |
StCtrlInvalid |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T16 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T11,T12 |
LineNo. Expression
-1-: 655 if ((!rst_ni))
-2-: 657 if (update_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T16 |
LineNo. Expression
-1-: 666 case (state_q)
Branches:
-1- | Status | Tests |
StCtrlReset StCtrlEntropyReseed StCtrlRandom |
Covered |
T1,T2,T3 |
StCtrlRootKey StCtrlInit |
Covered |
T1,T2,T3 |
StCtrlCreatorRootKey |
Covered |
T1,T2,T13 |
StCtrlOwnerIntKey |
Covered |
T1,T2,T13 |
StCtrlOwnerKey |
Covered |
T2,T13,T15 |
StCtrlDisabled |
Covered |
T2,T13,T14 |
StCtrlWipe |
Covered |
T1,T2,T16 |
StCtrlInvalid |
Covered |
T1,T2,T16 |
default |
Covered |
T10,T11,T12 |
LineNo. Expression
-1-: 700 if (op_done_o)
-2-: 704 ((|{error_o, fault_o})) ?
-3-: 705 if (op_start_i)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T1,T2,T3 |
1 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 782 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 881 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
keymgr_ctrl
Assertion Details
CntZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25582265 |
27628 |
0 |
0 |
T1 |
1939 |
26 |
0 |
0 |
T2 |
2257 |
7 |
0 |
0 |
T3 |
10272 |
31 |
0 |
0 |
T13 |
145084 |
16 |
0 |
0 |
T14 |
5902 |
8 |
0 |
0 |
T15 |
3485 |
16 |
0 |
0 |
T16 |
5018 |
7 |
0 |
0 |
T17 |
3604 |
20 |
0 |
0 |
T18 |
154645 |
239 |
0 |
0 |
T19 |
3261 |
16 |
0 |
0 |
DataEnDis_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25060771 |
27081 |
0 |
0 |
T1 |
1939 |
26 |
0 |
0 |
T2 |
2257 |
7 |
0 |
0 |
T3 |
10272 |
31 |
0 |
0 |
T13 |
145084 |
16 |
0 |
0 |
T14 |
5902 |
8 |
0 |
0 |
T15 |
3485 |
16 |
0 |
0 |
T16 |
5018 |
6 |
0 |
0 |
T17 |
3604 |
20 |
0 |
0 |
T18 |
154645 |
239 |
0 |
0 |
T19 |
3261 |
16 |
0 |
0 |
DataEn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25060771 |
5927099 |
0 |
0 |
T1 |
1939 |
90 |
0 |
0 |
T2 |
2257 |
0 |
0 |
0 |
T3 |
10272 |
1390 |
0 |
0 |
T13 |
145084 |
27595 |
0 |
0 |
T14 |
5902 |
1249 |
0 |
0 |
T15 |
3485 |
67 |
0 |
0 |
T16 |
5018 |
102 |
0 |
0 |
T17 |
3604 |
545 |
0 |
0 |
T18 |
154645 |
362802 |
0 |
0 |
T19 |
3261 |
482 |
0 |
0 |
T30 |
0 |
580 |
0 |
0 |
GeneralLegalCommands_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26556222 |
22103 |
0 |
0 |
T20 |
7219 |
0 |
0 |
0 |
T36 |
39765 |
0 |
0 |
0 |
T37 |
103742 |
50 |
0 |
0 |
T52 |
0 |
12009 |
0 |
0 |
T56 |
11830 |
0 |
0 |
0 |
T59 |
42609 |
50 |
0 |
0 |
T62 |
0 |
232 |
0 |
0 |
T63 |
0 |
50 |
0 |
0 |
T64 |
0 |
1726 |
0 |
0 |
T65 |
0 |
2634 |
0 |
0 |
T66 |
0 |
50 |
0 |
0 |
T67 |
0 |
2375 |
0 |
0 |
T68 |
0 |
1348 |
0 |
0 |
T69 |
17231 |
0 |
0 |
0 |
T70 |
6936 |
0 |
0 |
0 |
T71 |
986 |
0 |
0 |
0 |
T72 |
5251 |
0 |
0 |
0 |
T73 |
6571 |
0 |
0 |
0 |
InitLegalCommands_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26556222 |
1296671 |
0 |
0 |
T1 |
1939 |
30 |
0 |
0 |
T2 |
22550 |
0 |
0 |
0 |
T3 |
10272 |
1436 |
0 |
0 |
T13 |
145084 |
919 |
0 |
0 |
T14 |
5902 |
1220 |
0 |
0 |
T15 |
3485 |
7 |
0 |
0 |
T16 |
8861 |
106 |
0 |
0 |
T17 |
3604 |
51 |
0 |
0 |
T18 |
154645 |
42058 |
0 |
0 |
T19 |
3261 |
88 |
0 |
0 |
T30 |
0 |
112 |
0 |
0 |
LoadKey_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26166996 |
19867252 |
0 |
0 |
T1 |
1939 |
208 |
0 |
0 |
T2 |
22550 |
12095 |
0 |
0 |
T3 |
10272 |
2488 |
0 |
0 |
T13 |
145084 |
140260 |
0 |
0 |
T14 |
5902 |
3305 |
0 |
0 |
T15 |
3485 |
433 |
0 |
0 |
T16 |
8861 |
1055 |
0 |
0 |
T17 |
3604 |
1496 |
0 |
0 |
T18 |
154645 |
146926 |
0 |
0 |
T19 |
3261 |
1744 |
0 |
0 |
OwnerLegalCommands_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26556222 |
1578392 |
0 |
0 |
T2 |
22550 |
1456 |
0 |
0 |
T3 |
10272 |
0 |
0 |
0 |
T13 |
145084 |
18852 |
0 |
0 |
T14 |
5902 |
0 |
0 |
0 |
T15 |
3485 |
50 |
0 |
0 |
T16 |
8861 |
0 |
0 |
0 |
T17 |
3604 |
142 |
0 |
0 |
T18 |
154645 |
147507 |
0 |
0 |
T19 |
3261 |
146 |
0 |
0 |
T30 |
2927 |
0 |
0 |
0 |
T74 |
0 |
951 |
0 |
0 |
T75 |
0 |
1963 |
0 |
0 |
T76 |
0 |
877 |
0 |
0 |
T77 |
0 |
2302 |
0 |
0 |
SameErrCnt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
865 |
865 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
SecCmCFILinear_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26556222 |
0 |
0 |
4842 |
StageDisableSel_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26556222 |
761591 |
0 |
0 |
T1 |
1939 |
37 |
0 |
0 |
T2 |
22550 |
1548 |
0 |
0 |
T3 |
10272 |
3 |
0 |
0 |
T13 |
145084 |
25 |
0 |
0 |
T14 |
5902 |
26 |
0 |
0 |
T15 |
3485 |
58 |
0 |
0 |
T16 |
8861 |
797 |
0 |
0 |
T17 |
3604 |
499 |
0 |
0 |
T18 |
154645 |
7157 |
0 |
0 |
T19 |
3261 |
48 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26556222 |
26398864 |
0 |
0 |
T1 |
1939 |
1746 |
0 |
0 |
T2 |
22550 |
22397 |
0 |
0 |
T3 |
10272 |
10216 |
0 |
0 |
T13 |
145084 |
144996 |
0 |
0 |
T14 |
5902 |
5804 |
0 |
0 |
T15 |
3485 |
3405 |
0 |
0 |
T16 |
8861 |
8737 |
0 |
0 |
T17 |
3604 |
3516 |
0 |
0 |
T18 |
154645 |
154542 |
0 |
0 |
T19 |
3261 |
3200 |
0 |
0 |