KEYMGR Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: `0cb61fc7e7`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	41.180s	1.708ms	50	50	100.00
V1	random	keymgr_random	53.410s	3.790ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.140s	59.048us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.600s	37.735us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	19.670s	858.649us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	14.450s	1.905ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.610s	146.396us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.600s	37.735us	20	20	100.00
		keymgr_csr_aliasing	14.450s	1.905ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.955m	2.160ms	50	50	100.00
V2	sideload	keymgr_sideload	44.410s	7.022ms	50	50	100.00
		keymgr_sideload_kmac	1.068m	2.058ms	50	50	100.00
		keymgr_sideload_aes	53.060s	2.077ms	49	50	98.00
		keymgr_sideload_otbn	36.590s	4.139ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	30.430s	15.579ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	5.580s	514.347us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.038m	40.468ms	45	50	90.00
V2	invalid_sw_input	keymgr_sw_invalid_input	43.070s	1.991ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	55.920s	11.472ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	30.320s	10.097ms	49	50	98.00
V2	stress_all	keymgr_stress_all	6.205m	96.653ms	50	50	100.00
V2	intr_test	keymgr_intr_test	0.910s	41.358us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.040s	65.776us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.560s	298.320us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.560s	298.320us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.140s	59.048us	5	5	100.00
		keymgr_csr_rw	1.600s	37.735us	20	20	100.00
		keymgr_csr_aliasing	14.450s	1.905ms	5	5	100.00
		keymgr_same_csr_outstanding	4.500s	862.395us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.140s	59.048us	5	5	100.00
		keymgr_csr_rw	1.600s	37.735us	20	20	100.00
		keymgr_csr_aliasing	14.450s	1.905ms	5	5	100.00
		keymgr_same_csr_outstanding	4.500s	862.395us	20	20	100.00
V2		TOTAL			732	740	98.92
V2S	sec_cm_additional_check	keymgr_sec_cm	3.345m	7.064ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	3.345m	7.064ms	5	5	100.00
		keymgr_tl_intg_err	34.310s	1.599ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	17.000s	993.340us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	17.000s	993.340us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	17.000s	993.340us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	17.000s	993.340us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.690s	433.732us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	3.345m	7.064ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	3.345m	7.064ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	34.310s	1.599ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	17.000s	993.340us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.955m	2.160ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	53.410s	3.790ms	50	50	100.00
		keymgr_csr_rw	1.600s	37.735us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	53.410s	3.790ms	50	50	100.00
		keymgr_csr_rw	1.600s	37.735us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	53.410s	3.790ms	50	50	100.00
		keymgr_csr_rw	1.600s	37.735us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	5.580s	514.347us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	55.920s	11.472ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	55.920s	11.472ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	53.410s	3.790ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	36.640s	3.312ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	3.345m	7.064ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	3.345m	7.064ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	3.345m	7.064ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	1.396m	4.763ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	5.580s	514.347us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	3.345m	7.064ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	3.345m	7.064ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	3.345m	7.064ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	1.396m	4.763ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	1.396m	4.763ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	3.345m	7.064ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	1.396m	4.763ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	3.345m	7.064ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	1.396m	4.763ms	49	50	98.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	22.130s	3.728ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			1070	1110	96.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	12	75.00
V2S	6	6	5	83.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.83	99.07	98.10	98.44	100.00	99.11	98.41	91.66

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test keymgr_stress_all_with_rand_reset has 27 failures.
  - 1.keymgr_stress_all_with_rand_reset.26961047368530718937068427819708447550095336177632697201261769939925439935916
    Line 311, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 445013059 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 445013059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.keymgr_stress_all_with_rand_reset.66989692956498381532662342067576258466855228970597317056357135485262654398522
    Line 629, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 848016831 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 848016831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.

UVM_ERROR (keymgr_scoreboard.sv:1013) [scoreboard] Check failed act != exp (* [*] vs * [*]) cdi_type: Attestation has 5 failures:

Test keymgr_kmac_rsp_err has 5 failures.

6.keymgr_kmac_rsp_err.890041479033163701379926027057288445466720549747662115483521012979312602740
Line 300, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  66930736 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (13869088684237589750254652523805745455607483863801036890679746459828093165537799588314215361270513115899118640132025363884310838304088735174803125982796589985776689453566159703017799500602332613046583076895746249403068864274579957134484888547034591383471797840616557256190761514941844428992899809589427557693523274592560989709361555825921855202503 [0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f954e0f568082653a2eb07f1548bfd0f2c83af08509f15dd767e4dfd086bff2b976c6939c1ccefb6bf687a6bb96a7b0fda97a997450b45cdb89ca83610f2782f932ad23e6ef0a3ba115d09085f62b3d3063b0db7e5ec77554d6be04aba50780ea5922b7d91cdfe9fbffaa280ee3f4624c7] vs 13869088684237589750254652523805745455607483863801036890679746459828093165537799588314215361270513115899118640132025363884310838304088735174803125982796589985776689453566159703017799500602332613046583076895746249403068864274579957134484888547034591383471797840616557256190761514941844428992899809589427557693523274592560989709361555825921855202503 [0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f954e0f568082653a2eb07f1548bfd0f2c83af08509f15dd767e4dfd086bff2b976c6939c1ccefb6bf687a6bb96a7b0fda97a997450b45cdb89ca83610f2782f932ad23e6ef0a3ba115d09085f62b3d3063b0db7e5ec77554d6be04aba50780ea5922b7d91cdfe9fbffaa280ee3f4624c7]) cdi_type: Attestation
  
   DiversificationKey act: 0x3b0db7e5ec77554d6be04aba50780ea5922b7d91cdfe9fbffaa280ee3f4624c7, exp: 0x3b0db7e5ec77554d6be04aba50780ea5922b7d91cdfe9fbffaa280ee3f4624c7
   RomDigest act: 0x97a997450b45cdb89ca83610f2782f932ad23e6ef0a3ba115d09085f62b3d306, exp: 0x97a997450b45cdb89ca83610f2782f932ad23e6ef0a3ba115d09085f62b3d306
   HealthMeasurement act: 0x6c6939c1ccefb6bf687a6bb96a7b0fda, exp: 0x6c6939c1ccefb6bf687a6bb96a7b0fda

7.keymgr_kmac_rsp_err.5811031072548694180955813885289272099706360692052796053171513452123329385991
Line 329, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/7.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  52583090 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (4240409571960324327966090285475185277575840375602766924686342041270136067899204797729841101887321494347964872641240245231158325353251946536541260313670944836331308207134447515320693219799049851705784897980047626336430942220869594199971353519000241481180587434772519134562347971653800705309809313918946316823057781674251406166590214319076921609107291631305542196933500884036578073002361088507298416626587958814036562867757409 [0x994135bcde78ca0f3d4a036f7f64667b36f8cb847e18d3fd5a75fd3e227c4aab3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9ac846dd4892d298896d4ca2e76ee7d66877484e22411007715bf5a16eca9a77a5be2d6eaa84c8ff5b0f5c23f644e2db84dcb76bca208db4a48d2d073fc97f8c36d898c834ad3d9468eebfdf73b7a21a8e4decded90108f2a1a7717b8d518c472163b317024487ecc4c12027bf701a161] vs 4240409571960324327966090285475185277575840375602766924686342041270136067899204797729841101887321494347964872641240245231158325353251946536541260313670944836331308207134447515320693219799049851705784897980047626336430942220869594199971353519000241481180587434772519134562347971653800705309809313918946316823057781674251406166590214319076921609107291631305542196933500884036578073002361088507298416626587958814036562867757409 [0x994135bcde78ca0f3d4a036f7f64667b36f8cb847e18d3fd5a75fd3e227c4aab3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9ac846dd4892d298896d4ca2e76ee7d66877484e22411007715bf5a16eca9a77a5be2d6eaa84c8ff5b0f5c23f644e2db84dcb76bca208db4a48d2d073fc97f8c36d898c834ad3d9468eebfdf73b7a21a8e4decded90108f2a1a7717b8d518c472163b317024487ecc4c12027bf701a161]) cdi_type: Attestation
  
   DiversificationKey act: 0xe4decded90108f2a1a7717b8d518c472163b317024487ecc4c12027bf701a161, exp: 0xe4decded90108f2a1a7717b8d518c472163b317024487ecc4c12027bf701a161
   RomDigest act: 0x4dcb76bca208db4a48d2d073fc97f8c36d898c834ad3d9468eebfdf73b7a21a8, exp: 0x4dcb76bca208db4a48d2d073fc97f8c36d898c834ad3d9468eebfdf73b7a21a8
   HealthMeasurement act: 0x5be2d6eaa84c8ff5b0f5c23f644e2db8, exp: 0x5be2d6eaa84c8ff5b0f5c23f644e2db8

... and 3 more failures.

UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 0.keymgr_sync_async_fault_cross.18572276758230953488403645797686833287456054117218016156516569731981806780258
    Line 303, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  16664593 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  16664593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_custom_cm has 1 failures.
  - 11.keymgr_custom_cm.11560650543793726269467388924885910892032873714263911630001398746523120864504
    Line 445, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/11.keymgr_custom_cm/latest/run.log
```
  UVM_ERROR @  32717642 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  32717642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_hwsw_invalid_input has 1 failures.
  - 39.keymgr_hwsw_invalid_input.91291776742462205953182772643804675609365194803116974393022038399826289717976
    Line 263, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/39.keymgr_hwsw_invalid_input/latest/run.log
```
  UVM_ERROR @   3655153 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   3655153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sideload_aes has 1 failures.
  - 40.keymgr_sideload_aes.108282007117926098509168626459199891673028538049483082279673412878235744767948
    Line 264, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/40.keymgr_sideload_aes/latest/run.log
```
  UVM_ERROR @   2341750 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   2341750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:736) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * [])` has 3 failures:
- Test keymgr_stress_all_with_rand_reset has 3 failures.
  - 0.keymgr_stress_all_with_rand_reset.60695118353344144373694941350442096265405833096258124439637981970713839383537
    Line 870, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2269884269 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (428957613 [0x19915fad] vs 428957613 [0x19915fad])
  UVM_INFO @ 2269884269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.keymgr_stress_all_with_rand_reset.114126983605573769273801278769989395684574930773490807834690951118774434214133
    Line 1619, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/30.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 598018112 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (2564720958 [0x98de893e] vs 2564720958 [0x98de893e])
  UVM_INFO @ 598018112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 42.keymgr_stress_all_with_rand_reset.74913013790564266019608779491656495977793460364086892180266271211326680842427
    Line 2218, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 212668109 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (1040822631 [0x3e09b167] vs 2422565289 [0x906569a9]) reg name: keymgr_reg_block.sw_share1_output_5
  UVM_INFO @ 212668109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```