SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_sideload_ctrl.u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[0].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[1].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[2].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[3].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[4].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[5].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[6].u_mubi_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_sw_assigns[7].u_mubi_buf | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | u_sideload_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.04 | 95.95 | 98.39 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.04 | 95.95 | 98.39 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.04 | 95.95 | 98.39 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.04 | 95.95 | 98.39 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.04 | 95.95 | 98.39 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.04 | 95.95 | 98.39 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.04 | 95.95 | 98.39 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.04 | 95.95 | 98.39 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 7965 | 7965 | 0 | 0 |
OutputsKnown_A | 242555049 | 241119756 | 0 | 0 |
gen_no_flops.OutputDelay_A | 242555049 | 241119756 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 7965 | 7965 | 0 | 0 |
T1 | 9 | 9 | 0 | 0 |
T2 | 9 | 9 | 0 | 0 |
T3 | 9 | 9 | 0 | 0 |
T4 | 9 | 9 | 0 | 0 |
T5 | 9 | 9 | 0 | 0 |
T6 | 9 | 9 | 0 | 0 |
T15 | 9 | 9 | 0 | 0 |
T16 | 9 | 9 | 0 | 0 |
T17 | 9 | 9 | 0 | 0 |
T18 | 9 | 9 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 242555049 | 241119756 | 0 | 0 |
T1 | 93969 | 93276 | 0 | 0 |
T2 | 13185 | 12393 | 0 | 0 |
T3 | 392805 | 391347 | 0 | 0 |
T4 | 1515474 | 1514979 | 0 | 0 |
T5 | 18855 | 18072 | 0 | 0 |
T6 | 386982 | 380538 | 0 | 0 |
T15 | 85608 | 84402 | 0 | 0 |
T16 | 303579 | 302985 | 0 | 0 |
T17 | 195624 | 194814 | 0 | 0 |
T18 | 64764 | 64224 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 242555049 | 241119756 | 0 | 0 |
T1 | 93969 | 93276 | 0 | 0 |
T2 | 13185 | 12393 | 0 | 0 |
T3 | 392805 | 391347 | 0 | 0 |
T4 | 1515474 | 1514979 | 0 | 0 |
T5 | 18855 | 18072 | 0 | 0 |
T6 | 386982 | 380538 | 0 | 0 |
T15 | 85608 | 84402 | 0 | 0 |
T16 | 303579 | 302985 | 0 | 0 |
T17 | 195624 | 194814 | 0 | 0 |
T18 | 64764 | 64224 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 885 | 885 | 0 | 0 |
OutputsKnown_A | 26950561 | 26791084 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26950561 | 26791084 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 885 | 885 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26950561 | 26791084 | 0 | 0 |
T1 | 10441 | 10364 | 0 | 0 |
T2 | 1465 | 1377 | 0 | 0 |
T3 | 43645 | 43483 | 0 | 0 |
T4 | 168386 | 168331 | 0 | 0 |
T5 | 2095 | 2008 | 0 | 0 |
T6 | 42998 | 42282 | 0 | 0 |
T15 | 9512 | 9378 | 0 | 0 |
T16 | 33731 | 33665 | 0 | 0 |
T17 | 21736 | 21646 | 0 | 0 |
T18 | 7196 | 7136 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26950561 | 26791084 | 0 | 0 |
T1 | 10441 | 10364 | 0 | 0 |
T2 | 1465 | 1377 | 0 | 0 |
T3 | 43645 | 43483 | 0 | 0 |
T4 | 168386 | 168331 | 0 | 0 |
T5 | 2095 | 2008 | 0 | 0 |
T6 | 42998 | 42282 | 0 | 0 |
T15 | 9512 | 9378 | 0 | 0 |
T16 | 33731 | 33665 | 0 | 0 |
T17 | 21736 | 21646 | 0 | 0 |
T18 | 7196 | 7136 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 885 | 885 | 0 | 0 |
OutputsKnown_A | 26950561 | 26791084 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26950561 | 26791084 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 885 | 885 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26950561 | 26791084 | 0 | 0 |
T1 | 10441 | 10364 | 0 | 0 |
T2 | 1465 | 1377 | 0 | 0 |
T3 | 43645 | 43483 | 0 | 0 |
T4 | 168386 | 168331 | 0 | 0 |
T5 | 2095 | 2008 | 0 | 0 |
T6 | 42998 | 42282 | 0 | 0 |
T15 | 9512 | 9378 | 0 | 0 |
T16 | 33731 | 33665 | 0 | 0 |
T17 | 21736 | 21646 | 0 | 0 |
T18 | 7196 | 7136 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26950561 | 26791084 | 0 | 0 |
T1 | 10441 | 10364 | 0 | 0 |
T2 | 1465 | 1377 | 0 | 0 |
T3 | 43645 | 43483 | 0 | 0 |
T4 | 168386 | 168331 | 0 | 0 |
T5 | 2095 | 2008 | 0 | 0 |
T6 | 42998 | 42282 | 0 | 0 |
T15 | 9512 | 9378 | 0 | 0 |
T16 | 33731 | 33665 | 0 | 0 |
T17 | 21736 | 21646 | 0 | 0 |
T18 | 7196 | 7136 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 885 | 885 | 0 | 0 |
OutputsKnown_A | 26950561 | 26791084 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26950561 | 26791084 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 885 | 885 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26950561 | 26791084 | 0 | 0 |
T1 | 10441 | 10364 | 0 | 0 |
T2 | 1465 | 1377 | 0 | 0 |
T3 | 43645 | 43483 | 0 | 0 |
T4 | 168386 | 168331 | 0 | 0 |
T5 | 2095 | 2008 | 0 | 0 |
T6 | 42998 | 42282 | 0 | 0 |
T15 | 9512 | 9378 | 0 | 0 |
T16 | 33731 | 33665 | 0 | 0 |
T17 | 21736 | 21646 | 0 | 0 |
T18 | 7196 | 7136 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26950561 | 26791084 | 0 | 0 |
T1 | 10441 | 10364 | 0 | 0 |
T2 | 1465 | 1377 | 0 | 0 |
T3 | 43645 | 43483 | 0 | 0 |
T4 | 168386 | 168331 | 0 | 0 |
T5 | 2095 | 2008 | 0 | 0 |
T6 | 42998 | 42282 | 0 | 0 |
T15 | 9512 | 9378 | 0 | 0 |
T16 | 33731 | 33665 | 0 | 0 |
T17 | 21736 | 21646 | 0 | 0 |
T18 | 7196 | 7136 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 885 | 885 | 0 | 0 |
OutputsKnown_A | 26950561 | 26791084 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26950561 | 26791084 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 885 | 885 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26950561 | 26791084 | 0 | 0 |
T1 | 10441 | 10364 | 0 | 0 |
T2 | 1465 | 1377 | 0 | 0 |
T3 | 43645 | 43483 | 0 | 0 |
T4 | 168386 | 168331 | 0 | 0 |
T5 | 2095 | 2008 | 0 | 0 |
T6 | 42998 | 42282 | 0 | 0 |
T15 | 9512 | 9378 | 0 | 0 |
T16 | 33731 | 33665 | 0 | 0 |
T17 | 21736 | 21646 | 0 | 0 |
T18 | 7196 | 7136 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26950561 | 26791084 | 0 | 0 |
T1 | 10441 | 10364 | 0 | 0 |
T2 | 1465 | 1377 | 0 | 0 |
T3 | 43645 | 43483 | 0 | 0 |
T4 | 168386 | 168331 | 0 | 0 |
T5 | 2095 | 2008 | 0 | 0 |
T6 | 42998 | 42282 | 0 | 0 |
T15 | 9512 | 9378 | 0 | 0 |
T16 | 33731 | 33665 | 0 | 0 |
T17 | 21736 | 21646 | 0 | 0 |
T18 | 7196 | 7136 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 885 | 885 | 0 | 0 |
OutputsKnown_A | 26950561 | 26791084 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26950561 | 26791084 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 885 | 885 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26950561 | 26791084 | 0 | 0 |
T1 | 10441 | 10364 | 0 | 0 |
T2 | 1465 | 1377 | 0 | 0 |
T3 | 43645 | 43483 | 0 | 0 |
T4 | 168386 | 168331 | 0 | 0 |
T5 | 2095 | 2008 | 0 | 0 |
T6 | 42998 | 42282 | 0 | 0 |
T15 | 9512 | 9378 | 0 | 0 |
T16 | 33731 | 33665 | 0 | 0 |
T17 | 21736 | 21646 | 0 | 0 |
T18 | 7196 | 7136 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26950561 | 26791084 | 0 | 0 |
T1 | 10441 | 10364 | 0 | 0 |
T2 | 1465 | 1377 | 0 | 0 |
T3 | 43645 | 43483 | 0 | 0 |
T4 | 168386 | 168331 | 0 | 0 |
T5 | 2095 | 2008 | 0 | 0 |
T6 | 42998 | 42282 | 0 | 0 |
T15 | 9512 | 9378 | 0 | 0 |
T16 | 33731 | 33665 | 0 | 0 |
T17 | 21736 | 21646 | 0 | 0 |
T18 | 7196 | 7136 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 885 | 885 | 0 | 0 |
OutputsKnown_A | 26950561 | 26791084 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26950561 | 26791084 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 885 | 885 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26950561 | 26791084 | 0 | 0 |
T1 | 10441 | 10364 | 0 | 0 |
T2 | 1465 | 1377 | 0 | 0 |
T3 | 43645 | 43483 | 0 | 0 |
T4 | 168386 | 168331 | 0 | 0 |
T5 | 2095 | 2008 | 0 | 0 |
T6 | 42998 | 42282 | 0 | 0 |
T15 | 9512 | 9378 | 0 | 0 |
T16 | 33731 | 33665 | 0 | 0 |
T17 | 21736 | 21646 | 0 | 0 |
T18 | 7196 | 7136 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26950561 | 26791084 | 0 | 0 |
T1 | 10441 | 10364 | 0 | 0 |
T2 | 1465 | 1377 | 0 | 0 |
T3 | 43645 | 43483 | 0 | 0 |
T4 | 168386 | 168331 | 0 | 0 |
T5 | 2095 | 2008 | 0 | 0 |
T6 | 42998 | 42282 | 0 | 0 |
T15 | 9512 | 9378 | 0 | 0 |
T16 | 33731 | 33665 | 0 | 0 |
T17 | 21736 | 21646 | 0 | 0 |
T18 | 7196 | 7136 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 885 | 885 | 0 | 0 |
OutputsKnown_A | 26950561 | 26791084 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26950561 | 26791084 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 885 | 885 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26950561 | 26791084 | 0 | 0 |
T1 | 10441 | 10364 | 0 | 0 |
T2 | 1465 | 1377 | 0 | 0 |
T3 | 43645 | 43483 | 0 | 0 |
T4 | 168386 | 168331 | 0 | 0 |
T5 | 2095 | 2008 | 0 | 0 |
T6 | 42998 | 42282 | 0 | 0 |
T15 | 9512 | 9378 | 0 | 0 |
T16 | 33731 | 33665 | 0 | 0 |
T17 | 21736 | 21646 | 0 | 0 |
T18 | 7196 | 7136 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26950561 | 26791084 | 0 | 0 |
T1 | 10441 | 10364 | 0 | 0 |
T2 | 1465 | 1377 | 0 | 0 |
T3 | 43645 | 43483 | 0 | 0 |
T4 | 168386 | 168331 | 0 | 0 |
T5 | 2095 | 2008 | 0 | 0 |
T6 | 42998 | 42282 | 0 | 0 |
T15 | 9512 | 9378 | 0 | 0 |
T16 | 33731 | 33665 | 0 | 0 |
T17 | 21736 | 21646 | 0 | 0 |
T18 | 7196 | 7136 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 885 | 885 | 0 | 0 |
OutputsKnown_A | 26950561 | 26791084 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26950561 | 26791084 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 885 | 885 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26950561 | 26791084 | 0 | 0 |
T1 | 10441 | 10364 | 0 | 0 |
T2 | 1465 | 1377 | 0 | 0 |
T3 | 43645 | 43483 | 0 | 0 |
T4 | 168386 | 168331 | 0 | 0 |
T5 | 2095 | 2008 | 0 | 0 |
T6 | 42998 | 42282 | 0 | 0 |
T15 | 9512 | 9378 | 0 | 0 |
T16 | 33731 | 33665 | 0 | 0 |
T17 | 21736 | 21646 | 0 | 0 |
T18 | 7196 | 7136 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26950561 | 26791084 | 0 | 0 |
T1 | 10441 | 10364 | 0 | 0 |
T2 | 1465 | 1377 | 0 | 0 |
T3 | 43645 | 43483 | 0 | 0 |
T4 | 168386 | 168331 | 0 | 0 |
T5 | 2095 | 2008 | 0 | 0 |
T6 | 42998 | 42282 | 0 | 0 |
T15 | 9512 | 9378 | 0 | 0 |
T16 | 33731 | 33665 | 0 | 0 |
T17 | 21736 | 21646 | 0 | 0 |
T18 | 7196 | 7136 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 885 | 885 | 0 | 0 |
OutputsKnown_A | 26950561 | 26791084 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26950561 | 26791084 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 885 | 885 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26950561 | 26791084 | 0 | 0 |
T1 | 10441 | 10364 | 0 | 0 |
T2 | 1465 | 1377 | 0 | 0 |
T3 | 43645 | 43483 | 0 | 0 |
T4 | 168386 | 168331 | 0 | 0 |
T5 | 2095 | 2008 | 0 | 0 |
T6 | 42998 | 42282 | 0 | 0 |
T15 | 9512 | 9378 | 0 | 0 |
T16 | 33731 | 33665 | 0 | 0 |
T17 | 21736 | 21646 | 0 | 0 |
T18 | 7196 | 7136 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26950561 | 26791084 | 0 | 0 |
T1 | 10441 | 10364 | 0 | 0 |
T2 | 1465 | 1377 | 0 | 0 |
T3 | 43645 | 43483 | 0 | 0 |
T4 | 168386 | 168331 | 0 | 0 |
T5 | 2095 | 2008 | 0 | 0 |
T6 | 42998 | 42282 | 0 | 0 |
T15 | 9512 | 9378 | 0 | 0 |
T16 | 33731 | 33665 | 0 | 0 |
T17 | 21736 | 21646 | 0 | 0 |
T18 | 7196 | 7136 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |