Line Coverage for Module :
keymgr
| Line No. | Total | Covered | Percent |
TOTAL | | 74 | 71 | 95.95 |
CONT_ASSIGN | 234 | 1 | 1 | 100.00 |
CONT_ASSIGN | 235 | 1 | 1 | 100.00 |
CONT_ASSIGN | 237 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 271 | 1 | 1 | 100.00 |
CONT_ASSIGN | 271 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 325 | 1 | 1 | 100.00 |
CONT_ASSIGN | 327 | 1 | 1 | 100.00 |
CONT_ASSIGN | 345 | 1 | 1 | 100.00 |
CONT_ASSIGN | 352 | 1 | 1 | 100.00 |
CONT_ASSIGN | 368 | 1 | 1 | 100.00 |
CONT_ASSIGN | 398 | 1 | 1 | 100.00 |
CONT_ASSIGN | 403 | 1 | 1 | 100.00 |
CONT_ASSIGN | 416 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 436 | 1 | 1 | 100.00 |
CONT_ASSIGN | 443 | 1 | 1 | 100.00 |
CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
CONT_ASSIGN | 458 | 1 | 1 | 100.00 |
CONT_ASSIGN | 460 | 1 | 1 | 100.00 |
CONT_ASSIGN | 461 | 1 | 1 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 469 | 1 | 1 | 100.00 |
CONT_ASSIGN | 472 | 1 | 0 | 0.00 |
CONT_ASSIGN | 473 | 1 | 0 | 0.00 |
CONT_ASSIGN | 474 | 1 | 0 | 0.00 |
CONT_ASSIGN | 482 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 486 | 1 | 1 | 100.00 |
CONT_ASSIGN | 488 | 1 | 1 | 100.00 |
CONT_ASSIGN | 498 | 1 | 1 | 100.00 |
CONT_ASSIGN | 499 | 1 | 1 | 100.00 |
CONT_ASSIGN | 500 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
CONT_ASSIGN | 538 | 1 | 1 | 100.00 |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
CONT_ASSIGN | 540 | 1 | 1 | 100.00 |
CONT_ASSIGN | 541 | 1 | 1 | 100.00 |
CONT_ASSIGN | 542 | 1 | 1 | 100.00 |
CONT_ASSIGN | 543 | 1 | 1 | 100.00 |
CONT_ASSIGN | 544 | 1 | 1 | 100.00 |
CONT_ASSIGN | 551 | 1 | 1 | 100.00 |
CONT_ASSIGN | 552 | 1 | 1 | 100.00 |
CONT_ASSIGN | 553 | 1 | 1 | 100.00 |
CONT_ASSIGN | 554 | 1 | 1 | 100.00 |
CONT_ASSIGN | 671 | 1 | 1 | 100.00 |
CONT_ASSIGN | 672 | 1 | 1 | 100.00 |
CONT_ASSIGN | 673 | 1 | 1 | 100.00 |
CONT_ASSIGN | 675 | 1 | 1 | 100.00 |
CONT_ASSIGN | 676 | 1 | 1 | 100.00 |
CONT_ASSIGN | 677 | 1 | 1 | 100.00 |
CONT_ASSIGN | 678 | 1 | 1 | 100.00 |
CONT_ASSIGN | 679 | 1 | 1 | 100.00 |
CONT_ASSIGN | 680 | 1 | 1 | 100.00 |
CONT_ASSIGN | 681 | 1 | 1 | 100.00 |
CONT_ASSIGN | 682 | 1 | 1 | 100.00 |
CONT_ASSIGN | 683 | 1 | 1 | 100.00 |
CONT_ASSIGN | 684 | 1 | 1 | 100.00 |
CONT_ASSIGN | 685 | 1 | 1 | 100.00 |
CONT_ASSIGN | 686 | 1 | 1 | 100.00 |
CONT_ASSIGN | 687 | 1 | 1 | 100.00 |
CONT_ASSIGN | 688 | 1 | 1 | 100.00 |
CONT_ASSIGN | 712 | 1 | 1 | 100.00 |
CONT_ASSIGN | 714 | 1 | 1 | 100.00 |
CONT_ASSIGN | 717 | 1 | 1 | 100.00 |
CONT_ASSIGN | 718 | 1 | 1 | 100.00 |
ALWAYS | 722 | 5 | 5 | 100.00 |
CONT_ASSIGN | 732 | 1 | 1 | 100.00 |
CONT_ASSIGN | 749 | 1 | 1 | 100.00 |
CONT_ASSIGN | 780 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
234 |
1 |
1 |
235 |
1 |
1 |
237 |
1 |
1 |
238 |
1 |
1 |
271 |
2 |
2 |
275 |
1 |
1 |
325 |
1 |
1 |
327 |
1 |
1 |
345 |
1 |
1 |
352 |
1 |
1 |
368 |
1 |
1 |
398 |
1 |
1 |
403 |
1 |
1 |
416 |
1 |
1 |
418 |
1 |
1 |
436 |
1 |
1 |
443 |
1 |
1 |
456 |
1 |
1 |
458 |
1 |
1 |
460 |
1 |
1 |
461 |
1 |
1 |
464 |
1 |
1 |
469 |
1 |
1 |
472 |
0 |
1 |
473 |
0 |
1 |
474 |
0 |
1 |
482 |
1 |
1 |
483 |
1 |
1 |
486 |
1 |
1 |
488 |
1 |
1 |
498 |
1 |
1 |
499 |
1 |
1 |
500 |
1 |
1 |
537 |
1 |
1 |
538 |
1 |
1 |
539 |
1 |
1 |
540 |
1 |
1 |
541 |
1 |
1 |
542 |
1 |
1 |
543 |
1 |
1 |
544 |
1 |
1 |
551 |
1 |
1 |
552 |
1 |
1 |
553 |
1 |
1 |
554 |
1 |
1 |
671 |
1 |
1 |
672 |
1 |
1 |
673 |
1 |
1 |
675 |
1 |
1 |
676 |
1 |
1 |
677 |
1 |
1 |
678 |
1 |
1 |
679 |
1 |
1 |
680 |
1 |
1 |
681 |
1 |
1 |
682 |
1 |
1 |
683 |
1 |
1 |
684 |
1 |
1 |
685 |
1 |
1 |
686 |
1 |
1 |
687 |
1 |
1 |
688 |
1 |
1 |
712 |
1 |
1 |
714 |
1 |
1 |
717 |
1 |
1 |
718 |
1 |
1 |
722 |
1 |
1 |
723 |
1 |
1 |
724 |
1 |
1 |
726 |
1 |
1 |
727 |
1 |
1 |
732 |
1 |
1 |
749 |
1 |
1 |
780 |
|
unreachable |
Cond Coverage for Module :
keymgr
| Total | Covered | Percent |
Conditions | 186 | 183 | 98.39 |
Logical | 186 | 183 | 98.39 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 214
EXPRESSION (ctrl_lfsr_en | data_lfsr_en | sideload_lfsr_en)
------1----- ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T3,T5 |
0 | 1 | 0 | Covered | T1,T3,T4 |
1 | 0 | 0 | Covered | T1,T3,T4 |
LINE 214
EXPRESSION (seed_en & ((~reg2hw.start.q)))
---1--- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T3,T6,T15 |
LINE 335
EXPRESSION (op_start & op_done)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T12,T13,T14 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 352
EXPRESSION (reg2hw.sw_binding_regwen.qe & ((~reg2hw.sw_binding_regwen.q)))
-------------1------------- ---------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T6,T15 |
1 | 1 | Covered | T3,T6,T15 |
LINE 368
EXPRESSION (sw_binding_regwen & cfg_regwen)
--------1-------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T6,T15 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 398
EXPRESSION ((cdi_sel == 1'b0) ? reg2hw.sealing_sw_binding : ((cdi_sel == 1'b1) ? reg2hw.attest_sw_binding : RndCnstCdi))
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 398
SUB-EXPRESSION (cdi_sel == 1'b0)
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 398
SUB-EXPRESSION ((cdi_sel == 1'b1) ? reg2hw.attest_sw_binding : RndCnstCdi)
--------1--------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T3,T4 |
LINE 398
SUB-EXPRESSION (cdi_sel == 1'b1)
--------1--------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T3,T4 |
LINE 443
EXPRESSION (creator_seed_vld & devid_vld & health_state_vld & rom_digest_vld)
--------1------- ----2---- --------3------- -------4------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T15,T52,T88 |
1 | 0 | 1 | 1 | Covered | T23,T25,T89 |
1 | 1 | 0 | 1 | Covered | T52,T23,T25 |
1 | 1 | 1 | 0 | Covered | T40,T52,T90 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 483
EXPRESSION ((dest_sel == Aes) ? aes_seed : ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed)))
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 483
SUB-EXPRESSION (dest_sel == Aes)
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 483
SUB-EXPRESSION ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed))
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 483
SUB-EXPRESSION (dest_sel == Kmac)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 483
SUB-EXPRESSION ((dest_sel == Otbn) ? otbn_seed : none_seed)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T6 |
LINE 483
SUB-EXPRESSION (dest_sel == Otbn)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T6 |
LINE 488
EXPRESSION (invalid_stage_sel ? ({GenLfsrCopies {lfsr[31:0]}}) : ({reg2hw.key_version, reg2hw.salt, dest_seed, output_key}))
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 537
EXPRESSION (adv_en | id_en | gen_en)
---1-- --2-- ---3--
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T3,T4 |
0 | 1 | 0 | Covered | T3,T4,T6 |
1 | 0 | 0 | Covered | T1,T3,T4 |
LINE 538
EXPRESSION (adv_en & (stage_sel == Creator) & ((~creator_seed_vld)))
---1-- -----------2---------- ----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T88,T91,T92 |
1 | 0 | 1 | Covered | T88,T93,T94 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T91,T92,T95 |
LINE 538
SUB-EXPRESSION (stage_sel == Creator)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 539
EXPRESSION (adv_en & (stage_sel == OwnerInt) & ((~owner_seed_vld)))
---1-- -----------2----------- ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T88,T89,T21 |
1 | 0 | 1 | Covered | T96,T23,T88 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T88,T21,T97 |
LINE 539
SUB-EXPRESSION (stage_sel == OwnerInt)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 540
EXPRESSION (adv_en & (stage_sel == Creator) & ((~devid_vld)))
---1-- -----------2---------- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T23,T25,T89 |
1 | 0 | 1 | Covered | T96,T23,T25 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T23,T89,T97 |
LINE 540
SUB-EXPRESSION (stage_sel == Creator)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 541
EXPRESSION (adv_en & (stage_sel == Creator) & ((~health_state_vld)))
---1-- -----------2---------- ----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T23,T25,T89 |
1 | 0 | 1 | Covered | T96,T21,T98 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T23,T25,T89 |
LINE 541
SUB-EXPRESSION (stage_sel == Creator)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 542
EXPRESSION (gen_en & ((~key_version_vld)))
---1-- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T6,T15 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T6,T27,T28 |
LINE 543
EXPRESSION (valid_op & ((~key_vld)))
----1--- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T20,T22,T26 |
LINE 544
EXPRESSION (adv_en & (stage_sel == Creator) & ((~rom_digest_vld)))
---1-- -----------2---------- ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T96,T23,T24 |
1 | 0 | 1 | Covered | T96,T23,T25 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T23,T24,T89 |
LINE 544
SUB-EXPRESSION (stage_sel == Creator)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 551
EXPRESSION (((~key_vld)) | ((~adv_dvalid[stage_sel])))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T23,T24,T25 |
1 | 0 | Covered | T1,T2,T3 |
LINE 553
EXPRESSION (((~key_vld)) | ((~key_version_vld)))
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T3,T6,T15 |
1 | 0 | Covered | T1,T2,T3 |
LINE 554
EXPRESSION (((~key_vld)) | ((~key_version_vld)))
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T3,T6,T15 |
1 | 0 | Covered | T1,T2,T3 |
LINE 624
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(0 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 624
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T6 |
0 | 1 | Covered | T56,T54,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 624
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(1 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 624
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T6 |
0 | 1 | Covered | T56,T54,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 624
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(2 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 624
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T6 |
0 | 1 | Covered | T56,T54,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 624
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(3 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 624
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T6 |
0 | 1 | Covered | T56,T54,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 624
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(4 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 624
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T6 |
0 | 1 | Covered | T56,T54,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 624
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(5 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 624
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T6 |
0 | 1 | Covered | T56,T54,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 624
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(6 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 624
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T6 |
0 | 1 | Covered | T56,T54,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 624
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(7 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 624
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T6 |
0 | 1 | Covered | T56,T54,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 631
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(0 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 631
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T6 |
0 | 1 | Covered | T56,T54,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 631
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(1 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 631
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T6 |
0 | 1 | Covered | T56,T54,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 631
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(2 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 631
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T6 |
0 | 1 | Covered | T56,T54,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 631
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(3 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 631
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T6 |
0 | 1 | Covered | T56,T54,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 631
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(4 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 631
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T6 |
0 | 1 | Covered | T56,T54,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 631
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(5 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 631
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T6 |
0 | 1 | Covered | T56,T54,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 631
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(6 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 631
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T6 |
0 | 1 | Covered | T56,T54,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 631
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(7 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 631
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T6 |
0 | 1 | Covered | T56,T54,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 714
EXPRESSION (fault_errs ? 1'b1 : (fault_err_ack ? 1'b0 : fault_err_req_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T15,T38,T27 |
LINE 714
SUB-EXPRESSION (fault_err_ack ? 1'b0 : fault_err_req_q)
------1------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 718
EXPRESSION (op_errs ? 1'b1 : (op_err_ack ? 1'b0 : op_err_req_q))
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 718
SUB-EXPRESSION (op_err_ack ? 1'b0 : op_err_req_q)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 732
EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
-----------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T99,T100 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T99,T100 |
LINE 749
EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
-------------------1------------------- --------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T99,T100 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T99,T100 |
Toggle Coverage for Module :
keymgr
| Total | Covered | Percent |
Totals |
67 |
65 |
97.01 |
Total Bits |
10068 |
10064 |
99.96 |
Total Bits 0->1 |
5034 |
5032 |
99.96 |
Total Bits 1->0 |
5034 |
5032 |
99.96 |
| | | |
Ports |
67 |
65 |
97.01 |
Port Bits |
10068 |
10064 |
99.96 |
Port Bits 0->1 |
5034 |
5032 |
99.96 |
Port Bits 1->0 |
5034 |
5032 |
99.96 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T3,T6,T15 |
Yes |
T1,T2,T3 |
INPUT |
rst_shadowed_ni |
Yes |
Yes |
T3,T6,T15 |
Yes |
T1,T2,T3 |
INPUT |
clk_edn_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_edn_ni |
Yes |
Yes |
T3,T6,T15 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T3,T4,T6 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T3,T4,T15 |
Yes |
T3,T4,T15 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T3,T4 |
INPUT |
tl_i.a_address[31:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_source[7:0] |
Yes |
Yes |
T2,T3,T4 |
Yes |
T2,T3,T4 |
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T3,T17,T38 |
Yes |
T3,T17,T38 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T1,*T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_source[7:0] |
Yes |
Yes |
T2,T3,T4 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T1,*T3,*T4 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1:0][255:0] |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T3,T5 |
OUTPUT |
aes_key_o.valid |
Yes |
Yes |
T1,T3,T6 |
Yes |
T1,T3,T6 |
OUTPUT |
kmac_key_o.key[1:0][255:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
kmac_key_o.valid |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
otbn_key_o.key[1:0][383:0] |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T3,T5 |
OUTPUT |
otbn_key_o.valid |
Yes |
Yes |
T3,T6,T16 |
Yes |
T3,T6,T16 |
OUTPUT |
kmac_data_o.last |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
kmac_data_o.strb[7:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
kmac_data_o.data[63:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
kmac_data_o.valid |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
kmac_data_i.error |
Yes |
Yes |
T15,T20,T29 |
Yes |
T38,T39,T56 |
INPUT |
kmac_data_i.digest_share1[383:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
kmac_data_i.digest_share0[383:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
kmac_data_i.done |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
kmac_data_i.ready |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T2,T3 |
INPUT |
kmac_en_masking_i |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
lc_keymgr_en_i[3:0] |
Yes |
Yes |
T3,T6,T17 |
Yes |
T1,T2,T3 |
INPUT |
lc_keymgr_div_i[127:0] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
otp_key_i.owner_seed_valid |
Yes |
Yes |
T3,T28,T76 |
Yes |
T3,T6,T28 |
INPUT |
otp_key_i.owner_seed[255:0] |
Yes |
Yes |
T3,T60,T76 |
Yes |
T3,T60,T28 |
INPUT |
otp_key_i.creator_seed_valid |
Yes |
Yes |
T3,T54,T76 |
Yes |
T3,T28,T76 |
INPUT |
otp_key_i.creator_seed[255:0] |
Yes |
Yes |
T3,T6,T60 |
Yes |
T3,T6,T60 |
INPUT |
otp_key_i.creator_root_key_share1_valid |
No |
No |
|
No |
|
INPUT |
otp_key_i.creator_root_key_share1[255:0] |
Yes |
Yes |
T3,T6,T60 |
Yes |
T3,T6,T60 |
INPUT |
otp_key_i.creator_root_key_share0_valid |
No |
No |
|
No |
|
INPUT |
otp_key_i.creator_root_key_share0[255:0] |
Yes |
Yes |
T3,T6,T60 |
Yes |
T3,T60,T28 |
INPUT |
otp_device_id_i[255:0] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][0] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][1] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][2] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][4:3] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][6:5] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][7] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][8] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][9] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][10] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][11] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][18:12] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][19] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][20] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][21] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][22] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][23] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][24] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][25] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][26] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][29:27] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][30] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][31] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][38:32] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][39] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][42:40] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][43] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][45:44] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][46] |
Yes |
Yes |
T3,T6,T17 |
Yes |
T3,T6,T17 |
INPUT |
flash_i.seeds[0][51:47] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][52] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][53] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][54] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][55] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][56] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][57] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][58] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][59] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][72:60] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][73] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][74] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][75] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][79:76] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][80] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][82:81] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][84:83] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][85] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][88:86] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][89] |
Yes |
Yes |
T3,T6,T17 |
Yes |
T3,T6,T17 |
INPUT |
flash_i.seeds[0][90] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][91] |
Yes |
Yes |
T3,T6,T17 |
Yes |
T3,T6,T17 |
INPUT |
flash_i.seeds[0][92] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][94:93] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][95] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][97:96] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][99:98] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][100] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][102:101] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][103] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][104] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][105] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][109:106] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][110] |
Yes |
Yes |
T3,T6,T17 |
Yes |
T3,T6,T17 |
INPUT |
flash_i.seeds[0][111] |
Yes |
Yes |
T3,T6,T17 |
Yes |
T3,T6,T17 |
INPUT |
flash_i.seeds[0][112] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][114:113] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][115] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][117:116] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][118] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][120:119] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][121] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][124:122] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][125] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][130:126] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][131] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][140:132] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][141] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][145:142] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][146] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][147] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][148] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][149] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][150] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][151] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][152] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][153] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][154] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][159:155] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][160] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][164:161] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][165] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][166] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][167] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][169:168] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][170] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][171] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][172] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][173] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][174] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][175] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][177:176] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][178] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][179] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][180] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][181] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][182] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][188:183] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][189] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][190] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][191] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][192] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][195:193] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][196] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][200:197] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][201] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][202] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][203] |
Yes |
Yes |
T3,T6,T17 |
Yes |
T3,T6,T17 |
INPUT |
flash_i.seeds[0][204] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][205] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][206] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][207] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][211:208] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][212] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][213] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][214] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][215] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][216] |
Yes |
Yes |
T3,T6,T17 |
Yes |
T3,T6,T17 |
INPUT |
flash_i.seeds[0][217] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][218] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][219] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][220] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][221] |
Yes |
Yes |
T3,T6,T17 |
Yes |
T3,T6,T17 |
INPUT |
flash_i.seeds[0][222] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][223] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][228:224] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][229] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][232:230] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][233] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][236:234] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][237] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][238] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][239] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][241:240] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][242] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][243] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][244] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][245] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][246] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][253:247] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][254] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[0][255] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][2:0] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][3] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][5:4] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][6] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][7] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][8] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][10:9] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][11] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][14:12] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][15] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][16] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][19:17] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][20] |
Yes |
Yes |
T3,T6,T17 |
Yes |
T3,T6,T17 |
INPUT |
flash_i.seeds[1][21] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][22] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][23] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][24] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][26:25] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][29:27] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][30] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][31] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][32] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][37:33] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][38] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][39] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][40] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][41] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][43:42] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][50:44] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][51] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][54:52] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][55] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][61:56] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][62] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][64:63] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][65] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][66] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][67] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][68] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][70:69] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][71] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][73:72] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][74] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][75] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][76] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][77] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][78] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][79] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][80] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][81] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][82] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][83] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][84] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][89:85] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][90] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][91] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][92] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][93] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][94] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][95] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][104:96] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][105] |
Yes |
Yes |
T3,T6,T17 |
Yes |
T3,T6,T17 |
INPUT |
flash_i.seeds[1][106] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][108:107] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][109] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][110] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][111] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][113:112] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][114] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][115] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][116] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][118:117] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][119] |
Yes |
Yes |
T3,T6,T17 |
Yes |
T3,T6,T17 |
INPUT |
flash_i.seeds[1][121:120] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][122] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][123] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][124] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][125] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][126] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][128:127] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][129] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][130] |
Yes |
Yes |
T3,T6,T17 |
Yes |
T3,T6,T17 |
INPUT |
flash_i.seeds[1][131] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][132] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][133] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][134] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][135] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][136] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][137] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][138] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][139] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][140] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][141] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][142] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][144:143] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][145] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][149:146] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][150] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][154:151] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][156:155] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][157] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][158] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][159] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][161:160] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][162] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][163] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][164] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][171:165] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][172] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][175:173] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][176] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][177] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][178] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][184:179] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][185] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][187:186] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][188] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][192:189] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][193] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][194] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][200:195] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][201] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][204:202] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][205] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][211:206] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][212] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][213] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][214] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][215] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][216] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][217] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][222:218] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][223] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][224] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][225] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][226] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][228:227] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][229] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][233:230] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][234] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][235] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][236] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][241:237] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][242] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][243] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][246:244] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][247] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][248] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][249] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][252:250] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][253] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
flash_i.seeds[1][255:254] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
edn_o.edn_req |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
edn_i.edn_bus[31:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T3,T4,T6 |
INPUT |
edn_i.edn_fips |
Yes |
Yes |
T3,T4,T6 |
Yes |
T1,T3,T4 |
INPUT |
edn_i.edn_ack |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
rom_digest_i.valid |
Yes |
Yes |
T40,T90,T96 |
Yes |
T96,T23,T101 |
INPUT |
rom_digest_i.data[255:0] |
Yes |
Yes |
T3,T6,T15 |
Yes |
T3,T6,T15 |
INPUT |
intr_op_done_o |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[1].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[1].ack_p |
Yes |
Yes |
T2,T15,T38 |
Yes |
T2,T15,T38 |
INPUT |
alert_rx_i[1].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[1].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[1].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[1].alert_p |
Yes |
Yes |
T2,T15,T38 |
Yes |
T2,T15,T38 |
OUTPUT |
*Tests covering at least one bit in the range
Branch Coverage for Module :
keymgr
| Line No. | Total | Covered | Percent |
Branches |
|
49 |
47 |
95.92 |
TERNARY |
398 |
3 |
2 |
66.67 |
TERNARY |
483 |
4 |
4 |
100.00 |
TERNARY |
488 |
2 |
2 |
100.00 |
TERNARY |
714 |
3 |
2 |
66.67 |
TERNARY |
718 |
3 |
3 |
100.00 |
TERNARY |
624 |
2 |
2 |
100.00 |
TERNARY |
631 |
2 |
2 |
100.00 |
TERNARY |
624 |
2 |
2 |
100.00 |
TERNARY |
631 |
2 |
2 |
100.00 |
TERNARY |
624 |
2 |
2 |
100.00 |
TERNARY |
631 |
2 |
2 |
100.00 |
TERNARY |
624 |
2 |
2 |
100.00 |
TERNARY |
631 |
2 |
2 |
100.00 |
TERNARY |
624 |
2 |
2 |
100.00 |
TERNARY |
631 |
2 |
2 |
100.00 |
TERNARY |
624 |
2 |
2 |
100.00 |
TERNARY |
631 |
2 |
2 |
100.00 |
TERNARY |
624 |
2 |
2 |
100.00 |
TERNARY |
631 |
2 |
2 |
100.00 |
TERNARY |
624 |
2 |
2 |
100.00 |
TERNARY |
631 |
2 |
2 |
100.00 |
IF |
722 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 398 ((cdi_sel == 1'b0)) ?
-2-: 398 ((cdi_sel == 1'b1)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 483 ((dest_sel == Aes)) ?
-2-: 483 ((dest_sel == Kmac)) ?
-3-: 483 ((dest_sel == Otbn)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T3,T4 |
0 |
1 |
- |
Covered |
T3,T4,T5 |
0 |
0 |
1 |
Covered |
T3,T4,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 488 (invalid_stage_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 714 (fault_errs) ?
-2-: 714 (fault_err_ack) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T15,T38,T27 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 718 (op_errs) ?
-2-: 718 (op_err_ack) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T3,T4 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 624 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T6 |
LineNo. Expression
-1-: 631 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T6 |
LineNo. Expression
-1-: 624 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T6 |
LineNo. Expression
-1-: 631 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T6 |
LineNo. Expression
-1-: 624 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T6 |
LineNo. Expression
-1-: 631 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T6 |
LineNo. Expression
-1-: 624 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T6 |
LineNo. Expression
-1-: 631 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T6 |
LineNo. Expression
-1-: 624 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T6 |
LineNo. Expression
-1-: 631 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T6 |
LineNo. Expression
-1-: 624 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T6 |
LineNo. Expression
-1-: 631 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T6 |
LineNo. Expression
-1-: 624 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T6 |
LineNo. Expression
-1-: 631 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T6 |
LineNo. Expression
-1-: 624 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T6 |
LineNo. Expression
-1-: 631 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T6 |
LineNo. Expression
-1-: 722 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
keymgr
Assertion Details
AdvDataWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
885 |
885 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
AesKeyKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26950561 |
26791084 |
0 |
0 |
T1 |
10441 |
10364 |
0 |
0 |
T2 |
1465 |
1377 |
0 |
0 |
T3 |
43645 |
43483 |
0 |
0 |
T4 |
168386 |
168331 |
0 |
0 |
T5 |
2095 |
2008 |
0 |
0 |
T6 |
42998 |
42282 |
0 |
0 |
T15 |
9512 |
9378 |
0 |
0 |
T16 |
33731 |
33665 |
0 |
0 |
T17 |
21736 |
21646 |
0 |
0 |
T18 |
7196 |
7136 |
0 |
0 |
AlertKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26950561 |
26791084 |
0 |
0 |
T1 |
10441 |
10364 |
0 |
0 |
T2 |
1465 |
1377 |
0 |
0 |
T3 |
43645 |
43483 |
0 |
0 |
T4 |
168386 |
168331 |
0 |
0 |
T5 |
2095 |
2008 |
0 |
0 |
T6 |
42998 |
42282 |
0 |
0 |
T15 |
9512 |
9378 |
0 |
0 |
T16 |
33731 |
33665 |
0 |
0 |
T17 |
21736 |
21646 |
0 |
0 |
T18 |
7196 |
7136 |
0 |
0 |
ErrCntMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
885 |
885 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
FaultCntMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
885 |
885 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
FpvSecCmCtrlCntAlertCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26950561 |
70 |
0 |
0 |
T12 |
60868 |
20 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
10 |
0 |
0 |
T29 |
17971 |
0 |
0 |
0 |
T46 |
0 |
10 |
0 |
0 |
T47 |
0 |
10 |
0 |
0 |
T100 |
1298 |
0 |
0 |
0 |
T102 |
17920 |
0 |
0 |
0 |
T103 |
2789 |
0 |
0 |
0 |
T104 |
10666 |
0 |
0 |
0 |
T105 |
3187 |
0 |
0 |
0 |
T106 |
1875 |
0 |
0 |
0 |
T107 |
2445 |
0 |
0 |
0 |
T108 |
6046 |
0 |
0 |
0 |
FpvSecCmCtrlDataFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26950561 |
70 |
0 |
0 |
T12 |
60868 |
20 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
10 |
0 |
0 |
T29 |
17971 |
0 |
0 |
0 |
T46 |
0 |
10 |
0 |
0 |
T47 |
0 |
10 |
0 |
0 |
T100 |
1298 |
0 |
0 |
0 |
T102 |
17920 |
0 |
0 |
0 |
T103 |
2789 |
0 |
0 |
0 |
T104 |
10666 |
0 |
0 |
0 |
T105 |
3187 |
0 |
0 |
0 |
T106 |
1875 |
0 |
0 |
0 |
T107 |
2445 |
0 |
0 |
0 |
T108 |
6046 |
0 |
0 |
0 |
FpvSecCmCtrlMainFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26950561 |
70 |
0 |
0 |
T12 |
60868 |
20 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
10 |
0 |
0 |
T29 |
17971 |
0 |
0 |
0 |
T46 |
0 |
10 |
0 |
0 |
T47 |
0 |
10 |
0 |
0 |
T100 |
1298 |
0 |
0 |
0 |
T102 |
17920 |
0 |
0 |
0 |
T103 |
2789 |
0 |
0 |
0 |
T104 |
10666 |
0 |
0 |
0 |
T105 |
3187 |
0 |
0 |
0 |
T106 |
1875 |
0 |
0 |
0 |
T107 |
2445 |
0 |
0 |
0 |
T108 |
6046 |
0 |
0 |
0 |
FpvSecCmCtrlOpFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26950561 |
70 |
0 |
0 |
T12 |
60868 |
20 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
10 |
0 |
0 |
T29 |
17971 |
0 |
0 |
0 |
T46 |
0 |
10 |
0 |
0 |
T47 |
0 |
10 |
0 |
0 |
T100 |
1298 |
0 |
0 |
0 |
T102 |
17920 |
0 |
0 |
0 |
T103 |
2789 |
0 |
0 |
0 |
T104 |
10666 |
0 |
0 |
0 |
T105 |
3187 |
0 |
0 |
0 |
T106 |
1875 |
0 |
0 |
0 |
T107 |
2445 |
0 |
0 |
0 |
T108 |
6046 |
0 |
0 |
0 |
FpvSecCmKmacIfCntAlertCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26950561 |
70 |
0 |
0 |
T12 |
60868 |
20 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
10 |
0 |
0 |
T29 |
17971 |
0 |
0 |
0 |
T46 |
0 |
10 |
0 |
0 |
T47 |
0 |
10 |
0 |
0 |
T100 |
1298 |
0 |
0 |
0 |
T102 |
17920 |
0 |
0 |
0 |
T103 |
2789 |
0 |
0 |
0 |
T104 |
10666 |
0 |
0 |
0 |
T105 |
3187 |
0 |
0 |
0 |
T106 |
1875 |
0 |
0 |
0 |
T107 |
2445 |
0 |
0 |
0 |
T108 |
6046 |
0 |
0 |
0 |
FpvSecCmKmacIfFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26950561 |
70 |
0 |
0 |
T12 |
60868 |
20 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
10 |
0 |
0 |
T29 |
17971 |
0 |
0 |
0 |
T46 |
0 |
10 |
0 |
0 |
T47 |
0 |
10 |
0 |
0 |
T100 |
1298 |
0 |
0 |
0 |
T102 |
17920 |
0 |
0 |
0 |
T103 |
2789 |
0 |
0 |
0 |
T104 |
10666 |
0 |
0 |
0 |
T105 |
3187 |
0 |
0 |
0 |
T106 |
1875 |
0 |
0 |
0 |
T107 |
2445 |
0 |
0 |
0 |
T108 |
6046 |
0 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26950561 |
70 |
0 |
0 |
T12 |
60868 |
20 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
10 |
0 |
0 |
T29 |
17971 |
0 |
0 |
0 |
T46 |
0 |
10 |
0 |
0 |
T47 |
0 |
10 |
0 |
0 |
T100 |
1298 |
0 |
0 |
0 |
T102 |
17920 |
0 |
0 |
0 |
T103 |
2789 |
0 |
0 |
0 |
T104 |
10666 |
0 |
0 |
0 |
T105 |
3187 |
0 |
0 |
0 |
T106 |
1875 |
0 |
0 |
0 |
T107 |
2445 |
0 |
0 |
0 |
T108 |
6046 |
0 |
0 |
0 |
FpvSecCmReseedCtrlCntAlertCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26950561 |
70 |
0 |
0 |
T12 |
60868 |
20 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
10 |
0 |
0 |
T29 |
17971 |
0 |
0 |
0 |
T46 |
0 |
10 |
0 |
0 |
T47 |
0 |
10 |
0 |
0 |
T100 |
1298 |
0 |
0 |
0 |
T102 |
17920 |
0 |
0 |
0 |
T103 |
2789 |
0 |
0 |
0 |
T104 |
10666 |
0 |
0 |
0 |
T105 |
3187 |
0 |
0 |
0 |
T106 |
1875 |
0 |
0 |
0 |
T107 |
2445 |
0 |
0 |
0 |
T108 |
6046 |
0 |
0 |
0 |
FpvSecCmSideloadCtrlFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26950561 |
70 |
0 |
0 |
T12 |
60868 |
20 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
10 |
0 |
0 |
T29 |
17971 |
0 |
0 |
0 |
T46 |
0 |
10 |
0 |
0 |
T47 |
0 |
10 |
0 |
0 |
T100 |
1298 |
0 |
0 |
0 |
T102 |
17920 |
0 |
0 |
0 |
T103 |
2789 |
0 |
0 |
0 |
T104 |
10666 |
0 |
0 |
0 |
T105 |
3187 |
0 |
0 |
0 |
T106 |
1875 |
0 |
0 |
0 |
T107 |
2445 |
0 |
0 |
0 |
T108 |
6046 |
0 |
0 |
0 |
GenDataWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
885 |
885 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
IdDataWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
885 |
885 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
IntrKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26950561 |
26791084 |
0 |
0 |
T1 |
10441 |
10364 |
0 |
0 |
T2 |
1465 |
1377 |
0 |
0 |
T3 |
43645 |
43483 |
0 |
0 |
T4 |
168386 |
168331 |
0 |
0 |
T5 |
2095 |
2008 |
0 |
0 |
T6 |
42998 |
42282 |
0 |
0 |
T15 |
9512 |
9378 |
0 |
0 |
T16 |
33731 |
33665 |
0 |
0 |
T17 |
21736 |
21646 |
0 |
0 |
T18 |
7196 |
7136 |
0 |
0 |
KmacDataKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26578451 |
26422501 |
0 |
0 |
T1 |
10441 |
10364 |
0 |
0 |
T2 |
1465 |
1377 |
0 |
0 |
T3 |
43645 |
43483 |
0 |
0 |
T4 |
168386 |
168331 |
0 |
0 |
T5 |
2095 |
2008 |
0 |
0 |
T6 |
42998 |
42282 |
0 |
0 |
T15 |
9512 |
9378 |
0 |
0 |
T16 |
33731 |
33665 |
0 |
0 |
T17 |
21736 |
21646 |
0 |
0 |
T18 |
7196 |
7136 |
0 |
0 |
KmacKeyKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26950561 |
26791084 |
0 |
0 |
T1 |
10441 |
10364 |
0 |
0 |
T2 |
1465 |
1377 |
0 |
0 |
T3 |
43645 |
43483 |
0 |
0 |
T4 |
168386 |
168331 |
0 |
0 |
T5 |
2095 |
2008 |
0 |
0 |
T6 |
42998 |
42282 |
0 |
0 |
T15 |
9512 |
9378 |
0 |
0 |
T16 |
33731 |
33665 |
0 |
0 |
T17 |
21736 |
21646 |
0 |
0 |
T18 |
7196 |
7136 |
0 |
0 |
KmacMaskCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
885 |
885 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
LfsrWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
885 |
885 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OtbnKeyKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26950561 |
26791084 |
0 |
0 |
T1 |
10441 |
10364 |
0 |
0 |
T2 |
1465 |
1377 |
0 |
0 |
T3 |
43645 |
43483 |
0 |
0 |
T4 |
168386 |
168331 |
0 |
0 |
T5 |
2095 |
2008 |
0 |
0 |
T6 |
42998 |
42282 |
0 |
0 |
T15 |
9512 |
9378 |
0 |
0 |
T16 |
33731 |
33665 |
0 |
0 |
T17 |
21736 |
21646 |
0 |
0 |
T18 |
7196 |
7136 |
0 |
0 |
OutputKeyDiff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
885 |
885 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
StageMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
885 |
885 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
TlAReadyKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26950561 |
26791084 |
0 |
0 |
T1 |
10441 |
10364 |
0 |
0 |
T2 |
1465 |
1377 |
0 |
0 |
T3 |
43645 |
43483 |
0 |
0 |
T4 |
168386 |
168331 |
0 |
0 |
T5 |
2095 |
2008 |
0 |
0 |
T6 |
42998 |
42282 |
0 |
0 |
T15 |
9512 |
9378 |
0 |
0 |
T16 |
33731 |
33665 |
0 |
0 |
T17 |
21736 |
21646 |
0 |
0 |
T18 |
7196 |
7136 |
0 |
0 |
TlDValidKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26950561 |
26791084 |
0 |
0 |
T1 |
10441 |
10364 |
0 |
0 |
T2 |
1465 |
1377 |
0 |
0 |
T3 |
43645 |
43483 |
0 |
0 |
T4 |
168386 |
168331 |
0 |
0 |
T5 |
2095 |
2008 |
0 |
0 |
T6 |
42998 |
42282 |
0 |
0 |
T15 |
9512 |
9378 |
0 |
0 |
T16 |
33731 |
33665 |
0 |
0 |
T17 |
21736 |
21646 |
0 |
0 |
T18 |
7196 |
7136 |
0 |
0 |