Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	95.95	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	28658239	17199	0	0
attest_sw_binding_0_rd_A	28658239	2982	0	0
attest_sw_binding_1_rd_A	28658239	3021	0	0
attest_sw_binding_2_rd_A	28658239	3055	0	0
attest_sw_binding_3_rd_A	28658239	2932	0	0
attest_sw_binding_4_rd_A	28658239	3042	0	0
attest_sw_binding_5_rd_A	28658239	3054	0	0
attest_sw_binding_6_rd_A	28658239	2877	0	0
attest_sw_binding_7_rd_A	28658239	2957	0	0
intr_enable_rd_A	28658239	3498	0	0
key_version_rd_A	28658239	2901	0	0
max_creator_key_ver_regwen_rd_A	28658239	3047	0	0
max_owner_int_key_ver_regwen_rd_A	28658239	2940	0	0
max_owner_key_ver_regwen_rd_A	28658239	2936	0	0
reseed_interval_regwen_rd_A	28658239	2939	0	0
salt_0_rd_A	28658239	2969	0	0
salt_1_rd_A	28658239	2893	0	0
salt_2_rd_A	28658239	2874	0	0
salt_3_rd_A	28658239	2958	0	0
salt_4_rd_A	28658239	3020	0	0
salt_5_rd_A	28658239	3043	0	0
salt_6_rd_A	28658239	3018	0	0
salt_7_rd_A	28658239	2858	0	0
sealing_sw_binding_0_rd_A	28658239	3014	0	0
sealing_sw_binding_1_rd_A	28658239	3032	0	0
sealing_sw_binding_2_rd_A	28658239	2801	0	0
sealing_sw_binding_3_rd_A	28658239	2897	0	0
sealing_sw_binding_4_rd_A	28658239	3077	0	0
sealing_sw_binding_5_rd_A	28658239	3084	0	0
sealing_sw_binding_6_rd_A	28658239	3167	0	0
sealing_sw_binding_7_rd_A	28658239	3024	0	0
sideload_clear_rd_A	28658239	2837	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	17199	0	0
T3	43645	65	0	0
T4	168386	0	0	0
T5	2095	0	0	0
T6	42998	0	0	0
T9	0	415	0	0
T15	9512	0	0	0
T16	33731	0	0	0
T17	21736	25	0	0
T18	7196	0	0	0
T37	79466	0	0	0
T40	2423	0	0	0
T60	0	797	0	0
T119	0	282	0	0
T120	0	870	0	0
T121	0	368	0	0
T122	0	38	0	0
T123	0	224	0	0
T124	0	85	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	2982	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	173	0	0
T115	0	32	0	0
T121	59518	86	0	0
T138	0	2	0	0
T162	0	27	0	0
T177	0	242	0	0
T178	0	27	0	0
T179	0	14	0	0
T180	0	22	0	0
T181	0	31	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	3021	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	195	0	0
T115	0	38	0	0
T121	59518	50	0	0
T138	0	15	0	0
T162	0	49	0	0
T177	0	232	0	0
T178	0	32	0	0
T179	0	28	0	0
T180	0	31	0	0
T181	0	43	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	3055	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	189	0	0
T115	0	50	0	0
T121	59518	54	0	0
T138	0	37	0	0
T162	0	27	0	0
T177	0	252	0	0
T178	0	31	0	0
T179	0	21	0	0
T180	0	36	0	0
T181	0	21	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	2932	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	168	0	0
T115	0	61	0	0
T121	59518	64	0	0
T138	0	29	0	0
T162	0	26	0	0
T177	0	227	0	0
T178	0	10	0	0
T179	0	22	0	0
T180	0	29	0	0
T181	0	29	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	3042	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	170	0	0
T115	0	68	0	0
T121	59518	77	0	0
T138	0	32	0	0
T162	0	37	0	0
T177	0	261	0	0
T178	0	36	0	0
T179	0	17	0	0
T180	0	16	0	0
T181	0	32	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	3054	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	200	0	0
T115	0	47	0	0
T121	59518	66	0	0
T138	0	48	0	0
T162	0	32	0	0
T177	0	265	0	0
T178	0	29	0	0
T179	0	9	0	0
T180	0	18	0	0
T181	0	17	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	2877	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	186	0	0
T115	0	38	0	0
T121	59518	69	0	0
T138	0	14	0	0
T162	0	23	0	0
T177	0	255	0	0
T178	0	20	0	0
T179	0	4	0	0
T180	0	14	0	0
T181	0	33	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	2957	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	206	0	0
T115	0	47	0	0
T121	59518	55	0	0
T138	0	18	0	0
T162	0	35	0	0
T177	0	228	0	0
T178	0	22	0	0
T179	0	12	0	0
T180	0	32	0	0
T181	0	35	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	3498	0	0
T50	0	18	0	0
T69	7181	0	0	0
T76	70582	3	0	0
T119	16340	0	0	0
T121	0	116	0	0
T178	0	25	0	0
T179	0	25	0	0
T180	0	35	0	0
T189	0	14	0	0
T190	0	21	0	0
T191	0	16	0	0
T192	0	18	0	0
T193	3422	0	0	0
T194	9964	0	0	0
T195	18690	0	0	0
T196	4131	0	0	0
T197	93614	0	0	0
T198	1854	0	0	0
T199	2320	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	2901	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	199	0	0
T115	0	43	0	0
T121	59518	63	0	0
T138	0	11	0	0
T162	0	36	0	0
T177	0	215	0	0
T178	0	14	0	0
T179	0	40	0	0
T180	0	31	0	0
T181	0	24	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	3047	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	141	0	0
T115	0	36	0	0
T121	59518	56	0	0
T138	0	40	0	0
T162	0	34	0	0
T177	0	249	0	0
T178	0	4	0	0
T179	0	30	0	0
T180	0	11	0	0
T181	0	35	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	2940	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	148	0	0
T115	0	33	0	0
T121	59518	71	0	0
T138	0	34	0	0
T162	0	38	0	0
T177	0	246	0	0
T178	0	37	0	0
T179	0	12	0	0
T180	0	23	0	0
T181	0	46	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	2936	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	191	0	0
T115	0	39	0	0
T121	59518	62	0	0
T138	0	17	0	0
T177	0	206	0	0
T178	0	19	0	0
T179	0	11	0	0
T180	0	22	0	0
T181	0	28	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0
T200	0	8	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	2939	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	180	0	0
T115	0	45	0	0
T121	59518	50	0	0
T138	0	28	0	0
T162	0	42	0	0
T177	0	209	0	0
T178	0	36	0	0
T179	0	5	0	0
T180	0	28	0	0
T181	0	22	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	2969	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	161	0	0
T115	0	49	0	0
T121	59518	54	0	0
T138	0	40	0	0
T162	0	38	0	0
T177	0	264	0	0
T178	0	24	0	0
T179	0	14	0	0
T180	0	25	0	0
T181	0	33	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	2893	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	187	0	0
T115	0	35	0	0
T121	59518	58	0	0
T138	0	14	0	0
T162	0	39	0	0
T177	0	220	0	0
T178	0	26	0	0
T179	0	19	0	0
T180	0	15	0	0
T181	0	26	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	2874	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	185	0	0
T115	0	48	0	0
T121	59518	40	0	0
T138	0	8	0	0
T162	0	58	0	0
T177	0	239	0	0
T178	0	33	0	0
T179	0	11	0	0
T180	0	24	0	0
T181	0	16	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	2958	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	189	0	0
T115	0	36	0	0
T121	59518	78	0	0
T138	0	42	0	0
T162	0	54	0	0
T177	0	255	0	0
T178	0	5	0	0
T179	0	7	0	0
T180	0	12	0	0
T181	0	24	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	3020	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	164	0	0
T115	0	53	0	0
T121	59518	37	0	0
T138	0	43	0	0
T162	0	30	0	0
T177	0	244	0	0
T178	0	18	0	0
T179	0	30	0	0
T180	0	21	0	0
T181	0	37	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	3043	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	169	0	0
T115	0	37	0	0
T121	59518	61	0	0
T138	0	16	0	0
T162	0	48	0	0
T177	0	219	0	0
T178	0	27	0	0
T179	0	25	0	0
T180	0	21	0	0
T181	0	28	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	3018	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	185	0	0
T115	0	55	0	0
T121	59518	57	0	0
T138	0	33	0	0
T162	0	51	0	0
T177	0	247	0	0
T178	0	35	0	0
T179	0	7	0	0
T180	0	19	0	0
T181	0	25	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	2858	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	168	0	0
T115	0	49	0	0
T121	59518	42	0	0
T138	0	60	0	0
T162	0	42	0	0
T177	0	211	0	0
T178	0	30	0	0
T179	0	13	0	0
T180	0	18	0	0
T181	0	44	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	3014	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	190	0	0
T115	0	37	0	0
T121	59518	51	0	0
T138	0	20	0	0
T162	0	32	0	0
T177	0	216	0	0
T178	0	22	0	0
T179	0	13	0	0
T180	0	24	0	0
T181	0	38	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	3032	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	188	0	0
T115	0	40	0	0
T121	59518	60	0	0
T138	0	39	0	0
T162	0	63	0	0
T177	0	253	0	0
T178	0	20	0	0
T179	0	2	0	0
T180	0	30	0	0
T181	0	19	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	2801	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	169	0	0
T115	0	54	0	0
T121	59518	47	0	0
T138	0	12	0	0
T162	0	34	0	0
T177	0	218	0	0
T178	0	19	0	0
T179	0	20	0	0
T180	0	15	0	0
T181	0	24	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	2897	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	154	0	0
T115	0	48	0	0
T121	59518	59	0	0
T138	0	17	0	0
T162	0	37	0	0
T177	0	209	0	0
T178	0	16	0	0
T179	0	5	0	0
T180	0	17	0	0
T181	0	15	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	3077	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	191	0	0
T115	0	68	0	0
T121	59518	52	0	0
T138	0	25	0	0
T162	0	55	0	0
T177	0	243	0	0
T178	0	28	0	0
T179	0	17	0	0
T180	0	16	0	0
T181	0	39	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	3084	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	219	0	0
T115	0	54	0	0
T121	59518	42	0	0
T138	0	46	0	0
T162	0	37	0	0
T177	0	214	0	0
T178	0	10	0	0
T179	0	8	0	0
T180	0	41	0	0
T181	0	23	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	3167	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	194	0	0
T115	0	59	0	0
T121	59518	43	0	0
T138	0	76	0	0
T162	0	57	0	0
T177	0	288	0	0
T178	0	24	0	0
T179	0	10	0	0
T180	0	39	0	0
T181	0	9	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	3024	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	182	0	0
T115	0	62	0	0
T121	59518	62	0	0
T138	0	32	0	0
T162	0	47	0	0
T177	0	262	0	0
T178	0	23	0	0
T179	0	15	0	0
T180	0	31	0	0
T181	0	22	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28658239	2837	0	0
T66	90329	0	0	0
T89	6728	0	0	0
T112	0	160	0	0
T115	0	21	0	0
T121	59518	52	0	0
T138	0	1	0	0
T162	0	41	0	0
T177	0	232	0	0
T178	0	30	0	0
T179	0	17	0	0
T180	0	23	0	0
T181	0	25	0	0
T182	16180	0	0	0
T183	19509	0	0	0
T184	22650	0	0	0
T185	10062	0	0	0
T186	5995	0	0	0
T187	4634	0	0	0
T188	7720	0	0	0