Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25185921	15699	0	0
attest_sw_binding_0_rd_A	25185921	3239	0	0
attest_sw_binding_1_rd_A	25185921	3295	0	0
attest_sw_binding_2_rd_A	25185921	3305	0	0
attest_sw_binding_3_rd_A	25185921	3223	0	0
attest_sw_binding_4_rd_A	25185921	3563	0	0
attest_sw_binding_5_rd_A	25185921	3380	0	0
attest_sw_binding_6_rd_A	25185921	3525	0	0
attest_sw_binding_7_rd_A	25185921	3440	0	0
intr_enable_rd_A	25185921	4053	0	0
key_version_rd_A	25185921	3406	0	0
max_creator_key_ver_regwen_rd_A	25185921	3269	0	0
max_owner_int_key_ver_regwen_rd_A	25185921	3201	0	0
max_owner_key_ver_regwen_rd_A	25185921	3377	0	0
reseed_interval_regwen_rd_A	25185921	3342	0	0
salt_0_rd_A	25185921	3448	0	0
salt_1_rd_A	25185921	3360	0	0
salt_2_rd_A	25185921	3211	0	0
salt_3_rd_A	25185921	3204	0	0
salt_4_rd_A	25185921	3089	0	0
salt_5_rd_A	25185921	3292	0	0
salt_6_rd_A	25185921	3429	0	0
salt_7_rd_A	25185921	3477	0	0
sealing_sw_binding_0_rd_A	25185921	3206	0	0
sealing_sw_binding_1_rd_A	25185921	3385	0	0
sealing_sw_binding_2_rd_A	25185921	3284	0	0
sealing_sw_binding_3_rd_A	25185921	3432	0	0
sealing_sw_binding_4_rd_A	25185921	3209	0	0
sealing_sw_binding_5_rd_A	25185921	3341	0	0
sealing_sw_binding_6_rd_A	25185921	3317	0	0
sealing_sw_binding_7_rd_A	25185921	3441	0	0
sideload_clear_rd_A	25185921	3353	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	15699	0	0
T1	32865	158	0	0
T2	9650	0	0	0
T3	30802	419	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T58	0	204	0	0
T63	0	124	0	0
T69	0	440	0	0
T114	0	300	0	0
T115	0	337	0	0
T116	0	580	0	0
T117	0	697	0	0
T118	0	217	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3239	0	0
T1	32865	30	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	51	0	0
T167	0	66	0	0
T168	0	13	0	0
T169	0	35	0	0
T170	0	49	0	0
T171	0	21	0	0
T172	0	56	0	0
T173	0	26	0	0
T174	0	8	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3295	0	0
T1	32865	27	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	36	0	0
T127	0	35	0	0
T167	0	26	0	0
T168	0	15	0	0
T169	0	80	0	0
T170	0	47	0	0
T171	0	34	0	0
T172	0	46	0	0
T173	0	21	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3305	0	0
T1	32865	42	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	36	0	0
T167	0	57	0	0
T168	0	47	0	0
T169	0	66	0	0
T170	0	36	0	0
T171	0	18	0	0
T172	0	73	0	0
T173	0	20	0	0
T174	0	8	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3223	0	0
T1	32865	36	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	40	0	0
T127	0	1	0	0
T167	0	51	0	0
T168	0	24	0	0
T169	0	54	0	0
T170	0	29	0	0
T171	0	38	0	0
T172	0	49	0	0
T173	0	22	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3563	0	0
T1	32865	10	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	53	0	0
T167	0	67	0	0
T168	0	35	0	0
T169	0	74	0	0
T170	0	22	0	0
T171	0	15	0	0
T172	0	51	0	0
T173	0	22	0	0
T174	0	23	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3380	0	0
T1	32865	24	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	52	0	0
T167	0	66	0	0
T168	0	27	0	0
T169	0	84	0	0
T170	0	27	0	0
T171	0	33	0	0
T172	0	48	0	0
T173	0	29	0	0
T174	0	3	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3525	0	0
T1	32865	26	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	59	0	0
T167	0	72	0	0
T168	0	25	0	0
T169	0	48	0	0
T170	0	17	0	0
T171	0	21	0	0
T172	0	55	0	0
T173	0	37	0	0
T174	0	4	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3440	0	0
T1	32865	33	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	77	0	0
T167	0	63	0	0
T168	0	15	0	0
T169	0	75	0	0
T170	0	7	0	0
T171	0	30	0	0
T172	0	59	0	0
T173	0	18	0	0
T174	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	4053	0	0
T1	32865	21	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T45	0	37	0	0
T53	0	33	0	0
T54	0	26	0	0
T61	0	66	0	0
T66	0	64	0	0
T71	0	44	0	0
T167	0	72	0	0
T168	0	62	0	0
T175	0	14	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3406	0	0
T1	32865	34	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	26	0	0
T167	0	74	0	0
T168	0	21	0	0
T169	0	49	0	0
T170	0	25	0	0
T171	0	21	0	0
T172	0	44	0	0
T173	0	35	0	0
T174	0	2	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3269	0	0
T1	32865	28	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	50	0	0
T167	0	63	0	0
T168	0	31	0	0
T169	0	44	0	0
T170	0	18	0	0
T171	0	29	0	0
T172	0	63	0	0
T173	0	28	0	0
T174	0	24	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3201	0	0
T1	32865	35	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	24	0	0
T167	0	70	0	0
T168	0	21	0	0
T169	0	64	0	0
T170	0	49	0	0
T171	0	34	0	0
T172	0	52	0	0
T173	0	33	0	0
T174	0	1	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3377	0	0
T1	32865	29	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	41	0	0
T167	0	71	0	0
T168	0	37	0	0
T169	0	62	0	0
T170	0	34	0	0
T171	0	30	0	0
T172	0	64	0	0
T173	0	20	0	0
T174	0	2	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3342	0	0
T1	32865	27	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	57	0	0
T167	0	45	0	0
T168	0	11	0	0
T169	0	60	0	0
T170	0	28	0	0
T171	0	15	0	0
T172	0	51	0	0
T173	0	34	0	0
T174	0	4	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3448	0	0
T1	32865	27	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	61	0	0
T167	0	39	0	0
T168	0	30	0	0
T169	0	67	0	0
T170	0	15	0	0
T171	0	21	0	0
T172	0	53	0	0
T173	0	6	0	0
T174	0	17	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3360	0	0
T1	32865	26	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	57	0	0
T167	0	80	0	0
T168	0	26	0	0
T169	0	71	0	0
T170	0	41	0	0
T171	0	15	0	0
T172	0	63	0	0
T173	0	21	0	0
T174	0	7	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3211	0	0
T1	32865	34	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T167	0	83	0	0
T168	0	18	0	0
T169	0	66	0	0
T170	0	21	0	0
T171	0	46	0	0
T172	0	44	0	0
T173	0	33	0	0
T174	0	7	0	0
T176	0	9	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3204	0	0
T1	32865	27	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	45	0	0
T167	0	46	0	0
T168	0	37	0	0
T169	0	77	0	0
T170	0	28	0	0
T171	0	25	0	0
T172	0	38	0	0
T173	0	29	0	0
T174	0	2	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3089	0	0
T1	32865	29	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	59	0	0
T127	0	14	0	0
T167	0	68	0	0
T168	0	31	0	0
T169	0	77	0	0
T170	0	28	0	0
T171	0	21	0	0
T172	0	47	0	0
T173	0	50	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3292	0	0
T1	32865	35	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	55	0	0
T167	0	68	0	0
T168	0	31	0	0
T169	0	61	0	0
T170	0	11	0	0
T171	0	27	0	0
T172	0	52	0	0
T173	0	15	0	0
T174	0	1	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3429	0	0
T1	32865	18	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	46	0	0
T127	0	29	0	0
T167	0	32	0	0
T168	0	30	0	0
T169	0	55	0	0
T170	0	16	0	0
T171	0	40	0	0
T172	0	59	0	0
T173	0	24	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3477	0	0
T1	32865	12	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	37	0	0
T167	0	62	0	0
T168	0	38	0	0
T169	0	62	0	0
T170	0	37	0	0
T171	0	36	0	0
T172	0	53	0	0
T173	0	37	0	0
T174	0	9	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3206	0	0
T1	32865	28	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	43	0	0
T167	0	84	0	0
T168	0	17	0	0
T169	0	72	0	0
T170	0	18	0	0
T171	0	30	0	0
T172	0	31	0	0
T173	0	38	0	0
T174	0	1	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3385	0	0
T1	32865	30	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	51	0	0
T167	0	37	0	0
T168	0	54	0	0
T169	0	59	0	0
T170	0	15	0	0
T171	0	25	0	0
T172	0	33	0	0
T173	0	39	0	0
T174	0	9	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3284	0	0
T1	32865	15	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	27	0	0
T127	0	29	0	0
T167	0	82	0	0
T168	0	16	0	0
T169	0	77	0	0
T170	0	31	0	0
T171	0	18	0	0
T172	0	51	0	0
T173	0	38	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3432	0	0
T1	32865	31	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	40	0	0
T167	0	56	0	0
T168	0	8	0	0
T169	0	64	0	0
T170	0	22	0	0
T171	0	32	0	0
T172	0	54	0	0
T173	0	36	0	0
T174	0	1	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3209	0	0
T1	32865	27	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	39	0	0
T167	0	41	0	0
T168	0	30	0	0
T169	0	22	0	0
T170	0	31	0	0
T171	0	30	0	0
T172	0	59	0	0
T173	0	28	0	0
T174	0	13	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3341	0	0
T1	32865	23	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	52	0	0
T167	0	67	0	0
T168	0	30	0	0
T169	0	95	0	0
T170	0	21	0	0
T171	0	19	0	0
T172	0	50	0	0
T173	0	44	0	0
T174	0	6	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3317	0	0
T1	32865	28	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	45	0	0
T167	0	82	0	0
T168	0	21	0	0
T169	0	68	0	0
T170	0	33	0	0
T171	0	21	0	0
T172	0	60	0	0
T173	0	17	0	0
T174	0	10	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3441	0	0
T1	32865	24	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	42	0	0
T167	0	61	0	0
T168	0	30	0	0
T169	0	67	0	0
T170	0	26	0	0
T171	0	18	0	0
T172	0	59	0	0
T173	0	26	0	0
T174	0	10	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25185921	3353	0	0
T1	32865	30	0	0
T2	9650	0	0	0
T3	30802	0	0	0
T12	10986	0	0	0
T13	15936	0	0	0
T14	3419	0	0	0
T15	153486	0	0	0
T16	17653	0	0	0
T17	3938	0	0	0
T18	10352	0	0	0
T106	0	54	0	0
T167	0	68	0	0
T168	0	54	0	0
T169	0	37	0	0
T170	0	32	0	0
T171	0	27	0	0
T172	0	48	0	0
T173	0	38	0	0
T174	0	19	0	0