Line Coverage for Module :
keymgr
| Line No. | Total | Covered | Percent |
TOTAL | | 75 | 72 | 96.00 |
CONT_ASSIGN | 210 | 1 | 1 | 100.00 |
CONT_ASSIGN | 234 | 1 | 1 | 100.00 |
CONT_ASSIGN | 235 | 1 | 1 | 100.00 |
CONT_ASSIGN | 237 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 271 | 1 | 1 | 100.00 |
CONT_ASSIGN | 271 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 326 | 1 | 1 | 100.00 |
CONT_ASSIGN | 328 | 1 | 1 | 100.00 |
CONT_ASSIGN | 346 | 1 | 1 | 100.00 |
CONT_ASSIGN | 353 | 1 | 1 | 100.00 |
CONT_ASSIGN | 369 | 1 | 1 | 100.00 |
CONT_ASSIGN | 399 | 1 | 1 | 100.00 |
CONT_ASSIGN | 404 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 436 | 1 | 1 | 100.00 |
CONT_ASSIGN | 442 | 1 | 1 | 100.00 |
CONT_ASSIGN | 455 | 1 | 1 | 100.00 |
CONT_ASSIGN | 457 | 1 | 1 | 100.00 |
CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
CONT_ASSIGN | 460 | 1 | 1 | 100.00 |
CONT_ASSIGN | 463 | 1 | 1 | 100.00 |
CONT_ASSIGN | 468 | 1 | 1 | 100.00 |
CONT_ASSIGN | 471 | 1 | 0 | 0.00 |
CONT_ASSIGN | 472 | 1 | 0 | 0.00 |
CONT_ASSIGN | 473 | 1 | 0 | 0.00 |
CONT_ASSIGN | 481 | 1 | 1 | 100.00 |
CONT_ASSIGN | 482 | 1 | 1 | 100.00 |
CONT_ASSIGN | 485 | 1 | 1 | 100.00 |
CONT_ASSIGN | 487 | 1 | 1 | 100.00 |
CONT_ASSIGN | 497 | 1 | 1 | 100.00 |
CONT_ASSIGN | 498 | 1 | 1 | 100.00 |
CONT_ASSIGN | 499 | 1 | 1 | 100.00 |
CONT_ASSIGN | 536 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
CONT_ASSIGN | 538 | 1 | 1 | 100.00 |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
CONT_ASSIGN | 540 | 1 | 1 | 100.00 |
CONT_ASSIGN | 541 | 1 | 1 | 100.00 |
CONT_ASSIGN | 542 | 1 | 1 | 100.00 |
CONT_ASSIGN | 543 | 1 | 1 | 100.00 |
CONT_ASSIGN | 550 | 1 | 1 | 100.00 |
CONT_ASSIGN | 551 | 1 | 1 | 100.00 |
CONT_ASSIGN | 552 | 1 | 1 | 100.00 |
CONT_ASSIGN | 553 | 1 | 1 | 100.00 |
CONT_ASSIGN | 670 | 1 | 1 | 100.00 |
CONT_ASSIGN | 671 | 1 | 1 | 100.00 |
CONT_ASSIGN | 672 | 1 | 1 | 100.00 |
CONT_ASSIGN | 674 | 1 | 1 | 100.00 |
CONT_ASSIGN | 675 | 1 | 1 | 100.00 |
CONT_ASSIGN | 676 | 1 | 1 | 100.00 |
CONT_ASSIGN | 677 | 1 | 1 | 100.00 |
CONT_ASSIGN | 678 | 1 | 1 | 100.00 |
CONT_ASSIGN | 679 | 1 | 1 | 100.00 |
CONT_ASSIGN | 680 | 1 | 1 | 100.00 |
CONT_ASSIGN | 681 | 1 | 1 | 100.00 |
CONT_ASSIGN | 682 | 1 | 1 | 100.00 |
CONT_ASSIGN | 683 | 1 | 1 | 100.00 |
CONT_ASSIGN | 684 | 1 | 1 | 100.00 |
CONT_ASSIGN | 685 | 1 | 1 | 100.00 |
CONT_ASSIGN | 686 | 1 | 1 | 100.00 |
CONT_ASSIGN | 687 | 1 | 1 | 100.00 |
CONT_ASSIGN | 711 | 1 | 1 | 100.00 |
CONT_ASSIGN | 713 | 1 | 1 | 100.00 |
CONT_ASSIGN | 716 | 1 | 1 | 100.00 |
CONT_ASSIGN | 717 | 1 | 1 | 100.00 |
ALWAYS | 721 | 5 | 5 | 100.00 |
CONT_ASSIGN | 731 | 1 | 1 | 100.00 |
CONT_ASSIGN | 748 | 1 | 1 | 100.00 |
CONT_ASSIGN | 779 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
210 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
237 |
1 |
1 |
238 |
1 |
1 |
271 |
2 |
2 |
275 |
1 |
1 |
326 |
1 |
1 |
328 |
1 |
1 |
346 |
1 |
1 |
353 |
1 |
1 |
369 |
1 |
1 |
399 |
1 |
1 |
404 |
1 |
1 |
417 |
1 |
1 |
419 |
1 |
1 |
436 |
1 |
1 |
442 |
1 |
1 |
455 |
1 |
1 |
457 |
1 |
1 |
459 |
1 |
1 |
460 |
1 |
1 |
463 |
1 |
1 |
468 |
1 |
1 |
471 |
0 |
1 |
472 |
0 |
1 |
473 |
0 |
1 |
481 |
1 |
1 |
482 |
1 |
1 |
485 |
1 |
1 |
487 |
1 |
1 |
497 |
1 |
1 |
498 |
1 |
1 |
499 |
1 |
1 |
536 |
1 |
1 |
537 |
1 |
1 |
538 |
1 |
1 |
539 |
1 |
1 |
540 |
1 |
1 |
541 |
1 |
1 |
542 |
1 |
1 |
543 |
1 |
1 |
550 |
1 |
1 |
551 |
1 |
1 |
552 |
1 |
1 |
553 |
1 |
1 |
670 |
1 |
1 |
671 |
1 |
1 |
672 |
1 |
1 |
674 |
1 |
1 |
675 |
1 |
1 |
676 |
1 |
1 |
677 |
1 |
1 |
678 |
1 |
1 |
679 |
1 |
1 |
680 |
1 |
1 |
681 |
1 |
1 |
682 |
1 |
1 |
683 |
1 |
1 |
684 |
1 |
1 |
685 |
1 |
1 |
686 |
1 |
1 |
687 |
1 |
1 |
711 |
1 |
1 |
713 |
1 |
1 |
716 |
1 |
1 |
717 |
1 |
1 |
721 |
1 |
1 |
722 |
1 |
1 |
723 |
1 |
1 |
725 |
1 |
1 |
726 |
1 |
1 |
731 |
1 |
1 |
748 |
1 |
1 |
779 |
|
unreachable |
Cond Coverage for Module :
keymgr
| Total | Covered | Percent |
Conditions | 183 | 180 | 98.36 |
Logical | 183 | 180 | 98.36 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 210
EXPRESSION (ctrl_lfsr_en | data_lfsr_en | sideload_lfsr_en)
------1----- ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T1,T2,T3 |
1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 336
EXPRESSION (op_start & op_done)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T9,T10,T11 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 353
EXPRESSION (reg2hw.sw_binding_regwen.qe & ((~reg2hw.sw_binding_regwen.q)))
-------------1------------- ---------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T12,T14 |
1 | 1 | Covered | T1,T3,T12 |
LINE 369
EXPRESSION (sw_binding_regwen & cfg_regwen)
--------1-------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T12,T14 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 399
EXPRESSION ((cdi_sel == 1'b0) ? reg2hw.sealing_sw_binding : ((cdi_sel == 1'b1) ? reg2hw.attest_sw_binding : RndCnstCdi))
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 399
SUB-EXPRESSION (cdi_sel == 1'b0)
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 399
SUB-EXPRESSION ((cdi_sel == 1'b1) ? reg2hw.attest_sw_binding : RndCnstCdi)
--------1--------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 399
SUB-EXPRESSION (cdi_sel == 1'b1)
--------1--------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 442
EXPRESSION (creator_seed_vld & devid_vld & health_state_vld & rom_digest_vld)
--------1------- ----2---- --------3------- -------4------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T23,T83,T84 |
1 | 0 | 1 | 1 | Covered | T34,T23,T85 |
1 | 1 | 0 | 1 | Covered | T34,T23,T60 |
1 | 1 | 1 | 0 | Covered | T12,T34,T85 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 482
EXPRESSION ((dest_sel == Aes) ? aes_seed : ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed)))
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 482
SUB-EXPRESSION (dest_sel == Aes)
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 482
SUB-EXPRESSION ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed))
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 482
SUB-EXPRESSION (dest_sel == Kmac)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 482
SUB-EXPRESSION ((dest_sel == Otbn) ? otbn_seed : none_seed)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 482
SUB-EXPRESSION (dest_sel == Otbn)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 487
EXPRESSION (invalid_stage_sel ? ({GenLfsrCopies {lfsr[31:0]}}) : ({reg2hw.key_version, reg2hw.salt, dest_seed, output_key}))
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 536
EXPRESSION (adv_en | id_en | gen_en)
---1-- --2-- ---3--
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T1,T2,T3 |
1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 537
EXPRESSION (adv_en & (stage_sel == Creator) & ((~creator_seed_vld)))
---1-- -----------2---------- ----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T23,T83,T86 |
1 | 0 | 1 | Covered | T83,T87,T88 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T23,T86,T89 |
LINE 537
SUB-EXPRESSION (stage_sel == Creator)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 538
EXPRESSION (adv_en & (stage_sel == OwnerInt) & ((~owner_seed_vld)))
---1-- -----------2----------- ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T21,T90,T91 |
1 | 0 | 1 | Covered | T23,T90,T92 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T21 |
LINE 538
SUB-EXPRESSION (stage_sel == OwnerInt)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 539
EXPRESSION (adv_en & (stage_sel == Creator) & ((~devid_vld)))
---1-- -----------2---------- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T12,T23,T83 |
1 | 0 | 1 | Covered | T83,T21,T90 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T12,T23,T86 |
LINE 539
SUB-EXPRESSION (stage_sel == Creator)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 540
EXPRESSION (adv_en & (stage_sel == Creator) & ((~health_state_vld)))
---1-- -----------2---------- ----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T12,T23,T24 |
1 | 0 | 1 | Covered | T21,T60,T93 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T12,T23,T24 |
LINE 540
SUB-EXPRESSION (stage_sel == Creator)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 541
EXPRESSION (gen_en & ((~key_version_vld)))
---1-- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T12 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T12,T26 |
LINE 542
EXPRESSION (valid_op & ((~key_vld)))
----1--- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T20,T22,T25 |
LINE 543
EXPRESSION (adv_en & (stage_sel == Creator) & ((~rom_digest_vld)))
---1-- -----------2---------- ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T12,T23,T24 |
1 | 0 | 1 | Covered | T21,T94,T93 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T12,T23,T24 |
LINE 543
SUB-EXPRESSION (stage_sel == Creator)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 550
EXPRESSION (((~key_vld)) | ((~adv_dvalid[stage_sel])))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T12,T23,T83 |
1 | 0 | Covered | T1,T2,T3 |
LINE 552
EXPRESSION (((~key_vld)) | ((~key_version_vld)))
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T12,T14 |
1 | 0 | Covered | T1,T2,T3 |
LINE 553
EXPRESSION (((~key_vld)) | ((~key_version_vld)))
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T12,T14 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(0 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T53,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(1 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T53,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(2 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T53,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(3 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T53,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(4 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T53,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(5 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T53,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(6 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T53,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(7 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T53,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(0 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T53,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(1 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T53,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(2 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T53,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(3 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T53,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(4 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T53,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(5 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T53,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(6 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T53,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(7 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T53,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 713
EXPRESSION (fault_errs ? 1'b1 : (fault_err_ack ? 1'b0 : fault_err_req_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T13,T14,T19 |
LINE 713
SUB-EXPRESSION (fault_err_ack ? 1'b0 : fault_err_req_q)
------1------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 717
EXPRESSION (op_errs ? 1'b1 : (op_err_ack ? 1'b0 : op_err_req_q))
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 717
SUB-EXPRESSION (op_err_ack ? 1'b0 : op_err_req_q)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 731
EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
-----------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T95,T96,T97 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T95,T96,T97 |
LINE 748
EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
-------------------1------------------- --------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T95,T96,T97 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T95,T96,T97 |
Toggle Coverage for Module :
keymgr
| Total | Covered | Percent |
Totals |
67 |
65 |
97.01 |
Total Bits |
10068 |
10064 |
99.96 |
Total Bits 0->1 |
5034 |
5032 |
99.96 |
Total Bits 1->0 |
5034 |
5032 |
99.96 |
| | | |
Ports |
67 |
65 |
97.01 |
Port Bits |
10068 |
10064 |
99.96 |
Port Bits 0->1 |
5034 |
5032 |
99.96 |
Port Bits 1->0 |
5034 |
5032 |
99.96 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T1,T3,T13 |
Yes |
T1,T2,T3 |
INPUT |
rst_shadowed_ni |
Yes |
Yes |
T1,T3,T13 |
Yes |
T1,T2,T3 |
INPUT |
clk_edn_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_edn_ni |
Yes |
Yes |
T1,T3,T13 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T3,T18 |
Yes |
T1,T3,T18 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_source[7:0] |
Yes |
Yes |
T1,T3,T14 |
Yes |
T1,T3,T14 |
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T1,T3,T13 |
Yes |
T1,T3,T13 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
T1,*T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_source[7:0] |
Yes |
Yes |
T1,T3,T14 |
Yes |
T1,T3,T14 |
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][13:1] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][14] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][63:15] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][64] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][66:65] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][67] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][95:68] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][96] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][98:97] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][99] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][109:100] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][110] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][127:111] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][128] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][208:129] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][209] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][223:210] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][224] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][226:225] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][227] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][237:228] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][238] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][255:239] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][4] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][9:5] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][10] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][21:11] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][22] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][26:23] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][27] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][28] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][29] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][35:30] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][36] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][47:37] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][48] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][58:49] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][59] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][60] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][61] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][71:62] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][72] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][78:73] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][79] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][90:80] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][91] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][97:92] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][98] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][99] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][100] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][135:101] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][136] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][143:137] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][144] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][149:145] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][150] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][167:151] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][168] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][170:169] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][171] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][174:172] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][175] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][181:176] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][182] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][193:183] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][194] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][201:195] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][202] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][218:203] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][219] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][227:220] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][228] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][245:229] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][246] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][255:247] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.valid |
Yes |
Yes |
T3,T13,T4 |
Yes |
T3,T13,T17 |
OUTPUT |
kmac_key_o.key[1:0][255:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
kmac_key_o.valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][2] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][3] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][10:4] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][11] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][13:12] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][14] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][16:15] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][17] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][31:18] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][33:32] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][34] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][35] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][42:36] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][43] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][45:44] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][46] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][48:47] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][49] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][63:50] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][65:64] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][66] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][67] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][74:68] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][75] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][77:76] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][78] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][80:79] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][81] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][95:82] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][96] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][97] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][98] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][99] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][106:100] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][107] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][109:108] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][110] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][112:111] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][113] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][127:114] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][129:128] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][130] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][131] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][138:132] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][139] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][141:140] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][142] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][144:143] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][145] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][159:146] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][161:160] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][162] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][163] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][170:164] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][171] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][173:172] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][174] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][176:175] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][177] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][191:178] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][192] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][193] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][194] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][195] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][202:196] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][203] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][205:204] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][206] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][208:207] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][209] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][223:210] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][225:224] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][226] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][227] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][234:228] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][235] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][237:236] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][238] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][240:239] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][241] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][255:242] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][257:256] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][258] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][259] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][266:260] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][267] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][269:268] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][270] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][272:271] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][273] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][287:274] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][289:288] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][290] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][291] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][298:292] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][299] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][301:300] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][302] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][304:303] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][305] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][319:306] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][321:320] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][322] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][323] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][330:324] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][331] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][333:332] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][334] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][336:335] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][337] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][351:338] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][352] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][353] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][354] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][355] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][362:356] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][363] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][365:364] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][366] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][368:367] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][369] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[0][383:370] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][2] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][3] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][4] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][7:5] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][8] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][9] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][10] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][11] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][14:12] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][16:15] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][20:17] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][21] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][22] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][26:23] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][27] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][28] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][29] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][33:30] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][34] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][35] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][36] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][39:37] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][40] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][41] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][42] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][43] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][46:44] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][47] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][48] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][52:49] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][54:53] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][58:55] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][59] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][60] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][61] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][65:62] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][66] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][67] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][68] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][71:69] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][72] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][73] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][75:74] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][78:76] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][79] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][80] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][84:81] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][86:85] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][90:87] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][91] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][92] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][93] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][97:94] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][98] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][99] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][100] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][103:101] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][104] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][105] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][107:106] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][110:108] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][111] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][112] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][116:113] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][118:117] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][122:119] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][123] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][124] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][125] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][129:126] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][130] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][131] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][132] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][135:133] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][136] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][137] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][139:138] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][142:140] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][143] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][144] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][148:145] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][149] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][150] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][154:151] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][155] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][156] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][157] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][161:158] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][162] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][163] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][164] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][167:165] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][168] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][169] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][171:170] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][174:172] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][175] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][176] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][180:177] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][181] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][182] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][186:183] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][187] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][188] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][189] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][193:190] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][194] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][195] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][196] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][199:197] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][200] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][201] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][203:202] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][206:204] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][207] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][208] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][212:209] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][213] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][214] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][218:215] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][219] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][220] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][221] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][225:222] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][226] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][227] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][228] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][231:229] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][232] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][233] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][234] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][235] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][238:236] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][239] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][240] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][244:241] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][245] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][246] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][250:247] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][251] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][252] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][253] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][257:254] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][258] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][259] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][260] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][263:261] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][264] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][265] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][266] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][267] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][270:268] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][271] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][272] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][276:273] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][278:277] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][282:279] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][283] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][284] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][285] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][289:286] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][290] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][291] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][292] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][295:293] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][296] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][297] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][299:298] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][302:300] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][303] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][304] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][308:305] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][310:309] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][314:311] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][315] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][316] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][317] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][321:318] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][322] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][323] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][324] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][327:325] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][328] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][329] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][330] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][331] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][334:332] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][335] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][336] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][340:337] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][342:341] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][346:343] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][347] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][348] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][349] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][353:350] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][354] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][355] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][356] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][359:357] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][360] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][361] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][363:362] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][366:364] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][368:367] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][372:369] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][373] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][374] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][378:375] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][379] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][380] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][381] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.key[1][383:382] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.valid |
Yes |
Yes |
T2,T3,T12 |
Yes |
T2,T3,T12 |
OUTPUT |
kmac_data_o.last |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
kmac_data_o.strb[7:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
kmac_data_o.data[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
kmac_data_o.valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
kmac_data_i.error |
Yes |
Yes |
T19,T64,T41 |
Yes |
T13,T14,T19 |
INPUT |
kmac_data_i.digest_share1[383:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
kmac_data_i.digest_share0[383:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
kmac_data_i.done |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
kmac_data_i.ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
kmac_en_masking_i |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
lc_keymgr_en_i[3:0] |
Yes |
Yes |
T1,T3,T13 |
Yes |
T1,T2,T3 |
INPUT |
lc_keymgr_div_i[127:0] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
otp_key_i.owner_seed_valid |
Yes |
Yes |
T3,T4,T52 |
Yes |
T3,T4,T52 |
INPUT |
otp_key_i.owner_seed[255:0] |
Yes |
Yes |
T4,T53,T52 |
Yes |
T4,T53,T52 |
INPUT |
otp_key_i.creator_seed_valid |
Yes |
Yes |
T3,T26,T4 |
Yes |
T3,T4,T52 |
INPUT |
otp_key_i.creator_seed[255:0] |
Yes |
Yes |
T3,T4,T53 |
Yes |
T3,T26,T4 |
INPUT |
otp_key_i.creator_root_key_share1_valid |
No |
No |
|
No |
|
INPUT |
otp_key_i.creator_root_key_share1[255:0] |
Yes |
Yes |
T3,T4,T53 |
Yes |
T3,T4,T53 |
INPUT |
otp_key_i.creator_root_key_share0_valid |
No |
No |
|
No |
|
INPUT |
otp_key_i.creator_root_key_share0[255:0] |
Yes |
Yes |
T3,T4,T53 |
Yes |
T3,T4,T53 |
INPUT |
otp_device_id_i[255:0] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][0] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][1] |
Yes |
Yes |
T3,T12,T17 |
Yes |
T3,T12,T17 |
INPUT |
flash_i.seeds[0][2] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][3] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][4] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][5] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][6] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][7] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][8] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][9] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][10] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][11] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][12] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][13] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][14] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][15] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][16] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][17] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][18] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][20:19] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][21] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][22] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][23] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][24] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][25] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][26] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][27] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][28] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][29] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][30] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][31] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][32] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][33] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][34] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][36:35] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][37] |
Yes |
Yes |
T3,T12,T17 |
Yes |
T3,T12,T17 |
INPUT |
flash_i.seeds[0][38] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][39] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][40] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][41] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][43:42] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][44] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][45] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][46] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][47] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][48] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][49] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][50] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][51] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][52] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][53] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][54] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][55] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][56] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][57] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][58] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][60:59] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][61] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][62] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][63] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][64] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][66:65] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][67] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][69:68] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][70] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][72:71] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][73] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][74] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][78:75] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][79] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][80] |
Yes |
Yes |
T3,T14,T19 |
Yes |
T3,T14,T19 |
INPUT |
flash_i.seeds[0][81] |
Yes |
Yes |
T3,T12,T17 |
Yes |
T3,T12,T17 |
INPUT |
flash_i.seeds[0][83:82] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][84] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][85] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][86] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][87] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][88] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][89] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][90] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][91] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][92] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][94:93] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][95] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][96] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][97] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][98] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][99] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][100] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][101] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][102] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][103] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][104] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][105] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][106] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][107] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][108] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][110:109] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][111] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][112] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][113] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][114] |
Yes |
Yes |
T3,T14,T17 |
Yes |
T3,T14,T17 |
INPUT |
flash_i.seeds[0][115] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][116] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][117] |
Yes |
Yes |
T3,T12,T17 |
Yes |
T3,T12,T17 |
INPUT |
flash_i.seeds[0][118] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][119] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][120] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][121] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][122] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][123] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][124] |
Yes |
Yes |
T3,T12,T17 |
Yes |
T3,T12,T17 |
INPUT |
flash_i.seeds[0][125] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][126] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][128:127] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][129] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][130] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][131] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][132] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][133] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][134] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][135] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][136] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][138:137] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][139] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][140] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][141] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][144:142] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][145] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][146] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][148:147] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][149] |
Yes |
Yes |
T3,T12,T19 |
Yes |
T3,T12,T19 |
INPUT |
flash_i.seeds[0][150] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][151] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][152] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][153] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][154] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][155] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][157:156] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][159:158] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][160] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][161] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][162] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][163] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][165:164] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][166] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][167] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][168] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][169] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][170] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][171] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][172] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][173] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][177:174] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][178] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][179] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][180] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][182:181] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][183] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][184] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][185] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][187:186] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][188] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][189] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][190] |
Yes |
Yes |
T3,T12,T17 |
Yes |
T3,T12,T17 |
INPUT |
flash_i.seeds[0][191] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][194:192] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][195] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][196] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][198:197] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][202:199] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][203] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][204] |
Yes |
Yes |
T3,T12,T17 |
Yes |
T3,T12,T17 |
INPUT |
flash_i.seeds[0][205] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][206] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][208:207] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][209] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][210] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][211] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][212] |
Yes |
Yes |
T3,T14,T17 |
Yes |
T3,T14,T17 |
INPUT |
flash_i.seeds[0][213] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][214] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][215] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][216] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][218:217] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][219] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][220] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][222:221] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][223] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][224] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][225] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][229:226] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][230] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][231] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][232] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][233] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][234] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][235] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][237:236] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][238] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][239] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][240] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][242:241] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][243] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][244] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][245] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][246] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][247] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][249:248] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][250] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][251] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][252] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][253] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[0][254] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[0][255] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][0] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][1] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][2] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][3] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][4] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][5] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][6] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][8:7] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][13:9] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][14] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][15] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][17:16] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][18] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][19] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][21:20] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][22] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][23] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][24] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][25] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][26] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][27] |
Yes |
Yes |
T3,T14,T17 |
Yes |
T3,T14,T17 |
INPUT |
flash_i.seeds[1][28] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][29] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][30] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][31] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][32] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][33] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][34] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][35] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][36] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][37] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][38] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][39] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][40] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][41] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][42] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][43] |
Yes |
Yes |
T3,T14,T17 |
Yes |
T3,T14,T17 |
INPUT |
flash_i.seeds[1][44] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][46:45] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][47] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][49:48] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][50] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][51] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][52] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][53] |
Yes |
Yes |
T3,T12,T17 |
Yes |
T3,T12,T17 |
INPUT |
flash_i.seeds[1][54] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][55] |
Yes |
Yes |
T3,T12,T17 |
Yes |
T3,T12,T17 |
INPUT |
flash_i.seeds[1][56] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][58:57] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][59] |
Yes |
Yes |
T3,T12,T17 |
Yes |
T3,T12,T17 |
INPUT |
flash_i.seeds[1][60] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][62:61] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][63] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][64] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][65] |
Yes |
Yes |
T3,T12,T17 |
Yes |
T3,T12,T17 |
INPUT |
flash_i.seeds[1][66] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][67] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][68] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][69] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][70] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][71] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][73:72] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][74] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][78:75] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][79] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][80] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][81] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][82] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][83] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][84] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][85] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][87:86] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][89:88] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][90] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][91] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][92] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][93] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][95:94] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][96] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][97] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][98] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][99] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][100] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][101] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][102] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][103] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][104] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][105] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][106] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][107] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][108] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][109] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][110] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][111] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][112] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][113] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][114] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][115] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][116] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][117] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][118] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][119] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][120] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][121] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][122] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][123] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][124] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][125] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][126] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][129:127] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][130] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][131] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][132] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][134:133] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][135] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][136] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][137] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][138] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][139] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][140] |
Yes |
Yes |
T1,T3,T14 |
Yes |
T1,T3,T14 |
INPUT |
flash_i.seeds[1][141] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][142] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][144:143] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][145] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][146] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][148:147] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][149] |
Yes |
Yes |
T3,T12,T17 |
Yes |
T3,T12,T17 |
INPUT |
flash_i.seeds[1][151:150] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][152] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][153] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][154] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][155] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][156] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][157] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][160:158] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][161] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][163:162] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][164] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][165] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][166] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][167] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][168] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][169] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][170] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][171] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][172] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][173] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][174] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][179:175] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][180] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][182:181] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][183] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][186:184] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][188:187] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][189] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][191:190] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][192] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][193] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][194] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][196:195] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][197] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][198] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][199] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][200] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][201] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][202] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][203] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][204] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][205] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][206] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][207] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][208] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][210:209] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][211] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][212] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][213] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][214] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][215] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][216] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][217] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][218] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][219] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][221:220] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][222] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][223] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][224] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][225] |
Yes |
Yes |
T3,T12,T17 |
Yes |
T3,T12,T17 |
INPUT |
flash_i.seeds[1][226] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][227] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][228] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][229] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][230] |
Yes |
Yes |
T1,T3,T14 |
Yes |
T1,T3,T14 |
INPUT |
flash_i.seeds[1][233:231] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][234] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][235] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][237:236] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][238] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][239] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][240] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][241] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][242] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][243] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][244] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][247:245] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][248] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][249] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][250] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][251] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][252] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
flash_i.seeds[1][253] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][254] |
Yes |
Yes |
T1,T3,T12 |
Yes |
T1,T3,T12 |
INPUT |
flash_i.seeds[1][255] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
edn_o.edn_req |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
edn_i.edn_bus[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
edn_i.edn_fips |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
edn_i.edn_ack |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rom_digest_i.valid |
Yes |
Yes |
T12,T85,T21 |
Yes |
T12,T85,T21 |
INPUT |
rom_digest_i.data[255:0] |
Yes |
Yes |
T3,T12,T14 |
Yes |
T3,T12,T14 |
INPUT |
intr_op_done_o |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[1].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[1].ack_p |
Yes |
Yes |
T13,T14,T19 |
Yes |
T13,T14,T19 |
INPUT |
alert_rx_i[1].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[1].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[1].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[1].alert_p |
Yes |
Yes |
T13,T14,T19 |
Yes |
T13,T14,T19 |
OUTPUT |
*Tests covering at least one bit in the range
Branch Coverage for Module :
keymgr
| Line No. | Total | Covered | Percent |
Branches |
|
49 |
47 |
95.92 |
TERNARY |
399 |
3 |
2 |
66.67 |
TERNARY |
482 |
4 |
4 |
100.00 |
TERNARY |
487 |
2 |
2 |
100.00 |
TERNARY |
713 |
3 |
2 |
66.67 |
TERNARY |
717 |
3 |
3 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
IF |
721 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 399 ((cdi_sel == 1'b0)) ?
-2-: 399 ((cdi_sel == 1'b1)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 482 ((dest_sel == Aes)) ?
-2-: 482 ((dest_sel == Kmac)) ?
-3-: 482 ((dest_sel == Otbn)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 487 (invalid_stage_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 713 (fault_errs) ?
-2-: 713 (fault_err_ack) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T13,T14,T19 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 717 (op_errs) ?
-2-: 717 (op_err_ack) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 721 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
keymgr
Assertion Details
AdvDataWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
884 |
884 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
AesKeyKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23252296 |
23080916 |
0 |
0 |
T1 |
32865 |
32733 |
0 |
0 |
T2 |
9650 |
9577 |
0 |
0 |
T3 |
30802 |
30674 |
0 |
0 |
T12 |
10986 |
10929 |
0 |
0 |
T13 |
15936 |
15758 |
0 |
0 |
T14 |
3419 |
3247 |
0 |
0 |
T15 |
153486 |
153432 |
0 |
0 |
T16 |
17653 |
17564 |
0 |
0 |
T17 |
3938 |
3885 |
0 |
0 |
T18 |
10352 |
10287 |
0 |
0 |
AlertKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23252296 |
23080916 |
0 |
0 |
T1 |
32865 |
32733 |
0 |
0 |
T2 |
9650 |
9577 |
0 |
0 |
T3 |
30802 |
30674 |
0 |
0 |
T12 |
10986 |
10929 |
0 |
0 |
T13 |
15936 |
15758 |
0 |
0 |
T14 |
3419 |
3247 |
0 |
0 |
T15 |
153486 |
153432 |
0 |
0 |
T16 |
17653 |
17564 |
0 |
0 |
T17 |
3938 |
3885 |
0 |
0 |
T18 |
10352 |
10287 |
0 |
0 |
ErrCntMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
884 |
884 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
FaultCntMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
884 |
884 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
FpvSecCmCtrlCntAlertCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23252296 |
80 |
0 |
0 |
T9 |
102722 |
20 |
0 |
0 |
T10 |
34446 |
10 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T34 |
2947 |
0 |
0 |
0 |
T42 |
0 |
20 |
0 |
0 |
T43 |
0 |
20 |
0 |
0 |
T44 |
19783 |
0 |
0 |
0 |
T47 |
3112 |
0 |
0 |
0 |
T98 |
13821 |
0 |
0 |
0 |
T99 |
21797 |
0 |
0 |
0 |
T100 |
77910 |
0 |
0 |
0 |
T101 |
2926 |
0 |
0 |
0 |
T102 |
9536 |
0 |
0 |
0 |
FpvSecCmCtrlDataFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23252296 |
80 |
0 |
0 |
T9 |
102722 |
20 |
0 |
0 |
T10 |
34446 |
10 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T34 |
2947 |
0 |
0 |
0 |
T42 |
0 |
20 |
0 |
0 |
T43 |
0 |
20 |
0 |
0 |
T44 |
19783 |
0 |
0 |
0 |
T47 |
3112 |
0 |
0 |
0 |
T98 |
13821 |
0 |
0 |
0 |
T99 |
21797 |
0 |
0 |
0 |
T100 |
77910 |
0 |
0 |
0 |
T101 |
2926 |
0 |
0 |
0 |
T102 |
9536 |
0 |
0 |
0 |
FpvSecCmCtrlMainFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23252296 |
80 |
0 |
0 |
T9 |
102722 |
20 |
0 |
0 |
T10 |
34446 |
10 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T34 |
2947 |
0 |
0 |
0 |
T42 |
0 |
20 |
0 |
0 |
T43 |
0 |
20 |
0 |
0 |
T44 |
19783 |
0 |
0 |
0 |
T47 |
3112 |
0 |
0 |
0 |
T98 |
13821 |
0 |
0 |
0 |
T99 |
21797 |
0 |
0 |
0 |
T100 |
77910 |
0 |
0 |
0 |
T101 |
2926 |
0 |
0 |
0 |
T102 |
9536 |
0 |
0 |
0 |
FpvSecCmCtrlOpFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23252296 |
80 |
0 |
0 |
T9 |
102722 |
20 |
0 |
0 |
T10 |
34446 |
10 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T34 |
2947 |
0 |
0 |
0 |
T42 |
0 |
20 |
0 |
0 |
T43 |
0 |
20 |
0 |
0 |
T44 |
19783 |
0 |
0 |
0 |
T47 |
3112 |
0 |
0 |
0 |
T98 |
13821 |
0 |
0 |
0 |
T99 |
21797 |
0 |
0 |
0 |
T100 |
77910 |
0 |
0 |
0 |
T101 |
2926 |
0 |
0 |
0 |
T102 |
9536 |
0 |
0 |
0 |
FpvSecCmKmacIfCntAlertCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23252296 |
80 |
0 |
0 |
T9 |
102722 |
20 |
0 |
0 |
T10 |
34446 |
10 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T34 |
2947 |
0 |
0 |
0 |
T42 |
0 |
20 |
0 |
0 |
T43 |
0 |
20 |
0 |
0 |
T44 |
19783 |
0 |
0 |
0 |
T47 |
3112 |
0 |
0 |
0 |
T98 |
13821 |
0 |
0 |
0 |
T99 |
21797 |
0 |
0 |
0 |
T100 |
77910 |
0 |
0 |
0 |
T101 |
2926 |
0 |
0 |
0 |
T102 |
9536 |
0 |
0 |
0 |
FpvSecCmKmacIfFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23252296 |
80 |
0 |
0 |
T9 |
102722 |
20 |
0 |
0 |
T10 |
34446 |
10 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T34 |
2947 |
0 |
0 |
0 |
T42 |
0 |
20 |
0 |
0 |
T43 |
0 |
20 |
0 |
0 |
T44 |
19783 |
0 |
0 |
0 |
T47 |
3112 |
0 |
0 |
0 |
T98 |
13821 |
0 |
0 |
0 |
T99 |
21797 |
0 |
0 |
0 |
T100 |
77910 |
0 |
0 |
0 |
T101 |
2926 |
0 |
0 |
0 |
T102 |
9536 |
0 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23252296 |
80 |
0 |
0 |
T9 |
102722 |
20 |
0 |
0 |
T10 |
34446 |
10 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T34 |
2947 |
0 |
0 |
0 |
T42 |
0 |
20 |
0 |
0 |
T43 |
0 |
20 |
0 |
0 |
T44 |
19783 |
0 |
0 |
0 |
T47 |
3112 |
0 |
0 |
0 |
T98 |
13821 |
0 |
0 |
0 |
T99 |
21797 |
0 |
0 |
0 |
T100 |
77910 |
0 |
0 |
0 |
T101 |
2926 |
0 |
0 |
0 |
T102 |
9536 |
0 |
0 |
0 |
FpvSecCmReseedCtrlCntAlertCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23252296 |
80 |
0 |
0 |
T9 |
102722 |
20 |
0 |
0 |
T10 |
34446 |
10 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T34 |
2947 |
0 |
0 |
0 |
T42 |
0 |
20 |
0 |
0 |
T43 |
0 |
20 |
0 |
0 |
T44 |
19783 |
0 |
0 |
0 |
T47 |
3112 |
0 |
0 |
0 |
T98 |
13821 |
0 |
0 |
0 |
T99 |
21797 |
0 |
0 |
0 |
T100 |
77910 |
0 |
0 |
0 |
T101 |
2926 |
0 |
0 |
0 |
T102 |
9536 |
0 |
0 |
0 |
FpvSecCmSideloadCtrlFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23252296 |
80 |
0 |
0 |
T9 |
102722 |
20 |
0 |
0 |
T10 |
34446 |
10 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T34 |
2947 |
0 |
0 |
0 |
T42 |
0 |
20 |
0 |
0 |
T43 |
0 |
20 |
0 |
0 |
T44 |
19783 |
0 |
0 |
0 |
T47 |
3112 |
0 |
0 |
0 |
T98 |
13821 |
0 |
0 |
0 |
T99 |
21797 |
0 |
0 |
0 |
T100 |
77910 |
0 |
0 |
0 |
T101 |
2926 |
0 |
0 |
0 |
T102 |
9536 |
0 |
0 |
0 |
GenDataWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
884 |
884 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
IdDataWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
884 |
884 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
IntrKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23252296 |
23080916 |
0 |
0 |
T1 |
32865 |
32733 |
0 |
0 |
T2 |
9650 |
9577 |
0 |
0 |
T3 |
30802 |
30674 |
0 |
0 |
T12 |
10986 |
10929 |
0 |
0 |
T13 |
15936 |
15758 |
0 |
0 |
T14 |
3419 |
3247 |
0 |
0 |
T15 |
153486 |
153432 |
0 |
0 |
T16 |
17653 |
17564 |
0 |
0 |
T17 |
3938 |
3885 |
0 |
0 |
T18 |
10352 |
10287 |
0 |
0 |
KmacDataKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22767746 |
22618242 |
0 |
0 |
T1 |
32865 |
32733 |
0 |
0 |
T2 |
9650 |
9577 |
0 |
0 |
T3 |
30802 |
30674 |
0 |
0 |
T12 |
10986 |
10929 |
0 |
0 |
T13 |
15936 |
15758 |
0 |
0 |
T14 |
1420 |
1340 |
0 |
0 |
T15 |
153486 |
153432 |
0 |
0 |
T16 |
17653 |
17564 |
0 |
0 |
T17 |
3938 |
3885 |
0 |
0 |
T18 |
10352 |
10287 |
0 |
0 |
KmacKeyKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23252296 |
23080916 |
0 |
0 |
T1 |
32865 |
32733 |
0 |
0 |
T2 |
9650 |
9577 |
0 |
0 |
T3 |
30802 |
30674 |
0 |
0 |
T12 |
10986 |
10929 |
0 |
0 |
T13 |
15936 |
15758 |
0 |
0 |
T14 |
3419 |
3247 |
0 |
0 |
T15 |
153486 |
153432 |
0 |
0 |
T16 |
17653 |
17564 |
0 |
0 |
T17 |
3938 |
3885 |
0 |
0 |
T18 |
10352 |
10287 |
0 |
0 |
KmacMaskCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
884 |
884 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
LfsrWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
884 |
884 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OtbnKeyKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23252296 |
23080916 |
0 |
0 |
T1 |
32865 |
32733 |
0 |
0 |
T2 |
9650 |
9577 |
0 |
0 |
T3 |
30802 |
30674 |
0 |
0 |
T12 |
10986 |
10929 |
0 |
0 |
T13 |
15936 |
15758 |
0 |
0 |
T14 |
3419 |
3247 |
0 |
0 |
T15 |
153486 |
153432 |
0 |
0 |
T16 |
17653 |
17564 |
0 |
0 |
T17 |
3938 |
3885 |
0 |
0 |
T18 |
10352 |
10287 |
0 |
0 |
OutputKeyDiff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
884 |
884 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
StageMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
884 |
884 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
TlAReadyKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23252296 |
23080916 |
0 |
0 |
T1 |
32865 |
32733 |
0 |
0 |
T2 |
9650 |
9577 |
0 |
0 |
T3 |
30802 |
30674 |
0 |
0 |
T12 |
10986 |
10929 |
0 |
0 |
T13 |
15936 |
15758 |
0 |
0 |
T14 |
3419 |
3247 |
0 |
0 |
T15 |
153486 |
153432 |
0 |
0 |
T16 |
17653 |
17564 |
0 |
0 |
T17 |
3938 |
3885 |
0 |
0 |
T18 |
10352 |
10287 |
0 |
0 |
TlDValidKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23252296 |
23080916 |
0 |
0 |
T1 |
32865 |
32733 |
0 |
0 |
T2 |
9650 |
9577 |
0 |
0 |
T3 |
30802 |
30674 |
0 |
0 |
T12 |
10986 |
10929 |
0 |
0 |
T13 |
15936 |
15758 |
0 |
0 |
T14 |
3419 |
3247 |
0 |
0 |
T15 |
153486 |
153432 |
0 |
0 |
T16 |
17653 |
17564 |
0 |
0 |
T17 |
3938 |
3885 |
0 |
0 |
T18 |
10352 |
10287 |
0 |
0 |