Line Coverage for Module :
keymgr
| Line No. | Total | Covered | Percent |
TOTAL | | 75 | 72 | 96.00 |
CONT_ASSIGN | 210 | 1 | 1 | 100.00 |
CONT_ASSIGN | 234 | 1 | 1 | 100.00 |
CONT_ASSIGN | 235 | 1 | 1 | 100.00 |
CONT_ASSIGN | 237 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 271 | 1 | 1 | 100.00 |
CONT_ASSIGN | 271 | 1 | 1 | 100.00 |
CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
CONT_ASSIGN | 326 | 1 | 1 | 100.00 |
CONT_ASSIGN | 328 | 1 | 1 | 100.00 |
CONT_ASSIGN | 346 | 1 | 1 | 100.00 |
CONT_ASSIGN | 353 | 1 | 1 | 100.00 |
CONT_ASSIGN | 369 | 1 | 1 | 100.00 |
CONT_ASSIGN | 399 | 1 | 1 | 100.00 |
CONT_ASSIGN | 404 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 436 | 1 | 1 | 100.00 |
CONT_ASSIGN | 442 | 1 | 1 | 100.00 |
CONT_ASSIGN | 455 | 1 | 1 | 100.00 |
CONT_ASSIGN | 457 | 1 | 1 | 100.00 |
CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
CONT_ASSIGN | 460 | 1 | 1 | 100.00 |
CONT_ASSIGN | 463 | 1 | 1 | 100.00 |
CONT_ASSIGN | 468 | 1 | 1 | 100.00 |
CONT_ASSIGN | 471 | 1 | 0 | 0.00 |
CONT_ASSIGN | 472 | 1 | 0 | 0.00 |
CONT_ASSIGN | 473 | 1 | 0 | 0.00 |
CONT_ASSIGN | 481 | 1 | 1 | 100.00 |
CONT_ASSIGN | 482 | 1 | 1 | 100.00 |
CONT_ASSIGN | 485 | 1 | 1 | 100.00 |
CONT_ASSIGN | 487 | 1 | 1 | 100.00 |
CONT_ASSIGN | 497 | 1 | 1 | 100.00 |
CONT_ASSIGN | 498 | 1 | 1 | 100.00 |
CONT_ASSIGN | 499 | 1 | 1 | 100.00 |
CONT_ASSIGN | 536 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
CONT_ASSIGN | 538 | 1 | 1 | 100.00 |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
CONT_ASSIGN | 540 | 1 | 1 | 100.00 |
CONT_ASSIGN | 541 | 1 | 1 | 100.00 |
CONT_ASSIGN | 542 | 1 | 1 | 100.00 |
CONT_ASSIGN | 543 | 1 | 1 | 100.00 |
CONT_ASSIGN | 550 | 1 | 1 | 100.00 |
CONT_ASSIGN | 551 | 1 | 1 | 100.00 |
CONT_ASSIGN | 552 | 1 | 1 | 100.00 |
CONT_ASSIGN | 553 | 1 | 1 | 100.00 |
CONT_ASSIGN | 670 | 1 | 1 | 100.00 |
CONT_ASSIGN | 671 | 1 | 1 | 100.00 |
CONT_ASSIGN | 672 | 1 | 1 | 100.00 |
CONT_ASSIGN | 674 | 1 | 1 | 100.00 |
CONT_ASSIGN | 675 | 1 | 1 | 100.00 |
CONT_ASSIGN | 676 | 1 | 1 | 100.00 |
CONT_ASSIGN | 677 | 1 | 1 | 100.00 |
CONT_ASSIGN | 678 | 1 | 1 | 100.00 |
CONT_ASSIGN | 679 | 1 | 1 | 100.00 |
CONT_ASSIGN | 680 | 1 | 1 | 100.00 |
CONT_ASSIGN | 681 | 1 | 1 | 100.00 |
CONT_ASSIGN | 682 | 1 | 1 | 100.00 |
CONT_ASSIGN | 683 | 1 | 1 | 100.00 |
CONT_ASSIGN | 684 | 1 | 1 | 100.00 |
CONT_ASSIGN | 685 | 1 | 1 | 100.00 |
CONT_ASSIGN | 686 | 1 | 1 | 100.00 |
CONT_ASSIGN | 687 | 1 | 1 | 100.00 |
CONT_ASSIGN | 711 | 1 | 1 | 100.00 |
CONT_ASSIGN | 713 | 1 | 1 | 100.00 |
CONT_ASSIGN | 716 | 1 | 1 | 100.00 |
CONT_ASSIGN | 717 | 1 | 1 | 100.00 |
ALWAYS | 721 | 5 | 5 | 100.00 |
CONT_ASSIGN | 731 | 1 | 1 | 100.00 |
CONT_ASSIGN | 748 | 1 | 1 | 100.00 |
CONT_ASSIGN | 779 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
210 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
237 |
1 |
1 |
238 |
1 |
1 |
271 |
2 |
2 |
275 |
1 |
1 |
326 |
1 |
1 |
328 |
1 |
1 |
346 |
1 |
1 |
353 |
1 |
1 |
369 |
1 |
1 |
399 |
1 |
1 |
404 |
1 |
1 |
417 |
1 |
1 |
419 |
1 |
1 |
436 |
1 |
1 |
442 |
1 |
1 |
455 |
1 |
1 |
457 |
1 |
1 |
459 |
1 |
1 |
460 |
1 |
1 |
463 |
1 |
1 |
468 |
1 |
1 |
471 |
0 |
1 |
472 |
0 |
1 |
473 |
0 |
1 |
481 |
1 |
1 |
482 |
1 |
1 |
485 |
1 |
1 |
487 |
1 |
1 |
497 |
1 |
1 |
498 |
1 |
1 |
499 |
1 |
1 |
536 |
1 |
1 |
537 |
1 |
1 |
538 |
1 |
1 |
539 |
1 |
1 |
540 |
1 |
1 |
541 |
1 |
1 |
542 |
1 |
1 |
543 |
1 |
1 |
550 |
1 |
1 |
551 |
1 |
1 |
552 |
1 |
1 |
553 |
1 |
1 |
670 |
1 |
1 |
671 |
1 |
1 |
672 |
1 |
1 |
674 |
1 |
1 |
675 |
1 |
1 |
676 |
1 |
1 |
677 |
1 |
1 |
678 |
1 |
1 |
679 |
1 |
1 |
680 |
1 |
1 |
681 |
1 |
1 |
682 |
1 |
1 |
683 |
1 |
1 |
684 |
1 |
1 |
685 |
1 |
1 |
686 |
1 |
1 |
687 |
1 |
1 |
711 |
1 |
1 |
713 |
1 |
1 |
716 |
1 |
1 |
717 |
1 |
1 |
721 |
1 |
1 |
722 |
1 |
1 |
723 |
1 |
1 |
725 |
1 |
1 |
726 |
1 |
1 |
731 |
1 |
1 |
748 |
1 |
1 |
779 |
|
unreachable |
Cond Coverage for Module :
keymgr
| Total | Covered | Percent |
Conditions | 183 | 179 | 97.81 |
Logical | 183 | 179 | 97.81 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 210
EXPRESSION (ctrl_lfsr_en | data_lfsr_en | sideload_lfsr_en)
------1----- ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T1,T3,T15 |
1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 336
EXPRESSION (op_start & op_done)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T12,T13,T14 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 353
EXPRESSION (reg2hw.sw_binding_regwen.qe & ((~reg2hw.sw_binding_regwen.q)))
-------------1------------- ---------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 369
EXPRESSION (sw_binding_regwen & cfg_regwen)
--------1-------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 399
EXPRESSION ((cdi_sel == 1'b0) ? reg2hw.sealing_sw_binding : ((cdi_sel == 1'b1) ? reg2hw.attest_sw_binding : RndCnstCdi))
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 399
SUB-EXPRESSION (cdi_sel == 1'b0)
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 399
SUB-EXPRESSION ((cdi_sel == 1'b1) ? reg2hw.attest_sw_binding : RndCnstCdi)
--------1--------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 399
SUB-EXPRESSION (cdi_sel == 1'b1)
--------1--------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 442
EXPRESSION (creator_seed_vld & devid_vld & health_state_vld & rom_digest_vld)
--------1------- ----2---- --------3------- -------4------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T81,T88,T89 |
1 | 0 | 1 | 1 | Covered | T85,T90,T91 |
1 | 1 | 0 | 1 | Covered | T19,T92,T93 |
1 | 1 | 1 | 0 | Covered | T2,T5,T94 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 482
EXPRESSION ((dest_sel == Aes) ? aes_seed : ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed)))
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
LINE 482
SUB-EXPRESSION (dest_sel == Aes)
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
LINE 482
SUB-EXPRESSION ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed))
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 482
SUB-EXPRESSION (dest_sel == Kmac)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 482
SUB-EXPRESSION ((dest_sel == Otbn) ? otbn_seed : none_seed)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
LINE 482
SUB-EXPRESSION (dest_sel == Otbn)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
LINE 487
EXPRESSION (invalid_stage_sel ? ({GenLfsrCopies {lfsr[31:0]}}) : ({reg2hw.key_version, reg2hw.salt, dest_seed, output_key}))
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 536
EXPRESSION (adv_en | id_en | gen_en)
---1-- --2-- ---3--
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T3,T4 |
0 | 1 | 0 | Covered | T1,T5,T4 |
1 | 0 | 0 | Covered | T1,T3,T4 |
LINE 537
EXPRESSION (adv_en & (stage_sel == Creator) & ((~creator_seed_vld)))
---1-- -----------2---------- ----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T19,T95,T96 |
1 | 0 | 1 | Covered | T84,T88,T90 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T19,T96,T97 |
LINE 537
SUB-EXPRESSION (stage_sel == Creator)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 538
EXPRESSION (adv_en & (stage_sel == OwnerInt) & ((~owner_seed_vld)))
---1-- -----------2----------- ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T98,T97 |
1 | 0 | 1 | Covered | T19,T25,T90 |
1 | 1 | 0 | Covered | T1,T3,T15 |
1 | 1 | 1 | Not Covered | |
LINE 538
SUB-EXPRESSION (stage_sel == OwnerInt)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T15 |
LINE 539
EXPRESSION (adv_en & (stage_sel == Creator) & ((~devid_vld)))
---1-- -----------2---------- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T19,T26,T99 |
1 | 0 | 1 | Covered | T84,T100,T90 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T19,T26,T96 |
LINE 539
SUB-EXPRESSION (stage_sel == Creator)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 540
EXPRESSION (adv_en & (stage_sel == Creator) & ((~health_state_vld)))
---1-- -----------2---------- ----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T19,T25,T26 |
1 | 0 | 1 | Covered | T84,T90,T101 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T19,T25,T26 |
LINE 540
SUB-EXPRESSION (stage_sel == Creator)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 541
EXPRESSION (gen_en & ((~key_version_vld)))
---1-- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T19,T27,T28 |
LINE 542
EXPRESSION (valid_op & ((~key_vld)))
----1--- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T21,T23,T24 |
LINE 543
EXPRESSION (adv_en & (stage_sel == Creator) & ((~rom_digest_vld)))
---1-- -----------2---------- ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T19,T25,T26 |
1 | 0 | 1 | Covered | T84,T25,T100 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T19,T25,T26 |
LINE 543
SUB-EXPRESSION (stage_sel == Creator)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 550
EXPRESSION (((~key_vld)) | ((~adv_dvalid[stage_sel])))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T19,T25,T26 |
1 | 0 | Covered | T1,T2,T3 |
LINE 552
EXPRESSION (((~key_vld)) | ((~key_version_vld)))
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T3 |
LINE 553
EXPRESSION (((~key_vld)) | ((~key_version_vld)))
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(0 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T5,T4 |
0 | 1 | Covered | T5,T15,T17 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(1 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T5,T4 |
0 | 1 | Covered | T5,T15,T17 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(2 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T5,T4 |
0 | 1 | Covered | T5,T15,T17 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(3 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T5,T4 |
0 | 1 | Covered | T5,T15,T17 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(4 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T5,T4 |
0 | 1 | Covered | T5,T15,T17 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(5 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T5,T4 |
0 | 1 | Covered | T5,T15,T17 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(6 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T5,T4 |
0 | 1 | Covered | T5,T15,T17 |
1 | 0 | Covered | T1,T2,T3 |
LINE 623
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(7 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T2,T3 |
LINE 623
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T5,T4 |
0 | 1 | Covered | T5,T15,T17 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(0 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T5,T4 |
0 | 1 | Covered | T5,T15,T17 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(1 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T5,T4 |
0 | 1 | Covered | T5,T15,T17 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(2 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T5,T4 |
0 | 1 | Covered | T5,T15,T17 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(3 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T5,T4 |
0 | 1 | Covered | T5,T15,T17 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(4 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T5,T4 |
0 | 1 | Covered | T5,T15,T17 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(5 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T5,T4 |
0 | 1 | Covered | T5,T15,T17 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(6 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T5,T4 |
0 | 1 | Covered | T5,T15,T17 |
1 | 0 | Covered | T1,T2,T3 |
LINE 630
EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(7 * 32)+:32])
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T2,T3 |
LINE 630
SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
-------1------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T5,T4 |
0 | 1 | Covered | T5,T15,T17 |
1 | 0 | Covered | T1,T2,T3 |
LINE 713
EXPRESSION (fault_errs ? 1'b1 : (fault_err_ack ? 1'b0 : fault_err_req_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T15,T17 |
LINE 713
SUB-EXPRESSION (fault_err_ack ? 1'b0 : fault_err_req_q)
------1------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 717
EXPRESSION (op_errs ? 1'b1 : (op_err_ack ? 1'b0 : op_err_req_q))
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 717
SUB-EXPRESSION (op_err_ack ? 1'b0 : op_err_req_q)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 731
EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
-----------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T102,T103,T104 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T102,T103,T104 |
LINE 748
EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
-------------------1------------------- --------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T102,T103,T104 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T102,T103,T104 |
Toggle Coverage for Module :
keymgr
| Total | Covered | Percent |
Totals |
67 |
65 |
97.01 |
Total Bits |
10068 |
10064 |
99.96 |
Total Bits 0->1 |
5034 |
5032 |
99.96 |
Total Bits 1->0 |
5034 |
5032 |
99.96 |
| | | |
Ports |
67 |
65 |
97.01 |
Port Bits |
10068 |
10064 |
99.96 |
Port Bits 0->1 |
5034 |
5032 |
99.96 |
Port Bits 1->0 |
5034 |
5032 |
99.96 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T2,T5,T15 |
Yes |
T1,T2,T3 |
INPUT |
rst_shadowed_ni |
Yes |
Yes |
T2,T5,T15 |
Yes |
T1,T2,T3 |
INPUT |
clk_edn_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_edn_ni |
Yes |
Yes |
T2,T5,T15 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T2,T3,T5 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T2,T3,T16 |
Yes |
T2,T3,T16 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_source[7:0] |
Yes |
Yes |
T2,T3,T5 |
Yes |
T2,T3,T5 |
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T35,T55,T45 |
Yes |
T35,T55,T45 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_source[7:0] |
Yes |
Yes |
T2,T3,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][18:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][19] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][40:20] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][41] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][45:42] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][46] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][55:47] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][56] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][58:57] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][59] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][68:60] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][69] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][72:70] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][73] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][77:74] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][78] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][95:79] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][96] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][97] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][98] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][109:99] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][110] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][116:111] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][117] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][126:118] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][127] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][151:128] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][152] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][165:153] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][166] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][168:167] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][169] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][170] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][171] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][173:172] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][174] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][188:175] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][189] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][190] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][191] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][193:192] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][194] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][206:195] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][207] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][208] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][209] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][212:210] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][213] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][222:214] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][223] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][243:224] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][244] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[0][255:245] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][2:1] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][3] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][6:4] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][8:7] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][13:9] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][14] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][26:15] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][27] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][60:28] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][62:61] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][65:63] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][66] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][80:67] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][81] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][82] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][83] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][98:84] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][99] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][106:100] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][107] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][119:108] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][120] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][127:121] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][128] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][146:129] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][147] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][151:148] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][152] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][156:153] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][157] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][166:158] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][168:167] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][175:169] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][176] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][192:177] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][193] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][196:194] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][197] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][202:198] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][203] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][221:204] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][222] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][230:223] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][231] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][232] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][233] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][236:234] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][237] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][239:238] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][240] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][242:241] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][243] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][253:244] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][254] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.key[1][255] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
aes_key_o.valid |
Yes |
Yes |
T1,T15,T16 |
Yes |
T1,T15,T16 |
OUTPUT |
kmac_key_o.key[1:0][255:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
kmac_key_o.valid |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T3,T5 |
OUTPUT |
otbn_key_o.key[1:0][383:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
otbn_key_o.valid |
Yes |
Yes |
T1,T4,T16 |
Yes |
T1,T4,T16 |
OUTPUT |
kmac_data_o.last |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T3,T5 |
OUTPUT |
kmac_data_o.strb[7:0] |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T3,T5 |
OUTPUT |
kmac_data_o.data[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
kmac_data_o.valid |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T3,T5 |
OUTPUT |
kmac_data_i.error |
Yes |
Yes |
T15,T22,T62 |
Yes |
T5,T15,T35 |
INPUT |
kmac_data_i.digest_share1[383:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
kmac_data_i.digest_share0[383:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T5 |
INPUT |
kmac_data_i.done |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T3,T5 |
INPUT |
kmac_data_i.ready |
Yes |
Yes |
T2,T5,T4 |
Yes |
T1,T2,T3 |
INPUT |
kmac_en_masking_i |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
lc_keymgr_en_i[3:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T2,T5,T4 |
INPUT |
lc_keymgr_div_i[127:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
otp_key_i.owner_seed_valid |
Yes |
Yes |
T5,T17,T55 |
Yes |
T55,T51,T56 |
INPUT |
otp_key_i.owner_seed[255:0] |
Yes |
Yes |
T5,T55,T44 |
Yes |
T17,T55,T44 |
INPUT |
otp_key_i.creator_seed_valid |
Yes |
Yes |
T44,T85,T42 |
Yes |
T5,T17,T44 |
INPUT |
otp_key_i.creator_seed[255:0] |
Yes |
Yes |
T5,T17,T55 |
Yes |
T55,T44,T27 |
INPUT |
otp_key_i.creator_root_key_share1_valid |
No |
No |
|
No |
|
INPUT |
otp_key_i.creator_root_key_share1[255:0] |
Yes |
Yes |
T5,T17,T55 |
Yes |
T55,T51,T56 |
INPUT |
otp_key_i.creator_root_key_share0_valid |
No |
No |
|
No |
|
INPUT |
otp_key_i.creator_root_key_share0[255:0] |
Yes |
Yes |
T55,T44,T27 |
Yes |
T55,T44,T27 |
INPUT |
otp_device_id_i[255:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][1:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][2] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][10:3] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][11] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][12] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][13] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][15:14] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][16] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][17] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][18] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][19] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][20] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][22:21] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][23] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][24] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][25] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
flash_i.seeds[0][26] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][32:27] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][33] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][35:34] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][36] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][37] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][38] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][39] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][40] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][41] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][42] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][43] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][44] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][45] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][52:46] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][53] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][58:54] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][59] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][65:60] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][66] |
Yes |
Yes |
T2,T5,T4 |
Yes |
T2,T5,T4 |
INPUT |
flash_i.seeds[0][67] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][68] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][69] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][73:70] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][74] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][77:75] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][78] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][79] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][80] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][81] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][82] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][83] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][84] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][87:85] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][88] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][89] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][93:90] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][94] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][98:95] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][99] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][104:100] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][105] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][106] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][107] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][108] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][109] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][110] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][111] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][115:112] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][116] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][118:117] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][119] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T2,T4 |
INPUT |
flash_i.seeds[0][120] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][121] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][122] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][127:123] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][128] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][129] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][130] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][131] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][135:132] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][136] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][145:137] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][146] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][149:147] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][150] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][151] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][154:152] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][155] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][165:156] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][166] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][167] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T2,T4 |
INPUT |
flash_i.seeds[0][170:168] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][171] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][179:172] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][180] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][183:181] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][184] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][186:185] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][187] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][188] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][189] |
Yes |
Yes |
T2,T5,T4 |
Yes |
T2,T5,T4 |
INPUT |
flash_i.seeds[0][190] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][200:191] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][201] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][210:202] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][211] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][212] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][217:213] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][218] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][220:219] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][221] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][223:222] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][224] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][226:225] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][227] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][228] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][232:229] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][233] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][234] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][235] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][241:236] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][242] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][243] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][244] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][246:245] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][247] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][254:248] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[0][255] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][1:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][2] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][4:3] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][5] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][8:6] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][9] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][13:10] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][14] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][15] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][16] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][17] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T2,T4 |
INPUT |
flash_i.seeds[1][18] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T2,T4 |
INPUT |
flash_i.seeds[1][19] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][20] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][21] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][22] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][23] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][28:24] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][29] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][31:30] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][32] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][33] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][34] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][36:35] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][37] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T2,T4 |
INPUT |
flash_i.seeds[1][38] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][39] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][40] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][41] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][43:42] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][44] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][45] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][46] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][51:47] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][52] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][53] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][54] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][55] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][56] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][57] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][58] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][59] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][62:60] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][63] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][78:64] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][79] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][87:80] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][88] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][90:89] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][95:91] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][96] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][99:97] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][100] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][101] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][105:102] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][106] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][107] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][113:108] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][114] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][115] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][116] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][117] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][123:118] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][124] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][125] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][126] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][127] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][128] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][130:129] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][131] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][134:132] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][135] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][136] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][137] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][138] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][139] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][141:140] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][142] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][145:143] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][146] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][151:147] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][152] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][153] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][156:154] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][158:157] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][159] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][160] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][161] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][162] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][163] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][164] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][166:165] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][167] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][168] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][169] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][170] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][173:171] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][174] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][185:175] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][186] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][187] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][194:188] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][195] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][199:196] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][200] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][201] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][202] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][207:203] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][208] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][209] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][211:210] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][220:212] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][221] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][222] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][223] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][224] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][225] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][226] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][227] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][229:228] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][230] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][231] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][232] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][233] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][251:234] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][252] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][253] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][254] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
flash_i.seeds[1][255] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
edn_o.edn_req |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
edn_i.edn_bus[31:0] |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T2,T3 |
INPUT |
edn_i.edn_fips |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T3,T5 |
INPUT |
edn_i.edn_ack |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rom_digest_i.valid |
Yes |
Yes |
T5,T17,T19 |
Yes |
T5,T17,T19 |
INPUT |
rom_digest_i.data[255:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
intr_op_done_o |
Yes |
Yes |
T1,T5,T16 |
Yes |
T1,T5,T16 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[1].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[1].ack_p |
Yes |
Yes |
T5,T15,T17 |
Yes |
T5,T15,T17 |
INPUT |
alert_rx_i[1].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[1].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[1].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[1].alert_p |
Yes |
Yes |
T5,T15,T17 |
Yes |
T5,T15,T17 |
OUTPUT |
*Tests covering at least one bit in the range
Branch Coverage for Module :
keymgr
| Line No. | Total | Covered | Percent |
Branches |
|
49 |
47 |
95.92 |
TERNARY |
399 |
3 |
2 |
66.67 |
TERNARY |
482 |
4 |
4 |
100.00 |
TERNARY |
487 |
2 |
2 |
100.00 |
TERNARY |
713 |
3 |
2 |
66.67 |
TERNARY |
717 |
3 |
3 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
TERNARY |
623 |
2 |
2 |
100.00 |
TERNARY |
630 |
2 |
2 |
100.00 |
IF |
721 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 399 ((cdi_sel == 1'b0)) ?
-2-: 399 ((cdi_sel == 1'b1)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 482 ((dest_sel == Aes)) ?
-2-: 482 ((dest_sel == Kmac)) ?
-3-: 482 ((dest_sel == Otbn)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 487 (invalid_stage_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 713 (fault_errs) ?
-2-: 713 (fault_err_ack) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T5,T15,T17 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 717 (op_errs) ?
-2-: 717 (op_err_ack) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 623 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 630 (((~data_sw_en) | wipe_key)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 721 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
keymgr
Assertion Details
AdvDataWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
872 |
872 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
AesKeyKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22393006 |
22227738 |
0 |
0 |
T1 |
4097 |
4031 |
0 |
0 |
T2 |
9706 |
9552 |
0 |
0 |
T3 |
8105 |
8047 |
0 |
0 |
T4 |
11178 |
11102 |
0 |
0 |
T5 |
3534 |
3367 |
0 |
0 |
T15 |
12174 |
11999 |
0 |
0 |
T16 |
5204 |
5145 |
0 |
0 |
T17 |
18727 |
18565 |
0 |
0 |
T18 |
8980 |
8910 |
0 |
0 |
T19 |
2958 |
2875 |
0 |
0 |
AlertKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22393006 |
22227738 |
0 |
0 |
T1 |
4097 |
4031 |
0 |
0 |
T2 |
9706 |
9552 |
0 |
0 |
T3 |
8105 |
8047 |
0 |
0 |
T4 |
11178 |
11102 |
0 |
0 |
T5 |
3534 |
3367 |
0 |
0 |
T15 |
12174 |
11999 |
0 |
0 |
T16 |
5204 |
5145 |
0 |
0 |
T17 |
18727 |
18565 |
0 |
0 |
T18 |
8980 |
8910 |
0 |
0 |
T19 |
2958 |
2875 |
0 |
0 |
ErrCntMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
872 |
872 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
FaultCntMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
872 |
872 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
FpvSecCmCtrlCntAlertCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22393006 |
80 |
0 |
0 |
T12 |
47611 |
20 |
0 |
0 |
T13 |
0 |
10 |
0 |
0 |
T14 |
0 |
20 |
0 |
0 |
T41 |
0 |
10 |
0 |
0 |
T67 |
4922 |
0 |
0 |
0 |
T103 |
1341 |
0 |
0 |
0 |
T105 |
0 |
20 |
0 |
0 |
T106 |
6065 |
0 |
0 |
0 |
T107 |
9136 |
0 |
0 |
0 |
T108 |
73852 |
0 |
0 |
0 |
T109 |
115769 |
0 |
0 |
0 |
T110 |
1756 |
0 |
0 |
0 |
T111 |
1913 |
0 |
0 |
0 |
T112 |
3432 |
0 |
0 |
0 |
FpvSecCmCtrlDataFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22393006 |
80 |
0 |
0 |
T12 |
47611 |
20 |
0 |
0 |
T13 |
0 |
10 |
0 |
0 |
T14 |
0 |
20 |
0 |
0 |
T41 |
0 |
10 |
0 |
0 |
T67 |
4922 |
0 |
0 |
0 |
T103 |
1341 |
0 |
0 |
0 |
T105 |
0 |
20 |
0 |
0 |
T106 |
6065 |
0 |
0 |
0 |
T107 |
9136 |
0 |
0 |
0 |
T108 |
73852 |
0 |
0 |
0 |
T109 |
115769 |
0 |
0 |
0 |
T110 |
1756 |
0 |
0 |
0 |
T111 |
1913 |
0 |
0 |
0 |
T112 |
3432 |
0 |
0 |
0 |
FpvSecCmCtrlMainFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22393006 |
80 |
0 |
0 |
T12 |
47611 |
20 |
0 |
0 |
T13 |
0 |
10 |
0 |
0 |
T14 |
0 |
20 |
0 |
0 |
T41 |
0 |
10 |
0 |
0 |
T67 |
4922 |
0 |
0 |
0 |
T103 |
1341 |
0 |
0 |
0 |
T105 |
0 |
20 |
0 |
0 |
T106 |
6065 |
0 |
0 |
0 |
T107 |
9136 |
0 |
0 |
0 |
T108 |
73852 |
0 |
0 |
0 |
T109 |
115769 |
0 |
0 |
0 |
T110 |
1756 |
0 |
0 |
0 |
T111 |
1913 |
0 |
0 |
0 |
T112 |
3432 |
0 |
0 |
0 |
FpvSecCmCtrlOpFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22393006 |
80 |
0 |
0 |
T12 |
47611 |
20 |
0 |
0 |
T13 |
0 |
10 |
0 |
0 |
T14 |
0 |
20 |
0 |
0 |
T41 |
0 |
10 |
0 |
0 |
T67 |
4922 |
0 |
0 |
0 |
T103 |
1341 |
0 |
0 |
0 |
T105 |
0 |
20 |
0 |
0 |
T106 |
6065 |
0 |
0 |
0 |
T107 |
9136 |
0 |
0 |
0 |
T108 |
73852 |
0 |
0 |
0 |
T109 |
115769 |
0 |
0 |
0 |
T110 |
1756 |
0 |
0 |
0 |
T111 |
1913 |
0 |
0 |
0 |
T112 |
3432 |
0 |
0 |
0 |
FpvSecCmKmacIfCntAlertCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22393006 |
80 |
0 |
0 |
T12 |
47611 |
20 |
0 |
0 |
T13 |
0 |
10 |
0 |
0 |
T14 |
0 |
20 |
0 |
0 |
T41 |
0 |
10 |
0 |
0 |
T67 |
4922 |
0 |
0 |
0 |
T103 |
1341 |
0 |
0 |
0 |
T105 |
0 |
20 |
0 |
0 |
T106 |
6065 |
0 |
0 |
0 |
T107 |
9136 |
0 |
0 |
0 |
T108 |
73852 |
0 |
0 |
0 |
T109 |
115769 |
0 |
0 |
0 |
T110 |
1756 |
0 |
0 |
0 |
T111 |
1913 |
0 |
0 |
0 |
T112 |
3432 |
0 |
0 |
0 |
FpvSecCmKmacIfFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22393006 |
80 |
0 |
0 |
T12 |
47611 |
20 |
0 |
0 |
T13 |
0 |
10 |
0 |
0 |
T14 |
0 |
20 |
0 |
0 |
T41 |
0 |
10 |
0 |
0 |
T67 |
4922 |
0 |
0 |
0 |
T103 |
1341 |
0 |
0 |
0 |
T105 |
0 |
20 |
0 |
0 |
T106 |
6065 |
0 |
0 |
0 |
T107 |
9136 |
0 |
0 |
0 |
T108 |
73852 |
0 |
0 |
0 |
T109 |
115769 |
0 |
0 |
0 |
T110 |
1756 |
0 |
0 |
0 |
T111 |
1913 |
0 |
0 |
0 |
T112 |
3432 |
0 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22393006 |
80 |
0 |
0 |
T12 |
47611 |
20 |
0 |
0 |
T13 |
0 |
10 |
0 |
0 |
T14 |
0 |
20 |
0 |
0 |
T41 |
0 |
10 |
0 |
0 |
T67 |
4922 |
0 |
0 |
0 |
T103 |
1341 |
0 |
0 |
0 |
T105 |
0 |
20 |
0 |
0 |
T106 |
6065 |
0 |
0 |
0 |
T107 |
9136 |
0 |
0 |
0 |
T108 |
73852 |
0 |
0 |
0 |
T109 |
115769 |
0 |
0 |
0 |
T110 |
1756 |
0 |
0 |
0 |
T111 |
1913 |
0 |
0 |
0 |
T112 |
3432 |
0 |
0 |
0 |
FpvSecCmReseedCtrlCntAlertCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22393006 |
80 |
0 |
0 |
T12 |
47611 |
20 |
0 |
0 |
T13 |
0 |
10 |
0 |
0 |
T14 |
0 |
20 |
0 |
0 |
T41 |
0 |
10 |
0 |
0 |
T67 |
4922 |
0 |
0 |
0 |
T103 |
1341 |
0 |
0 |
0 |
T105 |
0 |
20 |
0 |
0 |
T106 |
6065 |
0 |
0 |
0 |
T107 |
9136 |
0 |
0 |
0 |
T108 |
73852 |
0 |
0 |
0 |
T109 |
115769 |
0 |
0 |
0 |
T110 |
1756 |
0 |
0 |
0 |
T111 |
1913 |
0 |
0 |
0 |
T112 |
3432 |
0 |
0 |
0 |
FpvSecCmSideloadCtrlFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22393006 |
80 |
0 |
0 |
T12 |
47611 |
20 |
0 |
0 |
T13 |
0 |
10 |
0 |
0 |
T14 |
0 |
20 |
0 |
0 |
T41 |
0 |
10 |
0 |
0 |
T67 |
4922 |
0 |
0 |
0 |
T103 |
1341 |
0 |
0 |
0 |
T105 |
0 |
20 |
0 |
0 |
T106 |
6065 |
0 |
0 |
0 |
T107 |
9136 |
0 |
0 |
0 |
T108 |
73852 |
0 |
0 |
0 |
T109 |
115769 |
0 |
0 |
0 |
T110 |
1756 |
0 |
0 |
0 |
T111 |
1913 |
0 |
0 |
0 |
T112 |
3432 |
0 |
0 |
0 |
GenDataWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
872 |
872 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
IdDataWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
872 |
872 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
IntrKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22393006 |
22227738 |
0 |
0 |
T1 |
4097 |
4031 |
0 |
0 |
T2 |
9706 |
9552 |
0 |
0 |
T3 |
8105 |
8047 |
0 |
0 |
T4 |
11178 |
11102 |
0 |
0 |
T5 |
3534 |
3367 |
0 |
0 |
T15 |
12174 |
11999 |
0 |
0 |
T16 |
5204 |
5145 |
0 |
0 |
T17 |
18727 |
18565 |
0 |
0 |
T18 |
8980 |
8910 |
0 |
0 |
T19 |
2958 |
2875 |
0 |
0 |
KmacDataKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
21907475 |
21763997 |
0 |
0 |
T1 |
4097 |
4031 |
0 |
0 |
T2 |
9706 |
9552 |
0 |
0 |
T3 |
8105 |
8047 |
0 |
0 |
T4 |
11178 |
11102 |
0 |
0 |
T5 |
3534 |
3367 |
0 |
0 |
T15 |
6201 |
6112 |
0 |
0 |
T16 |
5204 |
5145 |
0 |
0 |
T17 |
18727 |
18565 |
0 |
0 |
T18 |
8980 |
8910 |
0 |
0 |
T19 |
2958 |
2875 |
0 |
0 |
KmacKeyKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22393006 |
22227738 |
0 |
0 |
T1 |
4097 |
4031 |
0 |
0 |
T2 |
9706 |
9552 |
0 |
0 |
T3 |
8105 |
8047 |
0 |
0 |
T4 |
11178 |
11102 |
0 |
0 |
T5 |
3534 |
3367 |
0 |
0 |
T15 |
12174 |
11999 |
0 |
0 |
T16 |
5204 |
5145 |
0 |
0 |
T17 |
18727 |
18565 |
0 |
0 |
T18 |
8980 |
8910 |
0 |
0 |
T19 |
2958 |
2875 |
0 |
0 |
KmacMaskCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
872 |
872 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
LfsrWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
872 |
872 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OtbnKeyKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22393006 |
22227738 |
0 |
0 |
T1 |
4097 |
4031 |
0 |
0 |
T2 |
9706 |
9552 |
0 |
0 |
T3 |
8105 |
8047 |
0 |
0 |
T4 |
11178 |
11102 |
0 |
0 |
T5 |
3534 |
3367 |
0 |
0 |
T15 |
12174 |
11999 |
0 |
0 |
T16 |
5204 |
5145 |
0 |
0 |
T17 |
18727 |
18565 |
0 |
0 |
T18 |
8980 |
8910 |
0 |
0 |
T19 |
2958 |
2875 |
0 |
0 |
OutputKeyDiff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
872 |
872 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
StageMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
872 |
872 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
TlAReadyKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22393006 |
22227738 |
0 |
0 |
T1 |
4097 |
4031 |
0 |
0 |
T2 |
9706 |
9552 |
0 |
0 |
T3 |
8105 |
8047 |
0 |
0 |
T4 |
11178 |
11102 |
0 |
0 |
T5 |
3534 |
3367 |
0 |
0 |
T15 |
12174 |
11999 |
0 |
0 |
T16 |
5204 |
5145 |
0 |
0 |
T17 |
18727 |
18565 |
0 |
0 |
T18 |
8980 |
8910 |
0 |
0 |
T19 |
2958 |
2875 |
0 |
0 |
TlDValidKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22393006 |
22227738 |
0 |
0 |
T1 |
4097 |
4031 |
0 |
0 |
T2 |
9706 |
9552 |
0 |
0 |
T3 |
8105 |
8047 |
0 |
0 |
T4 |
11178 |
11102 |
0 |
0 |
T5 |
3534 |
3367 |
0 |
0 |
T15 |
12174 |
11999 |
0 |
0 |
T16 |
5204 |
5145 |
0 |
0 |
T17 |
18727 |
18565 |
0 |
0 |
T18 |
8980 |
8910 |
0 |
0 |
T19 |
2958 |
2875 |
0 |
0 |