Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.94	96.00	97.81	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24120970	11841	0	0
attest_sw_binding_0_rd_A	24120970	2373	0	0
attest_sw_binding_1_rd_A	24120970	2378	0	0
attest_sw_binding_2_rd_A	24120970	2400	0	0
attest_sw_binding_3_rd_A	24120970	2292	0	0
attest_sw_binding_4_rd_A	24120970	2262	0	0
attest_sw_binding_5_rd_A	24120970	2317	0	0
attest_sw_binding_6_rd_A	24120970	2467	0	0
attest_sw_binding_7_rd_A	24120970	2367	0	0
intr_enable_rd_A	24120970	2935	0	0
key_version_rd_A	24120970	2474	0	0
max_creator_key_ver_regwen_rd_A	24120970	2371	0	0
max_owner_int_key_ver_regwen_rd_A	24120970	2294	0	0
max_owner_key_ver_regwen_rd_A	24120970	2361	0	0
reseed_interval_regwen_rd_A	24120970	2511	0	0
salt_0_rd_A	24120970	2353	0	0
salt_1_rd_A	24120970	2435	0	0
salt_2_rd_A	24120970	2358	0	0
salt_3_rd_A	24120970	2385	0	0
salt_4_rd_A	24120970	2328	0	0
salt_5_rd_A	24120970	2385	0	0
salt_6_rd_A	24120970	2306	0	0
salt_7_rd_A	24120970	2478	0	0
sealing_sw_binding_0_rd_A	24120970	2384	0	0
sealing_sw_binding_1_rd_A	24120970	2438	0	0
sealing_sw_binding_2_rd_A	24120970	2324	0	0
sealing_sw_binding_3_rd_A	24120970	2361	0	0
sealing_sw_binding_4_rd_A	24120970	2387	0	0
sealing_sw_binding_5_rd_A	24120970	2370	0	0
sealing_sw_binding_6_rd_A	24120970	2264	0	0
sealing_sw_binding_7_rd_A	24120970	2376	0	0
sideload_clear_rd_A	24120970	2360	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	11841	0	0
T6	0	52	0	0
T27	70144	0	0	0
T28	7107	0	0	0
T44	29351	0	0	0
T45	4108	0	0	0
T48	0	220	0	0
T51	4468	0	0	0
T55	18847	656	0	0
T56	0	40	0	0
T70	0	82	0	0
T82	0	152	0	0
T119	3836	0	0	0
T126	0	167	0	0
T127	0	66	0	0
T128	0	70	0	0
T129	21998	0	0	0
T130	3311	0	0	0
T131	42136	0	0	0
T185	0	1	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2373	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	35	0	0
T126	30076	22	0	0
T127	0	8	0	0
T138	8435	0	0	0
T141	0	3	0	0
T142	0	20	0	0
T156	0	64	0	0
T184	0	21	0	0
T186	0	37	0	0
T187	0	8	0	0
T188	0	33	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2378	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	30	0	0
T126	30076	24	0	0
T127	0	14	0	0
T138	8435	0	0	0
T141	0	7	0	0
T142	0	2	0	0
T156	0	69	0	0
T184	0	26	0	0
T186	0	26	0	0
T187	0	28	0	0
T188	0	41	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2400	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	29	0	0
T126	30076	7	0	0
T127	0	7	0	0
T138	8435	0	0	0
T141	0	5	0	0
T142	0	19	0	0
T156	0	83	0	0
T184	0	19	0	0
T186	0	43	0	0
T187	0	9	0	0
T188	0	56	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2292	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	31	0	0
T126	30076	17	0	0
T127	0	13	0	0
T138	8435	0	0	0
T141	0	6	0	0
T142	0	6	0	0
T156	0	82	0	0
T184	0	13	0	0
T186	0	19	0	0
T187	0	6	0	0
T188	0	26	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2262	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	38	0	0
T126	30076	5	0	0
T127	0	16	0	0
T138	8435	0	0	0
T141	0	9	0	0
T142	0	19	0	0
T156	0	70	0	0
T184	0	15	0	0
T186	0	25	0	0
T187	0	15	0	0
T188	0	40	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2317	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	32	0	0
T126	30076	8	0	0
T127	0	24	0	0
T138	8435	0	0	0
T141	0	11	0	0
T142	0	35	0	0
T156	0	88	0	0
T184	0	12	0	0
T186	0	10	0	0
T187	0	22	0	0
T188	0	47	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2467	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	27	0	0
T126	30076	3	0	0
T127	0	7	0	0
T138	8435	0	0	0
T141	0	3	0	0
T142	0	34	0	0
T156	0	85	0	0
T184	0	9	0	0
T186	0	30	0	0
T187	0	21	0	0
T188	0	32	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2367	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	18	0	0
T126	30076	13	0	0
T127	0	12	0	0
T138	8435	0	0	0
T141	0	6	0	0
T142	0	1	0	0
T156	0	58	0	0
T184	0	30	0	0
T186	0	35	0	0
T187	0	13	0	0
T188	0	42	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2935	0	0
T12	47611	0	0	0
T39	5654	0	0	0
T42	95415	16	0	0
T43	0	102	0	0
T67	4922	0	0	0
T74	0	7	0	0
T106	6065	0	0	0
T107	9136	0	0	0
T108	73852	0	0	0
T126	0	24	0	0
T127	0	38	0	0
T186	0	37	0	0
T187	0	8	0	0
T193	0	15	0	0
T194	0	22	0	0
T195	0	18	0	0
T196	13318	0	0	0
T197	16823	0	0	0
T198	91536	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2474	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	49	0	0
T126	30076	18	0	0
T127	0	13	0	0
T138	8435	0	0	0
T141	0	11	0	0
T142	0	10	0	0
T156	0	75	0	0
T184	0	7	0	0
T186	0	35	0	0
T187	0	10	0	0
T188	0	26	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2371	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	45	0	0
T126	30076	13	0	0
T127	0	15	0	0
T138	8435	0	0	0
T156	0	91	0	0
T172	0	40	0	0
T180	0	22	0	0
T184	0	14	0	0
T186	0	26	0	0
T187	0	5	0	0
T188	0	44	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2294	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	28	0	0
T126	30076	10	0	0
T127	0	17	0	0
T138	8435	0	0	0
T141	0	8	0	0
T142	0	10	0	0
T156	0	80	0	0
T184	0	12	0	0
T186	0	29	0	0
T187	0	25	0	0
T188	0	27	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2361	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	31	0	0
T126	30076	23	0	0
T127	0	19	0	0
T138	8435	0	0	0
T141	0	14	0	0
T142	0	5	0	0
T156	0	86	0	0
T172	0	31	0	0
T184	0	22	0	0
T186	0	28	0	0
T188	0	32	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2511	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	23	0	0
T126	30076	14	0	0
T127	0	26	0	0
T138	8435	0	0	0
T141	0	9	0	0
T142	0	6	0	0
T156	0	73	0	0
T184	0	10	0	0
T186	0	15	0	0
T187	0	18	0	0
T188	0	28	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2353	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	39	0	0
T126	30076	28	0	0
T127	0	14	0	0
T138	8435	0	0	0
T141	0	12	0	0
T142	0	6	0	0
T156	0	92	0	0
T184	0	17	0	0
T186	0	20	0	0
T187	0	2	0	0
T188	0	38	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2435	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	29	0	0
T126	30076	19	0	0
T127	0	3	0	0
T138	8435	0	0	0
T141	0	8	0	0
T156	0	105	0	0
T172	0	44	0	0
T184	0	29	0	0
T186	0	28	0	0
T187	0	11	0	0
T188	0	26	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2358	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	37	0	0
T126	30076	10	0	0
T127	0	14	0	0
T138	8435	0	0	0
T141	0	7	0	0
T142	0	23	0	0
T156	0	75	0	0
T184	0	12	0	0
T186	0	25	0	0
T187	0	7	0	0
T188	0	26	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2385	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	24	0	0
T126	30076	18	0	0
T127	0	8	0	0
T138	8435	0	0	0
T141	0	9	0	0
T142	0	40	0	0
T156	0	85	0	0
T184	0	13	0	0
T186	0	27	0	0
T187	0	5	0	0
T188	0	41	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2328	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	46	0	0
T126	30076	4	0	0
T127	0	5	0	0
T138	8435	0	0	0
T141	0	10	0	0
T142	0	30	0	0
T156	0	76	0	0
T184	0	26	0	0
T186	0	14	0	0
T187	0	6	0	0
T188	0	18	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2385	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	23	0	0
T126	30076	18	0	0
T127	0	15	0	0
T138	8435	0	0	0
T141	0	1	0	0
T142	0	17	0	0
T156	0	89	0	0
T184	0	10	0	0
T186	0	32	0	0
T187	0	18	0	0
T188	0	35	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2306	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	48	0	0
T126	30076	26	0	0
T127	0	2	0	0
T138	8435	0	0	0
T141	0	5	0	0
T142	0	21	0	0
T156	0	99	0	0
T184	0	18	0	0
T186	0	25	0	0
T187	0	10	0	0
T188	0	15	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2478	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	30	0	0
T126	30076	7	0	0
T127	0	18	0	0
T138	8435	0	0	0
T141	0	7	0	0
T142	0	30	0	0
T156	0	94	0	0
T184	0	22	0	0
T186	0	39	0	0
T187	0	17	0	0
T188	0	24	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2384	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	31	0	0
T126	30076	38	0	0
T127	0	30	0	0
T138	8435	0	0	0
T141	0	10	0	0
T142	0	14	0	0
T156	0	73	0	0
T184	0	8	0	0
T186	0	27	0	0
T187	0	6	0	0
T188	0	41	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2438	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	32	0	0
T126	30076	24	0	0
T127	0	45	0	0
T138	8435	0	0	0
T141	0	2	0	0
T142	0	20	0	0
T156	0	80	0	0
T184	0	25	0	0
T186	0	31	0	0
T187	0	21	0	0
T188	0	11	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2324	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	32	0	0
T126	30076	9	0	0
T127	0	14	0	0
T138	8435	0	0	0
T141	0	2	0	0
T142	0	17	0	0
T156	0	94	0	0
T184	0	23	0	0
T186	0	28	0	0
T187	0	8	0	0
T188	0	52	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2361	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	30	0	0
T126	30076	28	0	0
T127	0	10	0	0
T138	8435	0	0	0
T141	0	10	0	0
T142	0	14	0	0
T156	0	84	0	0
T184	0	13	0	0
T186	0	29	0	0
T187	0	20	0	0
T188	0	43	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2387	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	18	0	0
T126	30076	11	0	0
T127	0	20	0	0
T138	8435	0	0	0
T141	0	6	0	0
T142	0	11	0	0
T156	0	73	0	0
T184	0	18	0	0
T186	0	27	0	0
T187	0	11	0	0
T188	0	20	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2370	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	24	0	0
T126	30076	11	0	0
T127	0	9	0	0
T138	8435	0	0	0
T141	0	8	0	0
T142	0	18	0	0
T156	0	80	0	0
T184	0	24	0	0
T186	0	25	0	0
T187	0	10	0	0
T188	0	29	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2264	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	31	0	0
T126	30076	8	0	0
T127	0	12	0	0
T138	8435	0	0	0
T141	0	8	0	0
T142	0	1	0	0
T156	0	86	0	0
T184	0	14	0	0
T186	0	20	0	0
T187	0	13	0	0
T188	0	30	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2376	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	34	0	0
T126	30076	17	0	0
T127	0	19	0	0
T138	8435	0	0	0
T141	0	9	0	0
T142	0	27	0	0
T156	0	71	0	0
T172	0	38	0	0
T184	0	16	0	0
T186	0	37	0	0
T188	0	30	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24120970	2360	0	0
T7	10661	0	0	0
T8	286322	0	0	0
T33	27274	0	0	0
T71	24078	0	0	0
T117	0	32	0	0
T126	30076	7	0	0
T127	0	15	0	0
T138	8435	0	0	0
T141	0	7	0	0
T142	0	2	0	0
T156	0	66	0	0
T184	0	31	0	0
T186	0	20	0	0
T187	0	15	0	0
T188	0	29	0	0
T189	2677	0	0	0
T190	7260	0	0	0
T191	11989	0	0	0
T192	7508	0	0	0