Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	19994297	16831	0	0
attest_sw_binding_0_rd_A	19994297	2679	0	0
attest_sw_binding_1_rd_A	19994297	2866	0	0
attest_sw_binding_2_rd_A	19994297	2731	0	0
attest_sw_binding_3_rd_A	19994297	2902	0	0
attest_sw_binding_4_rd_A	19994297	2663	0	0
attest_sw_binding_5_rd_A	19994297	2696	0	0
attest_sw_binding_6_rd_A	19994297	2871	0	0
attest_sw_binding_7_rd_A	19994297	2923	0	0
intr_enable_rd_A	19994297	3582	0	0
key_version_rd_A	19994297	2908	0	0
max_creator_key_ver_regwen_rd_A	19994297	2798	0	0
max_owner_int_key_ver_regwen_rd_A	19994297	2826	0	0
max_owner_key_ver_regwen_rd_A	19994297	2794	0	0
reseed_interval_regwen_rd_A	19994297	2898	0	0
salt_0_rd_A	19994297	2709	0	0
salt_1_rd_A	19994297	2851	0	0
salt_2_rd_A	19994297	2935	0	0
salt_3_rd_A	19994297	2669	0	0
salt_4_rd_A	19994297	2871	0	0
salt_5_rd_A	19994297	2876	0	0
salt_6_rd_A	19994297	2864	0	0
salt_7_rd_A	19994297	2866	0	0
sealing_sw_binding_0_rd_A	19994297	2735	0	0
sealing_sw_binding_1_rd_A	19994297	2790	0	0
sealing_sw_binding_2_rd_A	19994297	2942	0	0
sealing_sw_binding_3_rd_A	19994297	2759	0	0
sealing_sw_binding_4_rd_A	19994297	2785	0	0
sealing_sw_binding_5_rd_A	19994297	2791	0	0
sealing_sw_binding_6_rd_A	19994297	2803	0	0
sealing_sw_binding_7_rd_A	19994297	2752	0	0
sideload_clear_rd_A	19994297	2770	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	16831	0	0
T5	7902	0	0	0
T13	22183	236	0	0
T14	17646	0	0	0
T15	17335	22	0	0
T16	126527	0	0	0
T32	4567	0	0	0
T33	5308	0	0	0
T66	0	379	0	0
T85	4538	0	0	0
T88	0	197	0	0
T102	1451	0	0	0
T107	0	49	0	0
T122	0	1422	0	0
T130	0	1002	0	0
T131	0	691	0	0
T132	0	266	0	0
T133	8591	0	0	0
T134	0	59	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2679	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	6	0	0
T121	0	170	0	0
T132	0	60	0	0
T135	6012	0	0	0
T171	0	20	0	0
T195	0	18	0	0
T196	0	43	0	0
T197	0	45	0	0
T198	0	57	0	0
T199	0	31	0	0
T200	0	3	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2866	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	11	0	0
T121	0	209	0	0
T132	0	49	0	0
T135	6012	0	0	0
T195	0	58	0	0
T196	0	49	0	0
T197	0	16	0	0
T198	0	49	0	0
T199	0	49	0	0
T200	0	9	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0
T205	0	15	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2731	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	6	0	0
T121	0	197	0	0
T132	0	66	0	0
T135	6012	0	0	0
T171	0	26	0	0
T195	0	15	0	0
T196	0	50	0	0
T197	0	30	0	0
T198	0	67	0	0
T199	0	47	0	0
T200	0	3	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2902	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	13	0	0
T121	0	207	0	0
T132	0	51	0	0
T135	6012	0	0	0
T171	0	12	0	0
T195	0	26	0	0
T196	0	31	0	0
T197	0	21	0	0
T198	0	60	0	0
T199	0	54	0	0
T200	0	3	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2663	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	13	0	0
T121	0	186	0	0
T132	0	41	0	0
T135	6012	0	0	0
T171	0	9	0	0
T195	0	34	0	0
T196	0	39	0	0
T197	0	20	0	0
T198	0	51	0	0
T199	0	40	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0
T205	0	20	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2696	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	15	0	0
T121	0	177	0	0
T132	0	65	0	0
T135	6012	0	0	0
T171	0	3	0	0
T195	0	29	0	0
T196	0	22	0	0
T197	0	17	0	0
T198	0	72	0	0
T199	0	42	0	0
T200	0	2	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2871	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	16	0	0
T121	0	195	0	0
T132	0	38	0	0
T135	6012	0	0	0
T171	0	12	0	0
T195	0	19	0	0
T196	0	48	0	0
T197	0	49	0	0
T198	0	48	0	0
T199	0	62	0	0
T200	0	1	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2923	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	19	0	0
T121	0	204	0	0
T132	0	54	0	0
T135	6012	0	0	0
T171	0	12	0	0
T195	0	32	0	0
T196	0	53	0	0
T197	0	20	0	0
T198	0	70	0	0
T199	0	66	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0
T206	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	3582	0	0
T49	290813	66	0	0
T57	42294	0	0	0
T75	0	113	0	0
T107	0	14	0	0
T132	0	102	0	0
T137	3770	0	0	0
T138	53571	0	0	0
T139	3234	0	0	0
T140	1299	0	0	0
T158	40529	0	0	0
T159	18155	0	0	0
T160	4580	0	0	0
T161	82557	0	0	0
T195	0	51	0	0
T207	0	10	0	0
T208	0	1	0	0
T209	0	44	0	0
T210	0	10	0	0
T211	0	52	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2908	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	21	0	0
T121	0	208	0	0
T132	0	85	0	0
T135	6012	0	0	0
T171	0	14	0	0
T195	0	24	0	0
T196	0	46	0	0
T197	0	28	0	0
T198	0	85	0	0
T199	0	70	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0
T205	0	11	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2798	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	2	0	0
T121	0	172	0	0
T132	0	60	0	0
T135	6012	0	0	0
T171	0	7	0	0
T195	0	21	0	0
T196	0	34	0	0
T197	0	29	0	0
T198	0	60	0	0
T199	0	60	0	0
T200	0	6	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2826	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	9	0	0
T121	0	235	0	0
T132	0	64	0	0
T135	6012	0	0	0
T171	0	3	0	0
T195	0	34	0	0
T196	0	39	0	0
T197	0	13	0	0
T198	0	63	0	0
T199	0	59	0	0
T200	0	2	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2794	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	15	0	0
T121	0	197	0	0
T132	0	62	0	0
T135	6012	0	0	0
T171	0	26	0	0
T195	0	35	0	0
T196	0	43	0	0
T197	0	13	0	0
T198	0	44	0	0
T199	0	50	0	0
T200	0	6	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2898	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	21	0	0
T121	0	194	0	0
T132	0	51	0	0
T135	6012	0	0	0
T171	0	13	0	0
T195	0	17	0	0
T196	0	47	0	0
T197	0	20	0	0
T198	0	58	0	0
T199	0	65	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0
T205	0	26	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2709	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	19	0	0
T121	0	200	0	0
T132	0	62	0	0
T135	6012	0	0	0
T171	0	8	0	0
T195	0	10	0	0
T196	0	40	0	0
T197	0	38	0	0
T198	0	51	0	0
T199	0	53	0	0
T200	0	5	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2851	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	26	0	0
T121	0	218	0	0
T132	0	57	0	0
T135	6012	0	0	0
T171	0	3	0	0
T195	0	19	0	0
T196	0	45	0	0
T197	0	37	0	0
T198	0	58	0	0
T199	0	53	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0
T205	0	12	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2935	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	33	0	0
T121	0	182	0	0
T132	0	57	0	0
T135	6012	0	0	0
T171	0	24	0	0
T195	0	33	0	0
T196	0	52	0	0
T197	0	21	0	0
T198	0	72	0	0
T199	0	44	0	0
T200	0	6	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2669	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	5	0	0
T121	0	179	0	0
T132	0	47	0	0
T135	6012	0	0	0
T195	0	27	0	0
T196	0	46	0	0
T197	0	42	0	0
T198	0	40	0	0
T199	0	52	0	0
T200	0	1	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0
T205	0	26	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2871	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	25	0	0
T121	0	217	0	0
T132	0	67	0	0
T135	6012	0	0	0
T171	0	9	0	0
T195	0	29	0	0
T196	0	48	0	0
T197	0	17	0	0
T198	0	50	0	0
T199	0	61	0	0
T200	0	12	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2876	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	15	0	0
T121	0	174	0	0
T132	0	57	0	0
T135	6012	0	0	0
T171	0	8	0	0
T195	0	29	0	0
T196	0	58	0	0
T197	0	27	0	0
T198	0	78	0	0
T199	0	69	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0
T205	0	10	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2864	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	18	0	0
T121	0	207	0	0
T132	0	62	0	0
T135	6012	0	0	0
T171	0	13	0	0
T195	0	9	0	0
T196	0	50	0	0
T197	0	18	0	0
T198	0	55	0	0
T199	0	66	0	0
T200	0	1	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2866	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	22	0	0
T121	0	215	0	0
T132	0	39	0	0
T135	6012	0	0	0
T195	0	32	0	0
T196	0	55	0	0
T197	0	11	0	0
T198	0	52	0	0
T199	0	57	0	0
T200	0	3	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0
T205	0	14	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2735	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	11	0	0
T121	0	199	0	0
T132	0	50	0	0
T135	6012	0	0	0
T171	0	15	0	0
T195	0	38	0	0
T196	0	39	0	0
T197	0	22	0	0
T198	0	68	0	0
T199	0	56	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0
T205	0	27	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2790	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	22	0	0
T121	0	171	0	0
T132	0	56	0	0
T135	6012	0	0	0
T171	0	5	0	0
T195	0	39	0	0
T196	0	31	0	0
T197	0	20	0	0
T198	0	57	0	0
T199	0	53	0	0
T200	0	2	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2942	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	27	0	0
T121	0	198	0	0
T132	0	39	0	0
T135	6012	0	0	0
T171	0	8	0	0
T195	0	49	0	0
T196	0	34	0	0
T197	0	16	0	0
T198	0	82	0	0
T199	0	50	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0
T205	0	25	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2759	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	16	0	0
T121	0	191	0	0
T132	0	40	0	0
T135	6012	0	0	0
T171	0	6	0	0
T195	0	34	0	0
T196	0	45	0	0
T197	0	14	0	0
T198	0	58	0	0
T199	0	58	0	0
T200	0	4	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2785	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	21	0	0
T121	0	170	0	0
T132	0	53	0	0
T135	6012	0	0	0
T171	0	4	0	0
T195	0	19	0	0
T196	0	68	0	0
T197	0	13	0	0
T198	0	59	0	0
T199	0	55	0	0
T200	0	2	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2791	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	13	0	0
T121	0	208	0	0
T132	0	57	0	0
T135	6012	0	0	0
T171	0	17	0	0
T195	0	41	0	0
T196	0	45	0	0
T197	0	17	0	0
T198	0	93	0	0
T199	0	48	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0
T205	0	9	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2803	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	7	0	0
T121	0	198	0	0
T132	0	56	0	0
T135	6012	0	0	0
T171	0	20	0	0
T195	0	44	0	0
T196	0	62	0	0
T197	0	20	0	0
T198	0	64	0	0
T199	0	59	0	0
T200	0	1	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2752	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	11	0	0
T121	0	188	0	0
T132	0	70	0	0
T135	6012	0	0	0
T171	0	8	0	0
T195	0	35	0	0
T196	0	59	0	0
T197	0	22	0	0
T198	0	54	0	0
T199	0	54	0	0
T200	0	1	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19994297	2770	0	0
T8	13363	0	0	0
T19	12463	0	0	0
T42	11973	0	0	0
T101	3675	0	0	0
T107	33047	17	0	0
T121	0	188	0	0
T132	0	47	0	0
T135	6012	0	0	0
T171	0	15	0	0
T195	0	33	0	0
T196	0	83	0	0
T197	0	20	0	0
T198	0	56	0	0
T199	0	48	0	0
T200	0	7	0	0
T201	63780	0	0	0
T202	5486	0	0	0
T203	34071	0	0	0
T204	19366	0	0	0