Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25819495	15590	0	0
attest_sw_binding_0_rd_A	25819495	2968	0	0
attest_sw_binding_1_rd_A	25819495	2946	0	0
attest_sw_binding_2_rd_A	25819495	3090	0	0
attest_sw_binding_3_rd_A	25819495	3196	0	0
attest_sw_binding_4_rd_A	25819495	2969	0	0
attest_sw_binding_5_rd_A	25819495	2986	0	0
attest_sw_binding_6_rd_A	25819495	3044	0	0
attest_sw_binding_7_rd_A	25819495	3035	0	0
intr_enable_rd_A	25819495	3760	0	0
key_version_rd_A	25819495	3169	0	0
max_creator_key_ver_regwen_rd_A	25819495	3192	0	0
max_owner_int_key_ver_regwen_rd_A	25819495	2934	0	0
max_owner_key_ver_regwen_rd_A	25819495	3312	0	0
reseed_interval_regwen_rd_A	25819495	2941	0	0
salt_0_rd_A	25819495	3099	0	0
salt_1_rd_A	25819495	3044	0	0
salt_2_rd_A	25819495	3043	0	0
salt_3_rd_A	25819495	2984	0	0
salt_4_rd_A	25819495	3028	0	0
salt_5_rd_A	25819495	2967	0	0
salt_6_rd_A	25819495	3067	0	0
salt_7_rd_A	25819495	2962	0	0
sealing_sw_binding_0_rd_A	25819495	3084	0	0
sealing_sw_binding_1_rd_A	25819495	3038	0	0
sealing_sw_binding_2_rd_A	25819495	2968	0	0
sealing_sw_binding_3_rd_A	25819495	3100	0	0
sealing_sw_binding_4_rd_A	25819495	2983	0	0
sealing_sw_binding_5_rd_A	25819495	3075	0	0
sealing_sw_binding_6_rd_A	25819495	3178	0	0
sealing_sw_binding_7_rd_A	25819495	3047	0	0
sideload_clear_rd_A	25819495	3064	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	15590	0	0
T5	18553	46	0	0
T42	40050	0	0	0
T43	0	296	0	0
T55	0	220	0	0
T57	12900	287	0	0
T60	0	924	0	0
T70	0	76	0	0
T77	87663	0	0	0
T78	11227	0	0	0
T79	926	0	0	0
T80	1070	0	0	0
T81	993	0	0	0
T82	1158	0	0	0
T83	1850	0	0	0
T117	0	341	0	0
T118	0	371	0	0
T119	0	347	0	0
T120	0	288	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	2968	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	66	0	0
T70	32512	27	0	0
T74	0	38	0	0
T119	0	38	0	0
T128	0	56	0	0
T144	0	18	0	0
T145	0	66	0	0
T168	0	28	0	0
T169	0	9	0	0
T170	0	3	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	2946	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	72	0	0
T70	32512	17	0	0
T74	0	16	0	0
T112	0	63	0	0
T119	0	87	0	0
T128	0	20	0	0
T144	0	23	0	0
T145	0	84	0	0
T168	0	18	0	0
T169	0	6	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	3090	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	70	0	0
T70	32512	36	0	0
T74	0	28	0	0
T112	0	62	0	0
T119	0	51	0	0
T128	0	48	0	0
T144	0	5	0	0
T145	0	57	0	0
T168	0	44	0	0
T169	0	32	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	3196	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	64	0	0
T70	32512	6	0	0
T74	0	35	0	0
T119	0	74	0	0
T128	0	142	0	0
T144	0	25	0	0
T145	0	92	0	0
T168	0	11	0	0
T169	0	23	0	0
T170	0	8	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	2969	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	32	0	0
T70	32512	4	0	0
T74	0	33	0	0
T119	0	64	0	0
T128	0	15	0	0
T144	0	14	0	0
T145	0	68	0	0
T168	0	60	0	0
T169	0	24	0	0
T170	0	17	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	2986	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	44	0	0
T70	32512	13	0	0
T74	0	34	0	0
T119	0	57	0	0
T128	0	30	0	0
T144	0	15	0	0
T145	0	86	0	0
T168	0	58	0	0
T169	0	9	0	0
T170	0	8	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	3044	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	40	0	0
T70	32512	18	0	0
T74	0	37	0	0
T119	0	60	0	0
T128	0	57	0	0
T144	0	24	0	0
T145	0	88	0	0
T168	0	13	0	0
T169	0	11	0	0
T170	0	6	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	3035	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	39	0	0
T70	32512	23	0	0
T74	0	41	0	0
T119	0	53	0	0
T128	0	54	0	0
T144	0	38	0	0
T145	0	84	0	0
T168	0	38	0	0
T169	0	31	0	0
T170	0	7	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	3760	0	0
T7	0	45	0	0
T44	160704	45	0	0
T45	28813	0	0	0
T50	2933	0	0	0
T54	0	22	0	0
T55	0	84	0	0
T56	9805	0	0	0
T57	12900	0	0	0
T61	0	1	0	0
T70	0	12	0	0
T77	87663	0	0	0
T78	11227	0	0	0
T79	926	0	0	0
T80	1070	0	0	0
T119	0	66	0	0
T178	0	64	0	0
T179	0	13	0	0
T180	0	40	0	0
T181	10325	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	3169	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	43	0	0
T70	32512	21	0	0
T74	0	23	0	0
T119	0	51	0	0
T128	0	65	0	0
T144	0	47	0	0
T145	0	82	0	0
T168	0	39	0	0
T169	0	25	0	0
T170	0	2	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	3192	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	77	0	0
T70	32512	20	0	0
T74	0	33	0	0
T119	0	75	0	0
T128	0	59	0	0
T144	0	18	0	0
T145	0	83	0	0
T168	0	26	0	0
T169	0	10	0	0
T170	0	4	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	2934	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	49	0	0
T70	32512	21	0	0
T74	0	12	0	0
T112	0	45	0	0
T119	0	73	0	0
T128	0	55	0	0
T144	0	9	0	0
T145	0	67	0	0
T168	0	34	0	0
T169	0	33	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	3312	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	69	0	0
T70	32512	22	0	0
T74	0	43	0	0
T119	0	89	0	0
T128	0	18	0	0
T144	0	33	0	0
T145	0	72	0	0
T168	0	14	0	0
T169	0	17	0	0
T170	0	4	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	2941	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	37	0	0
T70	32512	10	0	0
T74	0	19	0	0
T119	0	78	0	0
T128	0	6	0	0
T144	0	21	0	0
T145	0	71	0	0
T168	0	35	0	0
T169	0	9	0	0
T170	0	2	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	3099	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	66	0	0
T70	32512	19	0	0
T74	0	32	0	0
T119	0	75	0	0
T128	0	26	0	0
T144	0	23	0	0
T145	0	90	0	0
T168	0	27	0	0
T169	0	14	0	0
T170	0	4	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	3044	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	46	0	0
T70	32512	31	0	0
T74	0	13	0	0
T112	0	57	0	0
T119	0	71	0	0
T128	0	50	0	0
T144	0	27	0	0
T145	0	71	0	0
T168	0	36	0	0
T169	0	19	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	3043	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	24	0	0
T70	32512	18	0	0
T74	0	34	0	0
T112	0	57	0	0
T119	0	75	0	0
T128	0	65	0	0
T144	0	12	0	0
T145	0	93	0	0
T168	0	21	0	0
T169	0	21	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	2984	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	79	0	0
T70	32512	3	0	0
T74	0	33	0	0
T112	0	50	0	0
T119	0	60	0	0
T128	0	45	0	0
T144	0	23	0	0
T145	0	69	0	0
T168	0	54	0	0
T169	0	16	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	3028	0	0
T27	29063	0	0	0
T35	5324	4	0	0
T44	160704	0	0	0
T45	28813	0	0	0
T50	2933	0	0	0
T55	0	56	0	0
T56	9805	0	0	0
T70	0	20	0	0
T74	0	17	0	0
T119	0	59	0	0
T128	0	54	0	0
T144	0	27	0	0
T145	0	96	0	0
T168	0	45	0	0
T169	0	16	0	0
T181	10325	0	0	0
T182	5878	0	0	0
T183	25140	0	0	0
T184	22106	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	2967	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	66	0	0
T70	32512	9	0	0
T74	0	29	0	0
T119	0	72	0	0
T128	0	42	0	0
T144	0	11	0	0
T145	0	82	0	0
T168	0	25	0	0
T169	0	24	0	0
T170	0	3	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	3067	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	47	0	0
T70	32512	21	0	0
T74	0	39	0	0
T112	0	76	0	0
T119	0	56	0	0
T128	0	33	0	0
T144	0	25	0	0
T145	0	67	0	0
T168	0	32	0	0
T169	0	18	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	2962	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	76	0	0
T70	32512	10	0	0
T74	0	16	0	0
T112	0	51	0	0
T119	0	39	0	0
T128	0	52	0	0
T144	0	24	0	0
T145	0	107	0	0
T168	0	18	0	0
T169	0	22	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	3084	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	74	0	0
T70	32512	38	0	0
T74	0	13	0	0
T119	0	47	0	0
T128	0	72	0	0
T144	0	26	0	0
T145	0	69	0	0
T168	0	41	0	0
T169	0	5	0	0
T170	0	3	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	3038	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	77	0	0
T70	32512	32	0	0
T74	0	25	0	0
T119	0	75	0	0
T128	0	33	0	0
T144	0	26	0	0
T145	0	69	0	0
T168	0	26	0	0
T169	0	24	0	0
T170	0	3	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	2968	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	48	0	0
T70	32512	23	0	0
T74	0	27	0	0
T119	0	68	0	0
T128	0	28	0	0
T144	0	39	0	0
T145	0	85	0	0
T168	0	32	0	0
T169	0	9	0	0
T170	0	15	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	3100	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	58	0	0
T70	32512	22	0	0
T74	0	18	0	0
T119	0	65	0	0
T128	0	63	0	0
T144	0	11	0	0
T145	0	80	0	0
T168	0	30	0	0
T169	0	6	0	0
T170	0	9	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	2983	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	40	0	0
T70	32512	9	0	0
T74	0	42	0	0
T119	0	36	0	0
T128	0	39	0	0
T144	0	5	0	0
T145	0	62	0	0
T168	0	33	0	0
T169	0	16	0	0
T170	0	6	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	3075	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	81	0	0
T70	32512	12	0	0
T74	0	25	0	0
T119	0	54	0	0
T128	0	41	0	0
T144	0	32	0	0
T145	0	75	0	0
T168	0	78	0	0
T169	0	19	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0
T185	0	9	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	3178	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	55	0	0
T70	32512	27	0	0
T74	0	42	0	0
T119	0	38	0	0
T128	0	22	0	0
T144	0	10	0	0
T145	0	82	0	0
T168	0	32	0	0
T169	0	12	0	0
T170	0	2	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	3047	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	56	0	0
T70	32512	32	0	0
T74	0	22	0	0
T119	0	57	0	0
T128	0	17	0	0
T144	0	23	0	0
T145	0	80	0	0
T168	0	31	0	0
T169	0	6	0	0
T170	0	5	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819495	3064	0	0
T43	11240	0	0	0
T52	5128	0	0	0
T55	0	50	0	0
T70	32512	3	0	0
T74	0	29	0	0
T119	0	61	0	0
T128	0	69	0	0
T144	0	35	0	0
T145	0	87	0	0
T168	0	39	0	0
T169	0	15	0	0
T170	0	3	0	0
T171	6238	0	0	0
T172	2887	0	0	0
T173	2815	0	0	0
T174	9935	0	0	0
T175	5318	0	0	0
T176	4124	0	0	0
T177	19492	0	0	0