Unified Coverage Report :: Module :: keymgr

Module : keymgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.05	96.00	98.36	99.96		95.92	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	98.05	96.00	98.36	99.96		95.92	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.05	96.00	98.36	99.96		95.92	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.84	99.04	98.07	98.53	100.00	99.02	98.41

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sw_assigns[0].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[0].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[1].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[1].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[2].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[2].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[3].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[3].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[4].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[4].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[5].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[5].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[6].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[6].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[7].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[7].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share1_de	100.00	100.00
keymgr_csr_assert	100.00						100.00
tlul_assert_device	99.30	100.00				100.00	97.90
u_cfgen	98.15	100.00	94.44			100.00
u_checks	100.00	100.00					100.00
u_ctrl	97.16	99.71	95.29	95.19	100.00	98.65	94.12
u_fault_alert	100.00			100.00
u_intr_op_done	100.00	100.00	100.00			100.00	100.00
u_kmac_if	97.35	100.00	90.91	100.00	100.00	93.18	100.00
u_lc_keymgr_en_sync	100.00	100.00				100.00	100.00
u_lfsr	100.00			100.00
u_op_err_alert	100.00			100.00
u_reg	99.47	98.74	99.13	100.00		99.47	100.00
u_reseed_ctrl	98.44	100.00	92.19	100.00		100.00	100.00
u_seed_anchor	0.00	0.00
u_sideload_ctrl	98.87	100.00	94.34		100.00	100.00	100.00
u_sw_binding_regwen	98.25	100.00	94.74			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr

	Line No.	Total	Covered	Percent
TOTAL		75	72	96.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	353	1	1	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	436	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	471	1	0	0.00
CONT_ASSIGN	472	1	0	0.00
CONT_ASSIGN	473	1	0	0.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	485	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	537	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	539	1	1	100.00
CONT_ASSIGN	540	1	1	100.00
CONT_ASSIGN	541	1	1	100.00
CONT_ASSIGN	542	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	670	1	1	100.00
CONT_ASSIGN	671	1	1	100.00
CONT_ASSIGN	672	1	1	100.00
CONT_ASSIGN	674	1	1	100.00
CONT_ASSIGN	675	1	1	100.00
CONT_ASSIGN	676	1	1	100.00
CONT_ASSIGN	677	1	1	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	680	1	1	100.00
CONT_ASSIGN	681	1	1	100.00
CONT_ASSIGN	682	1	1	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	684	1	1	100.00
CONT_ASSIGN	685	1	1	100.00
CONT_ASSIGN	686	1	1	100.00
CONT_ASSIGN	687	1	1	100.00
CONT_ASSIGN	711	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	716	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
ALWAYS	721	5	5	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	779	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
210	1	1
234	1	1
235	1	1
237	1	1
238	1	1
271	2	2
275	1	1
326	1	1
328	1	1
346	1	1
353	1	1
369	1	1
399	1	1
404	1	1
417	1	1
419	1	1
436	1	1
442	1	1
455	1	1
457	1	1
459	1	1
460	1	1
463	1	1
468	1	1
471	0	1
472	0	1
473	0	1
481	1	1
482	1	1
485	1	1
487	1	1
497	1	1
498	1	1
499	1	1
536	1	1
537	1	1
538	1	1
539	1	1
540	1	1
541	1	1
542	1	1
543	1	1
550	1	1
551	1	1
552	1	1
553	1	1
670	1	1
671	1	1
672	1	1
674	1	1
675	1	1
676	1	1
677	1	1
678	1	1
679	1	1
680	1	1
681	1	1
682	1	1
683	1	1
684	1	1
685	1	1
686	1	1
687	1	1
711	1	1
713	1	1
716	1	1
717	1	1
721	1	1
722	1	1
723	1	1
725	1	1
726	1	1
731	1	1
748	1	1
779		unreachable

---

Cond Coverage for Module : keymgr

	Total	Covered	Percent
Conditions	183	180	98.36
Logical	183	180	98.36
Non-Logical	0	0
Event	0	0

 LINE       210
 EXPRESSION (ctrl_lfsr_en | data_lfsr_en | sideload_lfsr_en)
             ------1-----   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	1	0	Covered	T1,T2,T4
1	0	0	Covered	T1,T2,T4

 LINE       336
 EXPRESSION (op_start & op_done)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       353
 EXPRESSION (reg2hw.sw_binding_regwen.qe & ((~reg2hw.sw_binding_regwen.q)))
             -------------1-------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T15
1	1	Covered	T3,T15,T16

 LINE       369
 EXPRESSION (sw_binding_regwen & cfg_regwen)
             --------1--------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       399
 EXPRESSION ((cdi_sel == 1'b0) ? reg2hw.sealing_sw_binding : ((cdi_sel == 1'b1) ? reg2hw.attest_sw_binding : RndCnstCdi))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       399
 SUB-EXPRESSION (cdi_sel == 1'b0)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       399
 SUB-EXPRESSION ((cdi_sel == 1'b1) ? reg2hw.attest_sw_binding : RndCnstCdi)
                 --------1--------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       399
 SUB-EXPRESSION (cdi_sel == 1'b1)
                --------1--------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       442
 EXPRESSION (creator_seed_vld & devid_vld & health_state_vld & rom_digest_vld)
             --------1-------   ----2----   --------3-------   -------4------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T86,T87,T88
1	0	1	1	Covered	T4,T89,T90
1	1	0	1	Covered	T4,T86,T47
1	1	1	0	Covered	T24,T26,T46
1	1	1	1	Covered	T1,T2,T3

 LINE       482
 EXPRESSION ((dest_sel == Aes) ? aes_seed : ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed)))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T15

 LINE       482
 SUB-EXPRESSION (dest_sel == Aes)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T15

 LINE       482
 SUB-EXPRESSION ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       482
 SUB-EXPRESSION (dest_sel == Kmac)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       482
 SUB-EXPRESSION ((dest_sel == Otbn) ? otbn_seed : none_seed)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       482
 SUB-EXPRESSION (dest_sel == Otbn)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       487
 EXPRESSION (invalid_stage_sel ? ({GenLfsrCopies {lfsr[31:0]}}) : ({reg2hw.key_version, reg2hw.salt, dest_seed, output_key}))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       536
 EXPRESSION (adv_en | id_en | gen_en)
             ---1--   --2--   ---3--

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T1,T2,T3

 LINE       537
 EXPRESSION (adv_en & (stage_sel == Creator) & ((~creator_seed_vld)))
             ---1--   -----------2----------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T23,T26,T91
1	0	1	Covered	T91,T92,T88
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T23,T26,T87

 LINE       537
 SUB-EXPRESSION (stage_sel == Creator)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       538
 EXPRESSION (adv_en & (stage_sel == OwnerInt) & ((~owner_seed_vld)))
             ---1--   -----------2-----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T91,T88
1	0	1	Covered	T4,T24,T26
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T4,T88,T93

 LINE       538
 SUB-EXPRESSION (stage_sel == OwnerInt)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       539
 EXPRESSION (adv_en & (stage_sel == Creator) & ((~devid_vld)))
             ---1--   -----------2----------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T24,T26
1	0	1	Covered	T4,T91,T94
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T24,T26,T86

 LINE       539
 SUB-EXPRESSION (stage_sel == Creator)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       540
 EXPRESSION (adv_en & (stage_sel == Creator) & ((~health_state_vld)))
             ---1--   -----------2----------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T23,T24
1	0	1	Covered	T95,T91,T94
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T4,T23,T24

 LINE       540
 SUB-EXPRESSION (stage_sel == Creator)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       541
 EXPRESSION (gen_en & ((~key_version_vld)))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T26,T27

 LINE       542
 EXPRESSION (valid_op & ((~key_vld)))
             ----1---   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T22,T25

 LINE       543
 EXPRESSION (adv_en & (stage_sel == Creator) & ((~rom_digest_vld)))
             ---1--   -----------2----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T23,T24,T26
1	0	1	Covered	T95,T91,T94
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T23,T24,T26

 LINE       543
 SUB-EXPRESSION (stage_sel == Creator)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       550
 EXPRESSION (((~key_vld)) | ((~adv_dvalid[stage_sel])))
             ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T23,T24
1	0	Covered	T1,T2,T3

 LINE       552
 EXPRESSION (((~key_vld)) | ((~key_version_vld)))
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T15
1	0	Covered	T1,T2,T3

 LINE       553
 EXPRESSION (((~key_vld)) | ((~key_version_vld)))
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T15
1	0	Covered	T1,T2,T3

 LINE       623
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(0 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       623
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T36,T20,T61
1	0	Covered	T1,T2,T3

 LINE       623
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(1 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       623
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T36,T20,T61
1	0	Covered	T1,T2,T3

 LINE       623
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(2 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       623
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T36,T20,T61
1	0	Covered	T1,T2,T3

 LINE       623
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(3 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       623
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T36,T20,T61
1	0	Covered	T1,T2,T3

 LINE       623
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(4 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       623
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T36,T20,T61
1	0	Covered	T1,T2,T3

 LINE       623
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(5 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       623
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T36,T20,T61
1	0	Covered	T1,T2,T3

 LINE       623
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(6 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       623
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T36,T20,T61
1	0	Covered	T1,T2,T3

 LINE       623
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(7 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       623
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T36,T20,T61
1	0	Covered	T1,T2,T3

 LINE       630
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(0 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       630
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T36,T20,T61
1	0	Covered	T1,T2,T3

 LINE       630
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(1 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       630
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T36,T20,T61
1	0	Covered	T1,T2,T3

 LINE       630
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(2 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       630
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T36,T20,T61
1	0	Covered	T1,T2,T3

 LINE       630
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(3 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       630
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T36,T20,T61
1	0	Covered	T1,T2,T3

 LINE       630
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(4 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       630
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T36,T20,T61
1	0	Covered	T1,T2,T3

 LINE       630
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(5 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       630
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T36,T20,T61
1	0	Covered	T1,T2,T3

 LINE       630
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(6 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       630
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T36,T20,T61
1	0	Covered	T1,T2,T3

 LINE       630
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(7 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       630
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T36,T20,T61
1	0	Covered	T1,T2,T3

 LINE       713
 EXPRESSION (fault_errs ? 1'b1 : (fault_err_ack ? 1'b0 : fault_err_req_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T23,T24,T36

 LINE       713
 SUB-EXPRESSION (fault_err_ack ? 1'b0 : fault_err_req_q)
                 ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       717
 EXPRESSION (op_errs ? 1'b1 : (op_err_ack ? 1'b0 : op_err_req_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       717
 SUB-EXPRESSION (op_err_ack ? 1'b0 : op_err_req_q)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       731
 EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T96,T79,T80
1	0	Covered	T1,T2,T3
1	1	Covered	T96,T79,T80

 LINE       748
 EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
             -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T96,T79,T80
1	0	Covered	T1,T2,T3
1	1	Covered	T96,T79,T80

---

Toggle Coverage for Module : keymgr

	Total	Covered	Percent
Totals	67	65	97.01
Total Bits	10068	10064	99.96
Total Bits 0->1	5034	5032	99.96
Total Bits 1->0	5034	5032	99.96

Ports	67	65	97.01
Port Bits	10068	10064	99.96
Port Bits 0->1	5034	5032	99.96
Port Bits 1->0	5034	5032	99.96

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T23,T24,T36	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T23,T24,T36	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T23,T24,T36	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T15,T23,T24	Yes	T15,T23,T24	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T35,T45,T57	Yes	T35,T45,T57	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T4,T15,T16	Yes	T4,T14,T15	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1:0][255:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.valid	Yes	Yes	T4,T15,T16	Yes	T3,T4,T15	OUTPUT
kmac_key_o.key[1:0][255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_key_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[0][6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][8:7]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][10:9]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][11]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][15:12]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][16]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][17]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][18]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][21:19]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][22]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][23]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][24]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][29:25]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][30]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][32:31]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][33]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][38:34]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][39]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][41:40]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][42]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][44:43]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][45]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][49:46]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][51:50]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][52]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][53]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][64:54]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][65]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][66]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][68:67]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][69]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][70]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][77:71]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][78]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][80:79]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][81]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][83:82]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][84]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][85]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][87:86]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][93:88]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][94]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][98:95]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][99]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][100]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][101]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][104:102]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][105]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][106]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][107]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][110:108]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][112:111]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][120:113]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][122:121]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][129:123]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][130]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][131]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][132]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][143:133]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][144]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][145]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][146]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][152:147]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][153]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][156:154]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][157]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][158]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][159]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][163:160]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][164]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][167:165]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][168]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][178:169]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][179]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][181:180]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][182]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][183]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][184]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][192:185]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][193]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][195:194]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][196]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][198:197]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][199]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][208:200]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][210:209]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][215:211]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][217:216]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][220:218]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][221]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][231:222]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][232]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][242:233]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][243]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][261:244]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][262]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][263]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][265:264]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][269:266]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][270]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][271]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][272]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][276:273]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][277]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][278]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][279]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][280]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][281]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][299:282]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][300]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][304:301]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][305]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][308:306]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][309]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][312:310]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][313]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][315:314]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][316]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][318:317]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][319]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][320]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][321]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][324:322]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][326:325]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][332:327]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][333]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][338:334]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][339]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][344:340]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][345]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][346]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][347]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][348]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][349]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][352:350]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][353]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][356:354]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][357]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][358]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][359]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][370:360]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][371]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][382:372]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][383]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][1]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][3:2]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][5:4]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][11:6]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][12]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][22:13]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][23]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][27:24]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][28]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][29]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][30]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][34:31]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][35]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][40:36]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][41]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][46:42]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][47]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][54:48]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][55]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][60:56]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][61]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][62]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][64:63]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][75:65]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][76]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][81:77]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][82]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][86:83]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][87]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][92:88]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][93]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][94]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][95]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][97:96]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][98]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][104:99]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][105]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][106]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][107]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][110:108]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][111]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][114:112]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][115]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][118:116]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][119]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][123:120]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][124]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][140:125]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][141]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][144:142]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][145]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][161:146]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][162]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][168:163]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][169]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][170]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][171]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][175:172]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][176]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][180:177]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][181]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][184:182]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][185]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][188:186]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][189]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][198:190]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][200:199]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][201]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][202]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][205:203]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][206]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][208:207]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][209]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][210]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][211]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][215:212]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][216]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][225:217]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][226]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][231:227]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][232]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][235:233]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][236]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][237]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][241:238]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][247:242]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][248]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][253:249]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][254]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][258:255]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][259]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][260]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][262:261]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][272:263]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][274:273]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][275]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][276]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][282:277]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][283]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][291:284]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][293:292]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][294]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][295]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][297:296]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][298]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][301:299]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][302]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][303]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][304]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][312:305]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][314:313]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][315]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][316]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][321:317]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][323:322]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][325:324]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][326]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][327]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][328]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][332:329]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][333]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][336:334]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][337]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][338]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][339]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][342:340]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][343]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][345:344]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][346]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][351:347]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][355:352]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][356]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][358:357]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][367:359]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][368]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][377:369]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][379:378]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][381:380]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][382]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][383]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.valid	Yes	Yes	T15,T18,T97	Yes	T15,T18,T19	OUTPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_i.error	Yes	Yes	T23,T24,T33	Yes	T35,T45,T61	INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T2,T3,T14	Yes	T1,T2,T3	INPUT
kmac_en_masking_i	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_en_i[3:0]	Yes	Yes	T16,T24,T37	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[127:0]	Yes	Yes	T4,T15,T16	Yes	T3,T4,T15	INPUT
otp_key_i.owner_seed_valid	Yes	Yes	T44,T98,T99	Yes	T23,T24,T44	INPUT
otp_key_i.owner_seed[255:0]	Yes	Yes	T44,T57,T46	Yes	T57,T99,T60	INPUT
otp_key_i.creator_seed_valid	Yes	Yes	T44,T99,T60	Yes	T44,T20,T46	INPUT
otp_key_i.creator_seed[255:0]	Yes	Yes	T44,T57,T42	Yes	T23,T44,T57	INPUT
otp_key_i.creator_root_key_share1_valid	No	No		No		INPUT
otp_key_i.creator_root_key_share1[255:0]	Yes	Yes	T23,T44,T98	Yes	T44,T20,T46	INPUT
otp_key_i.creator_root_key_share0_valid	No	No		No		INPUT
otp_key_i.creator_root_key_share0[255:0]	Yes	Yes	T24,T44,T57	Yes	T23,T44,T57	INPUT
otp_device_id_i[255:0]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][0]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][9:1]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][10]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[0][11]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][13:12]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][14]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][15]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][16]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[0][17]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][19:18]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][20]	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	INPUT
flash_i.seeds[0][21]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][22]	Yes	Yes	T3,T4,T18	Yes	T3,T4,T18	INPUT
flash_i.seeds[0][23]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][24]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][28:25]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][29]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][30]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][31]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][32]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][33]	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	INPUT
flash_i.seeds[0][35:34]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][36]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][37]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[0][38]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][40:39]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][41]	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	INPUT
flash_i.seeds[0][42]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][43]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][45:44]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][46]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][48:47]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][50:49]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][53:51]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][55:54]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][57:56]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][58]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][59]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][60]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[0][64:61]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][65]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[0][66]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][68:67]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][69]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][70]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][71]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[0][72]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][73]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][75:74]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][76]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[0][77]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][79:78]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][83:80]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][84]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][85]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][86]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][87]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][88]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[0][93:89]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][95:94]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][96]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][97]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][98]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][99]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][100]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][101]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][102]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][103]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][104]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][105]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[0][107:106]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][108]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][114:109]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][115]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][116]	Yes	Yes	T3,T15,T16	Yes	T3,T15,T16	INPUT
flash_i.seeds[0][122:117]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][123]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][125:124]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][126]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][127]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][129:128]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][130]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][132:131]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[0][133]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][134]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][135]	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	INPUT
flash_i.seeds[0][136]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][140:137]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][141]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][142]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][143]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][144]	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	INPUT
flash_i.seeds[0][145]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][146]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][147]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][148]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][149]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[0][150]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][151]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[0][153:152]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][155:154]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][156]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][158:157]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][159]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][160]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][161]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][162]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][164:163]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][165]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][166]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][167]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[0][168]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][169]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[0][170]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][172:171]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][173]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][174]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[0][175]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][176]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][177]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][180:178]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][181]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[0][184:182]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][185]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][186]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][188:187]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][190:189]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][191]	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	INPUT
flash_i.seeds[0][195:192]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][196]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][197]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][199:198]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][201:200]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][202]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][204:203]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][207:205]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][208]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][209]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][210]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[0][211]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][213:212]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][214]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][217:215]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][218]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][219]	Yes	Yes	T3,T15,T16	Yes	T3,T15,T16	INPUT
flash_i.seeds[0][221:220]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][223:222]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][224]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][225]	Yes	Yes	T4,T15,T23	Yes	T4,T15,T23	INPUT
flash_i.seeds[0][226]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][231:227]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][232]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[0][233]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][234]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[0][235]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][236]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][238:237]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][239]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][245:240]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][246]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[0][247]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[0][249:248]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][250]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[0][255:251]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][0]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][2:1]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][3]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][5:4]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][6]	Yes	Yes	T3,T15,T16	Yes	T3,T15,T16	INPUT
flash_i.seeds[1][8:7]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][9]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][11:10]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][12]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][13]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][14]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][17:15]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][19:18]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][20]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][21]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][25:22]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][26]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][27]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][28]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][29]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][35:30]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][37:36]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][38]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][39]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][40]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][41]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][42]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][43]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][44]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][46:45]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][47]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][55:48]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][57:56]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][59:58]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][60]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][64:61]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][65]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][66]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][67]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][70:68]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][71]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][72]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][73]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][74]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][76:75]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][77]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][85:78]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][86]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][87]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][88]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][89]	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	INPUT
flash_i.seeds[1][90]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][91]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][92]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][93]	Yes	Yes	T3,T15,T16	Yes	T3,T15,T16	INPUT
flash_i.seeds[1][94]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][95]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][98:96]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][99]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][100]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][102:101]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][107:103]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][110:108]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][111]	Yes	Yes	T4,T15,T23	Yes	T4,T15,T23	INPUT
flash_i.seeds[1][114:112]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][115]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][116]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][118:117]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][119]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][126:120]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][127]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][128]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][129]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][131:130]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][132]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][137:133]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][138]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][141:139]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][142]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][143]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][145:144]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][147:146]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][148]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][149]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][150]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][152:151]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][153]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][154]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][155]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][159:156]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][161:160]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][162]	Yes	Yes	T15,T16,T23	Yes	T15,T16,T23	INPUT
flash_i.seeds[1][163]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][164]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][165]	Yes	Yes	T3,T15,T16	Yes	T3,T15,T16	INPUT
flash_i.seeds[1][166]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][167]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][168]	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	INPUT
flash_i.seeds[1][173:169]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][175:174]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][176]	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	INPUT
flash_i.seeds[1][177]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][178]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][179]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][182:180]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][183]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][184]	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	INPUT
flash_i.seeds[1][185]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][193:186]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][194]	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	INPUT
flash_i.seeds[1][195]	Yes	Yes	T3,T15,T16	Yes	T3,T15,T16	INPUT
flash_i.seeds[1][196]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][197]	Yes	Yes	T3,T15,T16	Yes	T3,T15,T16	INPUT
flash_i.seeds[1][198]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][199]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][201:200]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][202]	Yes	Yes	T3,T15,T16	Yes	T3,T15,T16	INPUT
flash_i.seeds[1][203]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][213:204]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][214]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][215]	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	INPUT
flash_i.seeds[1][216]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][217]	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	INPUT
flash_i.seeds[1][225:218]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][226]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][227]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][230:228]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][231]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][232]	Yes	Yes	T3,T15,T16	Yes	T3,T15,T16	INPUT
flash_i.seeds[1][238:233]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][239]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][240]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][241]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][242]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
flash_i.seeds[1][243]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][247:244]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][248]	Yes	Yes	T3,T15,T16	Yes	T3,T15,T16	INPUT
flash_i.seeds[1][250:249]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][251]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][252]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][253]	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	INPUT
flash_i.seeds[1][254]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
flash_i.seeds[1][255]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i.edn_fips	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_digest_i.valid	Yes	Yes	T24,T26,T86	Yes	T24,T26,T86	INPUT
rom_digest_i.data[255:0]	Yes	Yes	T4,T15,T16	Yes	T4,T15,T16	INPUT
intr_op_done_o	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T23,T24,T36	Yes	T23,T24,T36	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T23,T24,T36	Yes	T23,T24,T36	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : keymgr

	Line No.	Total	Covered	Percent
Branches		49	47	95.92
TERNARY	399	3	2	66.67
TERNARY	482	4	4	100.00
TERNARY	487	2	2	100.00
TERNARY	713	3	2	66.67
TERNARY	717	3	3	100.00
TERNARY	623	2	2	100.00
TERNARY	630	2	2	100.00
TERNARY	623	2	2	100.00
TERNARY	630	2	2	100.00
TERNARY	623	2	2	100.00
TERNARY	630	2	2	100.00
TERNARY	623	2	2	100.00
TERNARY	630	2	2	100.00
TERNARY	623	2	2	100.00
TERNARY	630	2	2	100.00
TERNARY	623	2	2	100.00
TERNARY	630	2	2	100.00
TERNARY	623	2	2	100.00
TERNARY	630	2	2	100.00
TERNARY	623	2	2	100.00
TERNARY	630	2	2	100.00
IF	721	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	399	((cdi_sel == 1'b0)) ? 
-2-:	399	((cdi_sel == 1'b1)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	482	((dest_sel == Aes)) ? 
-2-:	482	((dest_sel == Kmac)) ? 
-3-:	482	((dest_sel == Otbn)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T3,T4,T15
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	487	(invalid_stage_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	713	(fault_errs) ? 
-2-:	713	(fault_err_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T23,T24,T36
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	717	(op_errs) ? 
-2-:	717	(op_err_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	623	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	630	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	623	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	630	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	623	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	630	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	623	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	630	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	623	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	630	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	623	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	630	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	623	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	630	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	623	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	630	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	721	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keymgr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AdvDataWidth_A	874	874	0	0
AesKeyKnownO_A	24088224	23919370	0	0
AlertKnownO_A	24088224	23919370	0	0
ErrCntMatch_A	874	874	0	0
FaultCntMatch_A	874	874	0	0
FpvSecCmCtrlCntAlertCheck_A	24088224	80	0	0
FpvSecCmCtrlDataFsmCheck_A	24088224	80	0	0
FpvSecCmCtrlMainFsmCheck_A	24088224	80	0	0
FpvSecCmCtrlOpFsmCheck_A	24088224	80	0	0
FpvSecCmKmacIfCntAlertCheck_A	24088224	80	0	0
FpvSecCmKmacIfFsmCheck_A	24088224	80	0	0
FpvSecCmRegWeOnehotCheck_A	24088224	80	0	0
FpvSecCmReseedCtrlCntAlertCheck_A	24088224	80	0	0
FpvSecCmSideloadCtrlFsmCheck_A	24088224	80	0	0
GenDataWidth_A	874	874	0	0
IdDataWidth_A	874	874	0	0
IntrKnownO_A	24088224	23919370	0	0
KmacDataKnownO_A	23602289	23454870	0	0
KmacKeyKnownO_A	24088224	23919370	0	0
KmacMaskCheck_A	874	874	0	0
LfsrWidth_A	874	874	0	0
OtbnKeyKnownO_A	24088224	23919370	0	0
OutputKeyDiff_A	874	874	0	0
StageMatch_A	874	874	0	0
TlAReadyKnownO_A	24088224	23919370	0	0
TlDValidKnownO_A	24088224	23919370	0	0

AdvDataWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

AesKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24088224	23919370	0	0
T1	2045	1960	0	0
T2	30733	30683	0	0
T3	16875	16809	0	0
T4	11450	11371	0	0
T14	10284	10199	0	0
T15	4622	4522	0	0
T16	7084	7014	0	0
T17	15339	15261	0	0
T18	79563	79498	0	0
T19	1619	1557	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24088224	23919370	0	0
T1	2045	1960	0	0
T2	30733	30683	0	0
T3	16875	16809	0	0
T4	11450	11371	0	0
T14	10284	10199	0	0
T15	4622	4522	0	0
T16	7084	7014	0	0
T17	15339	15261	0	0
T18	79563	79498	0	0
T19	1619	1557	0	0

ErrCntMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

FaultCntMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

FpvSecCmCtrlCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24088224	80	0	0
T11	50284	20	0	0
T12	0	10	0	0
T13	0	20	0	0
T40	0	20	0	0
T41	0	10	0	0
T75	7817	0	0	0
T100	4908	0	0	0
T101	60232	0	0	0
T102	7707	0	0	0
T103	20265	0	0	0
T104	23040	0	0	0
T105	18041	0	0	0
T106	11094	0	0	0
T107	3723	0	0	0

FpvSecCmCtrlDataFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24088224	80	0	0
T11	50284	20	0	0
T12	0	10	0	0
T13	0	20	0	0
T40	0	20	0	0
T41	0	10	0	0
T75	7817	0	0	0
T100	4908	0	0	0
T101	60232	0	0	0
T102	7707	0	0	0
T103	20265	0	0	0
T104	23040	0	0	0
T105	18041	0	0	0
T106	11094	0	0	0
T107	3723	0	0	0

FpvSecCmCtrlMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24088224	80	0	0
T11	50284	20	0	0
T12	0	10	0	0
T13	0	20	0	0
T40	0	20	0	0
T41	0	10	0	0
T75	7817	0	0	0
T100	4908	0	0	0
T101	60232	0	0	0
T102	7707	0	0	0
T103	20265	0	0	0
T104	23040	0	0	0
T105	18041	0	0	0
T106	11094	0	0	0
T107	3723	0	0	0

FpvSecCmCtrlOpFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24088224	80	0	0
T11	50284	20	0	0
T12	0	10	0	0
T13	0	20	0	0
T40	0	20	0	0
T41	0	10	0	0
T75	7817	0	0	0
T100	4908	0	0	0
T101	60232	0	0	0
T102	7707	0	0	0
T103	20265	0	0	0
T104	23040	0	0	0
T105	18041	0	0	0
T106	11094	0	0	0
T107	3723	0	0	0

FpvSecCmKmacIfCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24088224	80	0	0
T11	50284	20	0	0
T12	0	10	0	0
T13	0	20	0	0
T40	0	20	0	0
T41	0	10	0	0
T75	7817	0	0	0
T100	4908	0	0	0
T101	60232	0	0	0
T102	7707	0	0	0
T103	20265	0	0	0
T104	23040	0	0	0
T105	18041	0	0	0
T106	11094	0	0	0
T107	3723	0	0	0

FpvSecCmKmacIfFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24088224	80	0	0
T11	50284	20	0	0
T12	0	10	0	0
T13	0	20	0	0
T40	0	20	0	0
T41	0	10	0	0
T75	7817	0	0	0
T100	4908	0	0	0
T101	60232	0	0	0
T102	7707	0	0	0
T103	20265	0	0	0
T104	23040	0	0	0
T105	18041	0	0	0
T106	11094	0	0	0
T107	3723	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24088224	80	0	0
T11	50284	20	0	0
T12	0	10	0	0
T13	0	20	0	0
T40	0	20	0	0
T41	0	10	0	0
T75	7817	0	0	0
T100	4908	0	0	0
T101	60232	0	0	0
T102	7707	0	0	0
T103	20265	0	0	0
T104	23040	0	0	0
T105	18041	0	0	0
T106	11094	0	0	0
T107	3723	0	0	0

FpvSecCmReseedCtrlCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24088224	80	0	0
T11	50284	20	0	0
T12	0	10	0	0
T13	0	20	0	0
T40	0	20	0	0
T41	0	10	0	0
T75	7817	0	0	0
T100	4908	0	0	0
T101	60232	0	0	0
T102	7707	0	0	0
T103	20265	0	0	0
T104	23040	0	0	0
T105	18041	0	0	0
T106	11094	0	0	0
T107	3723	0	0	0

FpvSecCmSideloadCtrlFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24088224	80	0	0
T11	50284	20	0	0
T12	0	10	0	0
T13	0	20	0	0
T40	0	20	0	0
T41	0	10	0	0
T75	7817	0	0	0
T100	4908	0	0	0
T101	60232	0	0	0
T102	7707	0	0	0
T103	20265	0	0	0
T104	23040	0	0	0
T105	18041	0	0	0
T106	11094	0	0	0
T107	3723	0	0	0

GenDataWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

IdDataWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

IntrKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24088224	23919370	0	0
T1	2045	1960	0	0
T2	30733	30683	0	0
T3	16875	16809	0	0
T4	11450	11371	0	0
T14	10284	10199	0	0
T15	4622	4522	0	0
T16	7084	7014	0	0
T17	15339	15261	0	0
T18	79563	79498	0	0
T19	1619	1557	0	0

KmacDataKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23602289	23454870	0	0
T1	2045	1960	0	0
T2	30733	30683	0	0
T3	16875	16809	0	0
T4	11450	11371	0	0
T14	10284	10199	0	0
T15	4622	4522	0	0
T16	7084	7014	0	0
T17	15339	15261	0	0
T18	79563	79498	0	0
T19	1619	1557	0	0

KmacKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24088224	23919370	0	0
T1	2045	1960	0	0
T2	30733	30683	0	0
T3	16875	16809	0	0
T4	11450	11371	0	0
T14	10284	10199	0	0
T15	4622	4522	0	0
T16	7084	7014	0	0
T17	15339	15261	0	0
T18	79563	79498	0	0
T19	1619	1557	0	0

KmacMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

LfsrWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OtbnKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24088224	23919370	0	0
T1	2045	1960	0	0
T2	30733	30683	0	0
T3	16875	16809	0	0
T4	11450	11371	0	0
T14	10284	10199	0	0
T15	4622	4522	0	0
T16	7084	7014	0	0
T17	15339	15261	0	0
T18	79563	79498	0	0
T19	1619	1557	0	0

OutputKeyDiff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

StageMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24088224	23919370	0	0
T1	2045	1960	0	0
T2	30733	30683	0	0
T3	16875	16809	0	0
T4	11450	11371	0	0
T14	10284	10199	0	0
T15	4622	4522	0	0
T16	7084	7014	0	0
T17	15339	15261	0	0
T18	79563	79498	0	0
T19	1619	1557	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24088224	23919370	0	0
T1	2045	1960	0	0
T2	30733	30683	0	0
T3	16875	16809	0	0
T4	11450	11371	0	0
T14	10284	10199	0	0
T15	4622	4522	0	0
T16	7084	7014	0	0
T17	15339	15261	0	0
T18	79563	79498	0	0
T19	1619	1557	0	0