Unified Coverage Report :: Module :: keymgr

Module : keymgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.05	96.00	98.36	99.96		95.92	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	98.05	96.00	98.36	99.96		95.92	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.05	96.00	98.36	99.96		95.92	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.00	99.04	98.11	99.20	100.00	99.02	98.63

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sw_assigns[0].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[0].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[1].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[1].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[2].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[2].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[3].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[3].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[4].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[4].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[5].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[5].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[6].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[6].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[7].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[7].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share1_de	100.00	100.00
keymgr_csr_assert	100.00						100.00
tlul_assert_device	99.30	100.00				100.00	97.90
u_cfgen	98.15	100.00	94.44			100.00
u_checks	100.00	100.00					100.00
u_ctrl	98.51	99.71	95.29	97.40	100.00	98.65	100.00
u_fault_alert	100.00			100.00
u_intr_op_done	100.00	100.00	100.00			100.00	100.00
u_kmac_if	97.35	100.00	90.91	100.00	100.00	93.18	100.00
u_lc_keymgr_en_sync	100.00	100.00				100.00	100.00
u_lfsr	100.00			100.00
u_op_err_alert	100.00			100.00
u_reg	99.48	98.74	99.18	100.00		99.47	100.00
u_reseed_ctrl	98.44	100.00	92.19	100.00		100.00	100.00
u_seed_anchor	0.00	0.00
u_sideload_ctrl	98.87	100.00	94.34		100.00	100.00	100.00
u_sw_binding_regwen	98.25	100.00	94.74			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr

	Line No.	Total	Covered	Percent
TOTAL		75	72	96.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	353	1	1	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	436	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	471	1	0	0.00
CONT_ASSIGN	472	1	0	0.00
CONT_ASSIGN	473	1	0	0.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	485	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	537	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	539	1	1	100.00
CONT_ASSIGN	540	1	1	100.00
CONT_ASSIGN	541	1	1	100.00
CONT_ASSIGN	542	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	670	1	1	100.00
CONT_ASSIGN	671	1	1	100.00
CONT_ASSIGN	672	1	1	100.00
CONT_ASSIGN	674	1	1	100.00
CONT_ASSIGN	675	1	1	100.00
CONT_ASSIGN	676	1	1	100.00
CONT_ASSIGN	677	1	1	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	680	1	1	100.00
CONT_ASSIGN	681	1	1	100.00
CONT_ASSIGN	682	1	1	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	684	1	1	100.00
CONT_ASSIGN	685	1	1	100.00
CONT_ASSIGN	686	1	1	100.00
CONT_ASSIGN	687	1	1	100.00
CONT_ASSIGN	711	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	716	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
ALWAYS	721	5	5	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	779	0	0

209                       logic ctrl_lfsr_en, data_lfsr_en, sideload_lfsr_en;
210        1/1            assign lfsr_en = ctrl_lfsr_en | data_lfsr_en | sideload_lfsr_en;
           Tests:       T1 T2 T3 
211                     
212                       prim_lfsr #(
213                         .LfsrDw(LfsrWidth),
214                         .StateOutDw(LfsrWidth),
215                         .DefaultSeed(RndCnstLfsrSeed),
216                         .StatePermEn(1'b1),
217                         .StatePerm(RndCnstLfsrPerm),
218                         .NonLinearOut(1'b1)
219                       ) u_lfsr (
220                         .clk_i,
221                         .rst_ni,
222                         .lfsr_en_i(lfsr_en),
223                         .seed_en_i(seed_en),
224                         .seed_i(seed),
225                         .entropy_i('0),
226                         .state_o(lfsr)
227                       );
228                       `ASSERT_INIT(LfsrWidth_A, LfsrWidth == 64)
229                     
230                     
231                       logic [Shares-1:0][RandWidth-1:0] ctrl_rand;
232                       logic [Shares-1:0][RandWidth-1:0] data_rand;
233                     
234        1/1            assign ctrl_rand[0] = lfsr[63:32];
           Tests:       T1 T2 T3 
235        1/1            assign ctrl_rand[1] = perm_data(lfsr[31:0], RndCnstRandPerm);
           Tests:       T1 T2 T3 
236                     
237        1/1            assign data_rand[0] = lfsr[31:0];
           Tests:       T1 T2 T3 
238        1/1            assign data_rand[1] = perm_data(lfsr[63:32], RndCnstRandPerm);
           Tests:       T1 T2 T3 
239                     
240                       /////////////////////////////////////
241                       //  Key Manager Control
242                       /////////////////////////////////////
243                     
244                       keymgr_stage_e stage_sel;
245                       logic invalid_stage_sel;
246                       prim_mubi_pkg::mubi4_t hw_key_sel;
247                       logic adv_en, id_en, gen_en;
248                       logic wipe_key;
249                       hw_key_req_t kmac_key;
250                       logic op_done;
251                       logic init;
252                       logic data_valid;
253                       logic data_hw_en;
254                       logic data_sw_en;
255                       logic kmac_done;
256                       logic kmac_input_invalid;
257                       logic kmac_cmd_err;
258                       logic kmac_fsm_err;
259                       logic kmac_op_err;
260                       logic kmac_done_err;
261                       logic [Shares-1:0][kmac_pkg::AppDigestW-1:0] kmac_data;
262                       logic [Shares-1:0][KeyWidth-1:0] kmac_data_truncated;
263                       logic [ErrLastPos-1:0] err_code;
264                       logic [FaultLastPos-1:0] fault_code;
265                       logic sw_binding_unlock;
266                       logic [CdiWidth-1:0] cdi_sel;
267                       logic sideload_fsm_err;
268                       logic sideload_sel_err;
269                     
270                       for (genvar i = 0; i < Shares; i++) begin : gen_truncate_data
271        2/2              assign kmac_data_truncated[i] = kmac_data[i][KeyWidth-1:0];
           Tests:       T1 T2 T3  | T1 T2 T3 
272                       end
273                     
274                       logic op_start;
275        1/1            assign op_start = reg2hw.start.q;
           Tests:       T1 T2 T3 
276                       keymgr_ctrl #(
277                         .KmacEnMasking(KmacEnMasking)
278                       ) u_ctrl (
279                         .clk_i,
280                         .rst_ni,
281                         .en_i(lc_tx_test_true_strict(lc_keymgr_en[KeyMgrEnCtrl])),
282                         .regfile_intg_err_i(regfile_intg_err),
283                         .shadowed_update_err_i(shadowed_update_err),
284                         .shadowed_storage_err_i(shadowed_storage_err),
285                         .reseed_cnt_err_i(reseed_cnt_err),
286                         .sideload_sel_err_i(sideload_sel_err),
287                         .sideload_fsm_err_i(sideload_fsm_err),
288                         .prng_reseed_req_o(reseed_req),
289                         .prng_reseed_ack_i(reseed_ack),
290                         .prng_reseed_done_i(reseed_done),
291                         .prng_en_o(ctrl_lfsr_en),
292                         .entropy_i(ctrl_rand),
293                         .op_i(keymgr_ops_e'(reg2hw.control_shadowed.operation.q)),
294                         .op_start_i(op_start),
295                         .op_cdi_sel_i(reg2hw.control_shadowed.cdi_sel.q),
296                         .op_done_o(op_done),
297                         .init_o(init),
298                         .sw_binding_unlock_o(sw_binding_unlock),
299                         .status_o(hw2reg.op_status.d),
300                         .fault_o(fault_code),
301                         .error_o(err_code),
302                         .data_hw_en_o(data_hw_en),
303                         .data_sw_en_o(data_sw_en),
304                         .data_valid_o(data_valid),
305                         .working_state_o(hw2reg.working_state.d),
306                         .root_key_i(otp_key_i),
307                         .hw_sel_o(hw_key_sel),
308                         .stage_sel_o(stage_sel),
309                         .invalid_stage_sel_o(invalid_stage_sel),
310                         .cdi_sel_o(cdi_sel),
311                         .wipe_key_o(wipe_key),
312                         .adv_en_o(adv_en),
313                         .id_en_o(id_en),
314                         .gen_en_o(gen_en),
315                         .key_o(kmac_key),
316                         .kmac_done_i(kmac_done),
317                         .kmac_input_invalid_i(kmac_input_invalid),
318                         .kmac_fsm_err_i(kmac_fsm_err),
319                         .kmac_op_err_i(kmac_op_err),
320                         .kmac_done_err_i(kmac_done_err),
321                         .kmac_cmd_err_i(kmac_cmd_err),
322                         .kmac_data_i(kmac_data_truncated)
323                       );
324                     
325                       assign hw2reg.start.d  = '0;
326        1/1            assign hw2reg.start.de = op_done;
           Tests:       T1 T2 T3 
327                       // as long as operation is ongoing, capture status
328        1/1            assign hw2reg.op_status.de = op_start;
           Tests:       T1 T2 T3 
329                     
330                       // working state is always visible
331                       assign hw2reg.working_state.de = 1'b1;
332                     
333                       logic cfg_regwen;
334                     
335                       // key manager registers cannot be changed once an operation starts
336                       keymgr_cfg_en u_cfgen (
337                         .clk_i,
338                         .rst_ni,
339                         .init_i(1'b1), // cfg_regwen does not care about init
340                         .en_i(lc_tx_test_true_strict(lc_keymgr_en[KeyMgrEnCfgEn])),
341                         .set_i(op_start & op_done),
342                         .clr_i(op_start),
343                         .out_o(cfg_regwen)
344                       );
345                     
346        1/1            assign hw2reg.cfg_regwen.d = cfg_regwen;
           Tests:       T1 T2 T3 
347                     
348                     
349                       logic sw_binding_clr;
350                       logic sw_binding_regwen;
351                     
352                       // this is w0c
353        1/1            assign sw_binding_clr = reg2hw.sw_binding_regwen.qe & ~reg2hw.sw_binding_regwen.q;
           Tests:       T1 T2 T3 
354                     
355                       // software clears the enable
356                       // hardware restores it upon successful advance
357                       keymgr_cfg_en #(
358                         .NonInitClr(1'b1)  // clear has an effect regardless of init state
359                       ) u_sw_binding_regwen (
360                         .clk_i,
361                         .rst_ni,
362                         .init_i(init),
363                         .en_i(lc_tx_test_true_strict(lc_keymgr_en[KeyMgrEnSwBindingEn])),
364                         .set_i(sw_binding_unlock),
365                         .clr_i(sw_binding_clr),
366                         .out_o(sw_binding_regwen)
367                       );
368                     
369        1/1            assign hw2reg.sw_binding_regwen.d = sw_binding_regwen & cfg_regwen;
           Tests:       T1 T2 T3 
370                     
371                       /////////////////////////////////////
372                       //  Key Manager Input Construction
373                       /////////////////////////////////////
374                     
375                       // The various arrays of inputs for each operation
376                       logic rom_digest_vld;
377                       logic [2**StageWidth-1:0][AdvDataWidth-1:0] adv_matrix;
378                       logic [2**StageWidth-1:0] adv_dvalid;
379                       logic [2**StageWidth-1:0][IdDataWidth-1:0] id_matrix;
380                       logic [GenDataWidth-1:0] gen_in;
381                     
382                       // The max key version for each stage
383                       logic [2**StageWidth-1:0][31:0] max_key_versions;
384                     
385                       // Number of times the lfsr output fits into the inputs
386                       localparam int AdvLfsrCopies = AdvDataWidth / 32;
387                       localparam int IdLfsrCopies = IdDataWidth / 32;
388                       localparam int GenLfsrCopies = GenDataWidth / 32;
389                     
390                       // input checking
391                       logic creator_seed_vld;
392                       logic owner_seed_vld;
393                       logic devid_vld;
394                       logic health_state_vld;
395                       logic key_version_vld;
396                     
397                       // software binding
398                       logic [SwBindingWidth-1:0] sw_binding;
399        1/1            assign sw_binding = (cdi_sel == 0) ? reg2hw.sealing_sw_binding :
           Tests:       T1 T2 T3 
400                                           (cdi_sel == 1) ? reg2hw.attest_sw_binding  : RndCnstCdi;
401                     
402                       // Advance state operation input construction
403                       for (genvar i = KeyMgrStages; i < 2**StageWidth; i++) begin : gen_adv_matrix_fill
404        1/1              assign adv_matrix[i] = {AdvLfsrCopies{data_rand[0]}};
           Tests:       T1 T2 T3 
405                         assign adv_dvalid[i] = 1'b1;
406                       end
407                     
408                       // Advance to creator_root_key
409                       // The values coming from otp_ctrl / lc_ctrl are treat as quasi-static for CDC purposes
410                       logic [KeyWidth-1:0] creator_seed;
411                       logic unused_creator_seed;
412                       if (UseOtpSeedsInsteadOfFlash) begin : gen_otp_creator_seed
413                         assign unused_creator_seed = ^{flash_i.seeds[flash_ctrl_pkg::CreatorSeedIdx],
414                                                        otp_key_i.creator_seed_valid};
415                         assign creator_seed = otp_key_i.creator_seed;
416                       end else begin : gen_flash_creator_seed
417        1/1              assign unused_creator_seed = ^{otp_key_i.creator_seed,
           Tests:       T1 T2 T3 
418                                                        otp_key_i.creator_seed_valid};
419        1/1              assign creator_seed = flash_i.seeds[flash_ctrl_pkg::CreatorSeedIdx];
           Tests:       T1 T2 T3 
420                       end
421                       // TODO(opentitan-integrated/issues/251):
422                       // replace below code with commented code once SW and DV model can handle multiple
423                       // // ROM_CTRL digests.
424                       // logic [KeyWidth*NumRomDigestInputs-1:0] rom_digests;
425                       // always_comb begin
426                       //   rom_digests = '0;
427                       //   for (int k = 0; k < NumRomDigestInputs; k++) begin
428                       //     rom_digests[KeyWidth*k +: KeyWidth] = rom_digest_i[k].data;
429                       //   end
430                       // end
431                       // assign adv_matrix[Creator] = AdvDataWidth'({sw_binding,
432                       //                                             otp_device_id_i,
433                       //                                             lc_keymgr_div_i,
434                       //                                             rom_digests,
435                       //                                             revision_seed});
436        1/1            assign adv_matrix[Creator] = AdvDataWidth'({sw_binding,
           Tests:       T1 T2 T3 
437                                                                   otp_device_id_i,
438                                                                   lc_keymgr_div_i,
439                                                                   rom_digest_i.data,
440                                                                   revision_seed});
441                     
442        1/1            assign adv_dvalid[Creator] = creator_seed_vld &
           Tests:       T1 T2 T3 
443                                                    devid_vld &
444                                                    health_state_vld &
445                                                    rom_digest_vld;
446                     
447                       // Advance to owner_intermediate_key
448                       logic [KeyWidth-1:0] owner_seed;
449                       logic unused_owner_seed;
450                       if (UseOtpSeedsInsteadOfFlash) begin : gen_otp_owner_seed
451                         assign unused_owner_seed = ^{flash_i.seeds[flash_ctrl_pkg::OwnerSeedIdx],
452                                                      otp_key_i.owner_seed_valid};
453                         assign owner_seed = otp_key_i.owner_seed;
454                       end else begin : gen_flash_owner_seed
455        1/1              assign unused_owner_seed = ^{otp_key_i.owner_seed,
           Tests:       T1 T2 T3 
456                                                      otp_key_i.owner_seed_valid};
457        1/1              assign owner_seed = flash_i.seeds[flash_ctrl_pkg::OwnerSeedIdx];
           Tests:       T1 T2 T3 
458                       end
459        1/1            assign adv_matrix[OwnerInt] = AdvDataWidth'({sw_binding, creator_seed});
           Tests:       T1 T2 T3 
460        1/1            assign adv_dvalid[OwnerInt] = owner_seed_vld;
           Tests:       T1 T2 T3 
461                     
462                       // Advance to owner_key
463        1/1            assign adv_matrix[Owner] = AdvDataWidth'({sw_binding, owner_seed});
           Tests:       T1 T2 T3 
464                       assign adv_dvalid[Owner] = 1'b1;
465                     
466                       // Generate Identity operation input construction
467                       for (genvar i = KeyMgrStages; i < 2**StageWidth; i++) begin : gen_id_matrix_fill
468        1/1              assign id_matrix[i] = {IdLfsrCopies{data_rand[0]}};
           Tests:       T1 T2 T3 
469                       end
470                     
471        0/1     ==>    assign id_matrix[Creator]  = creator_identity_seed;
472        0/1     ==>    assign id_matrix[OwnerInt] = owner_int_identity_seed;
473        0/1     ==>    assign id_matrix[Owner]    = owner_identity_seed;
474                     
475                     
476                       // Generate output operation input construction
477                       logic [KeyWidth-1:0] output_key;
478                       keymgr_key_dest_e dest_sel;
479                       logic [KeyWidth-1:0] dest_seed;
480                     
481        1/1            assign dest_sel = keymgr_key_dest_e'(reg2hw.control_shadowed.dest_sel.q);
           Tests:       T1 T2 T3 
482        1/1            assign dest_seed = dest_sel == Aes  ? aes_seed  :
           Tests:       T1 T2 T3 
483                                            dest_sel == Kmac ? kmac_seed :
484                                            dest_sel == Otbn ? otbn_seed : none_seed;
485        1/1            assign output_key = mubi4_test_true_strict(hw_key_sel) ? hard_output_seed :
           Tests:       T1 T2 T3 
486                                           soft_output_seed;
487        1/1            assign gen_in = invalid_stage_sel ? {GenLfsrCopies{lfsr[31:0]}} : {reg2hw.key_version,
           Tests:       T1 T2 T3 
488                                                                                          reg2hw.salt,
489                                                                                          dest_seed,
490                                                                                          output_key};
491                     
492                       // Advance state operation input construction
493                       for (genvar i = KeyMgrStages; i < 2**StageWidth; i++) begin : gen_key_version_fill
494                         assign max_key_versions[i] = '0;
495                       end
496                     
497        1/1            assign max_key_versions[Creator]  = reg2hw.max_creator_key_ver_shadowed.q;
           Tests:       T1 T2 T3 
498        1/1            assign max_key_versions[OwnerInt] = reg2hw.max_owner_int_key_ver_shadowed.q;
           Tests:       T1 T2 T3 
499        1/1            assign max_key_versions[Owner]    = reg2hw.max_owner_key_ver_shadowed.q;
           Tests:       T1 T2 T3 
500                     
501                     
502                       // General module for checking inputs
503                       logic key_vld;
504                       // SEC_CM: CONSTANTS.CONSISTENCY
505                       // SEC_CM: INTERSIG.CONSISTENCY
506                       keymgr_input_checks #(
507                         .KmacEnMasking(KmacEnMasking)
508                       ) u_checks (
509                         .rom_digest_i,
510                         .max_key_versions_i(max_key_versions),
511                         .stage_sel_i(stage_sel),
512                         .key_version_i(reg2hw.key_version),
513                         .creator_seed_i(creator_seed),
514                         .owner_seed_i(owner_seed),
515                         .key_i(kmac_key_o),
516                         .devid_i(otp_device_id_i),
517                         .health_state_i(HealthStateWidth'(lc_keymgr_div_i)),
518                         .creator_seed_vld_o(creator_seed_vld),
519                         .owner_seed_vld_o(owner_seed_vld),
520                         .devid_vld_o(devid_vld),
521                         .health_state_vld_o(health_state_vld),
522                         .key_version_vld_o(key_version_vld),
523                         .key_vld_o(key_vld),
524                         .rom_digest_vld_o(rom_digest_vld)
525                       );
526                     
527                       assign hw2reg.debug.invalid_creator_seed.d = 1'b1;
528                       assign hw2reg.debug.invalid_owner_seed.d = 1'b1;
529                       assign hw2reg.debug.invalid_dev_id.d = 1'b1;
530                       assign hw2reg.debug.invalid_health_state.d = 1'b1;
531                       assign hw2reg.debug.invalid_key_version.d = 1'b1;
532                       assign hw2reg.debug.invalid_key.d = 1'b1;
533                       assign hw2reg.debug.invalid_digest.d = 1'b1;
534                     
535                       logic valid_op;
536        1/1            assign valid_op = adv_en | id_en | gen_en;
           Tests:       T1 T2 T3 
537        1/1            assign hw2reg.debug.invalid_creator_seed.de = adv_en & (stage_sel == Creator) & ~creator_seed_vld;
           Tests:       T1 T2 T3 
538        1/1            assign hw2reg.debug.invalid_owner_seed.de = adv_en & (stage_sel == OwnerInt) & ~owner_seed_vld;
           Tests:       T1 T2 T3 
539        1/1            assign hw2reg.debug.invalid_dev_id.de = adv_en & (stage_sel == Creator) & ~devid_vld;
           Tests:       T1 T2 T3 
540        1/1            assign hw2reg.debug.invalid_health_state.de = adv_en & (stage_sel == Creator) & ~health_state_vld;
           Tests:       T1 T2 T3 
541        1/1            assign hw2reg.debug.invalid_key_version.de = gen_en & ~key_version_vld;
           Tests:       T1 T2 T3 
542        1/1            assign hw2reg.debug.invalid_key.de = valid_op & ~key_vld;
           Tests:       T1 T2 T3 
543        1/1            assign hw2reg.debug.invalid_digest.de = adv_en & (stage_sel == Creator) & ~rom_digest_vld;
           Tests:       T1 T2 T3 
544                     
545                       /////////////////////////////////////
546                       //  KMAC Control
547                       /////////////////////////////////////
548                     
549                       logic [3:0] invalid_data;
550        1/1            assign invalid_data[OpAdvance]  = ~key_vld | ~adv_dvalid[stage_sel];
           Tests:       T1 T2 T3 
551        1/1            assign invalid_data[OpGenId]    = ~key_vld;
           Tests:       T1 T2 T3 
552        1/1            assign invalid_data[OpGenSwOut] = ~key_vld | ~key_version_vld;
           Tests:       T1 T2 T3 
553        1/1            assign invalid_data[OpGenHwOut] = ~key_vld | ~key_version_vld;
           Tests:       T1 T2 T3 
554                     
555                       keymgr_kmac_if #(
556                         .RndCnstRandPerm(RndCnstRandPerm)
557                       ) u_kmac_if (
558                         .clk_i,
559                         .rst_ni,
560                         .prng_en_o(data_lfsr_en),
561                         .adv_data_i(adv_matrix[stage_sel]),
562                         .id_data_i(id_matrix[stage_sel]),
563                         .gen_data_i(gen_in),
564                         .inputs_invalid_i(invalid_data),
565                         .inputs_invalid_o(kmac_input_invalid),
566                         .adv_en_i(adv_en),
567                         .id_en_i(id_en),
568                         .gen_en_i(gen_en),
569                         .done_o(kmac_done),
570                         .data_o(kmac_data),
571                         .kmac_data_o,
572                         .kmac_data_i,
573                         .entropy_i(data_rand),
574                         .fsm_error_o(kmac_fsm_err),
575                         .kmac_error_o(kmac_op_err),
576                         .kmac_done_error_o(kmac_done_err),
577                         .cmd_error_o(kmac_cmd_err)
578                       );
579                     
580                     
581                       /////////////////////////////////////
582                       //  Side load key storage
583                       /////////////////////////////////////
584                       // SEC_CM: HW.KEY.SW_NOACCESS
585                       keymgr_sideload_key_ctrl u_sideload_ctrl (
586                         .clk_i,
587                         .rst_ni,
588                         .init_i(init),
589                         .entropy_i(data_rand),
590                         .clr_key_i(keymgr_sideload_clr_e'(reg2hw.sideload_clear.q)),
591                         .wipe_key_i(wipe_key),
592                         .dest_sel_i(dest_sel),
593                         .hw_key_sel_i(hw_key_sel),
594                         // SEC_CM: OUTPUT_KEYS.CTRL.REDUN
595                         .data_en_i(data_hw_en),
596                         .data_valid_i(data_valid),
597                         .key_i(kmac_key),
598                         .data_i(kmac_data),
599                         .prng_en_o(sideload_lfsr_en),
600                         .aes_key_o,
601                         .otbn_key_o,
602                         .kmac_key_o,
603                         .sideload_sel_err_o(sideload_sel_err),
604                         .fsm_err_o(sideload_fsm_err)
605                       );
606                     
607                       for (genvar i = 0; i < 8; i++) begin : gen_sw_assigns
608                     
609                         prim_mubi_pkg::mubi4_t [1:0] hw_key_sel_buf;
610                         prim_mubi4_sync #(
611                           .NumCopies(2),
612                           .AsyncOn(0)
613                         ) u_mubi_buf (
614                           .clk_i,
615                           .rst_ni,
616                           .mubi_i(hw_key_sel),
617                           .mubi_o(hw_key_sel_buf)
618                         );
619                     
620                         // SEC_CM: OUTPUT_KEYS.CTRL.REDUN
621                         prim_sec_anchor_buf #(
622                          .Width(32)
623                         ) u_prim_buf_share0_d (
624                           .in_i(~data_sw_en | wipe_key ? data_rand[0] : kmac_data[0][i*32 +: 32]),
625                           .out_o(hw2reg.sw_share0_output[i].d)
626                         );
627                     
628                         prim_sec_anchor_buf #(
629                          .Width(32)
630                         ) u_prim_buf_share1_d (
631                           .in_i(~data_sw_en | wipe_key ? data_rand[1] : kmac_data[1][i*32 +: 32]),
632                           .out_o(hw2reg.sw_share1_output[i].d)
633                         );
634                     
635                         prim_sec_anchor_buf #(
636                          .Width(1)
637                         ) u_prim_buf_share0_de (
638                           .in_i(wipe_key | data_valid & mubi4_test_false_strict(hw_key_sel_buf[0])),
639                           .out_o(hw2reg.sw_share0_output[i].de)
640                         );
641                     
642                         prim_sec_anchor_buf #(
643                          .Width(1)
644                         ) u_prim_buf_share1_de (
645                           .in_i(wipe_key | data_valid & mubi4_test_false_strict(hw_key_sel_buf[1])),
646                           .out_o(hw2reg.sw_share1_output[i].de)
647                         );
648                       end
649                     
650                       /////////////////////////////////////
651                       //  Alerts and Interrupts
652                       /////////////////////////////////////
653                     
654                       prim_intr_hw #(.Width(1)) u_intr_op_done (
655                         .clk_i,
656                         .rst_ni,
657                         .event_intr_i           (op_done),
658                         .reg2hw_intr_enable_q_i (reg2hw.intr_enable.q),
659                         .reg2hw_intr_test_q_i   (reg2hw.intr_test.q),
660                         .reg2hw_intr_test_qe_i  (reg2hw.intr_test.qe),
661                         .reg2hw_intr_state_q_i  (reg2hw.intr_state.q),
662                         .hw2reg_intr_state_de_o (hw2reg.intr_state.de),
663                         .hw2reg_intr_state_d_o  (hw2reg.intr_state.d),
664                         .intr_o                 (intr_op_done_o)
665                       );
666                     
667                       assign hw2reg.err_code.invalid_op.d             = 1'b1;
668                       assign hw2reg.err_code.invalid_kmac_input.d     = 1'b1;
669                       assign hw2reg.err_code.invalid_shadow_update.d  = 1'b1;
670        1/1            assign hw2reg.err_code.invalid_op.de            = err_code[ErrInvalidOp];
           Tests:       T1 T2 T3 
671        1/1            assign hw2reg.err_code.invalid_kmac_input.de    = err_code[ErrInvalidIn];
           Tests:       T1 T2 T3 
672        1/1            assign hw2reg.err_code.invalid_shadow_update.de = err_code[ErrShadowUpdate];
           Tests:       T1 T2 T3 
673                     
674        1/1            assign hw2reg.fault_status.cmd.de           = fault_code[FaultKmacCmd];
           Tests:       T1 T2 T3 
675        1/1            assign hw2reg.fault_status.kmac_fsm.de      = fault_code[FaultKmacFsm];
           Tests:       T1 T2 T3 
676        1/1            assign hw2reg.fault_status.kmac_op.de       = fault_code[FaultKmacOp];
           Tests:       T1 T2 T3 
677        1/1            assign hw2reg.fault_status.kmac_done.de     = fault_code[FaultKmacDone];
           Tests:       T1 T2 T3 
678        1/1            assign hw2reg.fault_status.kmac_out.de      = fault_code[FaultKmacOut];
           Tests:       T1 T2 T3 
679        1/1            assign hw2reg.fault_status.regfile_intg.de  = fault_code[FaultRegIntg];
           Tests:       T1 T2 T3 
680        1/1            assign hw2reg.fault_status.shadow.de        = fault_code[FaultShadow];
           Tests:       T1 T2 T3 
681        1/1            assign hw2reg.fault_status.ctrl_fsm_intg.de = fault_code[FaultCtrlFsm];
           Tests:       T1 T2 T3 
682        1/1            assign hw2reg.fault_status.ctrl_fsm_chk.de  = fault_code[FaultCtrlFsmChk];
           Tests:       T1 T2 T3 
683        1/1            assign hw2reg.fault_status.ctrl_fsm_cnt.de  = fault_code[FaultCtrlCnt];
           Tests:       T1 T2 T3 
684        1/1            assign hw2reg.fault_status.reseed_cnt.de    = fault_code[FaultReseedCnt];
           Tests:       T1 T2 T3 
685        1/1            assign hw2reg.fault_status.side_ctrl_fsm.de = fault_code[FaultSideFsm];
           Tests:       T1 T2 T3 
686        1/1            assign hw2reg.fault_status.side_ctrl_sel.de = fault_code[FaultSideSel];
           Tests:       T1 T2 T3 
687        1/1            assign hw2reg.fault_status.key_ecc.de       = fault_code[FaultKeyEcc];
           Tests:       T1 T2 T3 
688                       assign hw2reg.fault_status.cmd.d            = 1'b1;
689                       assign hw2reg.fault_status.kmac_fsm.d       = 1'b1;
690                       assign hw2reg.fault_status.kmac_done.d      = 1'b1;
691                       assign hw2reg.fault_status.kmac_op.d        = 1'b1;
692                       assign hw2reg.fault_status.kmac_out.d       = 1'b1;
693                       assign hw2reg.fault_status.regfile_intg.d   = 1'b1;
694                       assign hw2reg.fault_status.shadow.d         = 1'b1;
695                       assign hw2reg.fault_status.ctrl_fsm_intg.d  = 1'b1;
696                       assign hw2reg.fault_status.ctrl_fsm_chk.d   = 1'b1;
697                       assign hw2reg.fault_status.ctrl_fsm_cnt.d   = 1'b1;
698                       assign hw2reg.fault_status.reseed_cnt.d     = 1'b1;
699                       assign hw2reg.fault_status.side_ctrl_fsm.d  = 1'b1;
700                       assign hw2reg.fault_status.side_ctrl_sel.d  = 1'b1;
701                       assign hw2reg.fault_status.key_ecc.d        = 1'b1;
702                     
703                       // There are two types of alerts
704                       // - alerts for hardware errors, these could not have been generated by software.
705                       // - alerts for errors that may have been generated by software.
706                     
707                       logic fault_errs, fault_err_req_q, fault_err_req_d, fault_err_ack;
708                       logic op_errs, op_err_req_q, op_err_req_d, op_err_ack;
709                     
710                       // Fault status can happen independently of any operation
711        1/1            assign fault_errs = |reg2hw.fault_status;
           Tests:       T1 T2 T3 
712                     
713        1/1            assign fault_err_req_d = fault_errs    ? 1'b1 :
           Tests:       T1 T2 T3 
714                                                fault_err_ack ? 1'b0 : fault_err_req_q;
715                     
716        1/1            assign op_errs = |err_code;
           Tests:       T1 T2 T3 
717        1/1            assign op_err_req_d = op_errs    ? 1'b1 :
           Tests:       T1 T2 T3 
718                                             op_err_ack ? 1'b0 : op_err_req_q;
719                     
720                       always_ff @(posedge clk_i or negedge rst_ni) begin
721        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
722        1/1                fault_err_req_q <= '0;
           Tests:       T1 T2 T3 
723        1/1                op_err_req_q <= '0;
           Tests:       T1 T2 T3 
724                         end else begin
725        1/1                fault_err_req_q <= fault_err_req_d;
           Tests:       T1 T2 T3 
726        1/1                op_err_req_q <= op_err_req_d;
           Tests:       T1 T2 T3 
727                         end
728                       end
729                     
730                       logic fault_alert_test;
731        1/1            assign fault_alert_test = reg2hw.alert_test.fatal_fault_err.q &
           Tests:       T1 T2 T3 
732                                                 reg2hw.alert_test.fatal_fault_err.qe;
733                       prim_alert_sender #(
734                         .AsyncOn(AlertAsyncOn[1]),
735                         .IsFatal(1)
736                       ) u_fault_alert (
737                         .clk_i,
738                         .rst_ni,
739                         .alert_test_i(fault_alert_test),
740                         .alert_req_i(fault_err_req_q),
741                         .alert_ack_o(fault_err_ack),
742                         .alert_state_o(),
743                         .alert_rx_i(alert_rx_i[1]),
744                         .alert_tx_o(alert_tx_o[1])
745                       );
746                     
747                       logic op_err_alert_test;
748        1/1            assign op_err_alert_test = reg2hw.alert_test.recov_operation_err.q &
           Tests:       T1 T2 T3 
749                                                  reg2hw.alert_test.recov_operation_err.qe;
750                       prim_alert_sender #(
751                         .AsyncOn(AlertAsyncOn[0]),
752                         .IsFatal(0)
753                       ) u_op_err_alert (
754                         .clk_i,
755                         .rst_ni,
756                         .alert_test_i(op_err_alert_test),
757                         .alert_req_i(op_err_req_q),
758                         .alert_ack_o(op_err_ack),
759                         .alert_state_o(),
760                         .alert_rx_i(alert_rx_i[0]),
761                         .alert_tx_o(alert_tx_o[0])
762                       );
763                     
764                       // known asserts
765                       `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid)
766                       `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready)
767                       `ASSERT_KNOWN(IntrKnownO_A, intr_op_done_o)
768                       `ASSERT_KNOWN(AlertKnownO_A, alert_tx_o)
769                     
770                       `ASSERT_KNOWN(AesKeyKnownO_A,  aes_key_o)
771                       `ASSERT_KNOWN(KmacKeyKnownO_A, kmac_key_o)
772                       `ASSERT_KNOWN(OtbnKeyKnownO_A, otbn_key_o)
773                       `ASSERT_KNOWN(KmacDataKnownO_A, kmac_data_o)
774                     
775                     
776                       // kmac parameter consistency
777                       // Both modules must be consistent with regards to masking assumptions
778                       logic unused_kmac_en_masking;
779        unreachable    assign unused_kmac_en_masking = kmac_en_masking_i;

---

Cond Coverage for Module : keymgr

	Total	Covered	Percent
Conditions	183	180	98.36
Logical	183	180	98.36
Non-Logical	0	0
Event	0	0

 LINE       210
 EXPRESSION (ctrl_lfsr_en | data_lfsr_en | sideload_lfsr_en)
             ------1-----   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       336
 EXPRESSION (op_start & op_done)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       353
 EXPRESSION (reg2hw.sw_binding_regwen.qe & ((~reg2hw.sw_binding_regwen.q)))
             -------------1-------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T16,T18
1	1	Covered	T1,T4,T16

 LINE       369
 EXPRESSION (sw_binding_regwen & cfg_regwen)
             --------1--------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       399
 EXPRESSION ((cdi_sel == 1'b0) ? reg2hw.sealing_sw_binding : ((cdi_sel == 1'b1) ? reg2hw.attest_sw_binding : RndCnstCdi))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       399
 SUB-EXPRESSION (cdi_sel == 1'b0)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       399
 SUB-EXPRESSION ((cdi_sel == 1'b1) ? reg2hw.attest_sw_binding : RndCnstCdi)
                 --------1--------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       399
 SUB-EXPRESSION (cdi_sel == 1'b1)
                --------1--------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       442
 EXPRESSION (creator_seed_vld & devid_vld & health_state_vld & rom_digest_vld)
             --------1-------   ----2----   --------3-------   -------4------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T24,T44,T45
1	0	1	1	Covered	T24,T25,T26
1	1	0	1	Covered	T25,T26,T46
1	1	1	0	Covered	T47,T25,T48
1	1	1	1	Covered	T1,T2,T3

 LINE       482
 EXPRESSION ((dest_sel == Aes) ? aes_seed : ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed)))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T14

 LINE       482
 SUB-EXPRESSION (dest_sel == Aes)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T14

 LINE       482
 SUB-EXPRESSION ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       482
 SUB-EXPRESSION (dest_sel == Kmac)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       482
 SUB-EXPRESSION ((dest_sel == Otbn) ? otbn_seed : none_seed)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       482
 SUB-EXPRESSION (dest_sel == Otbn)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       487
 EXPRESSION (invalid_stage_sel ? ({GenLfsrCopies {lfsr[31:0]}}) : ({reg2hw.key_version, reg2hw.salt, dest_seed, output_key}))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       536
 EXPRESSION (adv_en | id_en | gen_en)
             ---1--   --2--   ---3--

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T1,T2,T3

 LINE       537
 EXPRESSION (adv_en & (stage_sel == Creator) & ((~creator_seed_vld)))
             ---1--   -----------2----------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T49,T45,T50
1	0	1	Covered	T24,T51,T52
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T49,T45,T50

 LINE       537
 SUB-EXPRESSION (stage_sel == Creator)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       538
 EXPRESSION (adv_en & (stage_sel == OwnerInt) & ((~owner_seed_vld)))
             ---1--   -----------2-----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T22,T54
1	0	1	Covered	T24,T25,T53
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T22,T54

 LINE       538
 SUB-EXPRESSION (stage_sel == OwnerInt)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       539
 EXPRESSION (adv_en & (stage_sel == Creator) & ((~devid_vld)))
             ---1--   -----------2----------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T25,T26
1	0	1	Covered	T48,T26,T55
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T24,T25,T26

 LINE       539
 SUB-EXPRESSION (stage_sel == Creator)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       540
 EXPRESSION (adv_en & (stage_sel == Creator) & ((~health_state_vld)))
             ---1--   -----------2----------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T25,T26
1	0	1	Covered	T48,T26,T55
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T24,T25,T26

 LINE       540
 SUB-EXPRESSION (stage_sel == Creator)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       541
 EXPRESSION (gen_en & ((~key_version_vld)))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T20,T24

 LINE       542
 EXPRESSION (valid_op & ((~key_vld)))
             ----1---   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T23,T27

 LINE       543
 EXPRESSION (adv_en & (stage_sel == Creator) & ((~rom_digest_vld)))
             ---1--   -----------2----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T25,T26
1	0	1	Covered	T48,T26,T55
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T24,T25,T26

 LINE       543
 SUB-EXPRESSION (stage_sel == Creator)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       550
 EXPRESSION (((~key_vld)) | ((~adv_dvalid[stage_sel])))
             ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T24,T25,T26
1	0	Covered	T1,T2,T3

 LINE       552
 EXPRESSION (((~key_vld)) | ((~key_version_vld)))
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T16
1	0	Covered	T1,T2,T3

 LINE       553
 EXPRESSION (((~key_vld)) | ((~key_version_vld)))
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T16
1	0	Covered	T1,T2,T3

 LINE       623
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(0 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       623
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T16,T56,T57
1	0	Covered	T1,T2,T3

 LINE       623
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(1 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       623
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T16,T56,T57
1	0	Covered	T1,T2,T3

 LINE       623
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(2 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       623
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T16,T56,T57
1	0	Covered	T1,T2,T3

 LINE       623
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(3 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       623
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T16,T56,T57
1	0	Covered	T1,T2,T3

 LINE       623
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(4 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       623
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T16,T56,T57
1	0	Covered	T1,T2,T3

 LINE       623
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(5 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       623
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T16,T56,T57
1	0	Covered	T1,T2,T3

 LINE       623
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(6 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       623
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T16,T56,T57
1	0	Covered	T1,T2,T3

 LINE       623
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(7 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       623
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T16,T56,T57
1	0	Covered	T1,T2,T3

 LINE       630
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(0 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       630
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T16,T56,T57
1	0	Covered	T1,T2,T3

 LINE       630
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(1 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       630
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T16,T56,T57
1	0	Covered	T1,T2,T3

 LINE       630
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(2 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       630
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T16,T56,T57
1	0	Covered	T1,T2,T3

 LINE       630
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(3 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       630
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T16,T56,T57
1	0	Covered	T1,T2,T3

 LINE       630
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(4 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       630
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T16,T56,T57
1	0	Covered	T1,T2,T3

 LINE       630
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(5 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       630
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T16,T56,T57
1	0	Covered	T1,T2,T3

 LINE       630
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(6 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       630
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T16,T56,T57
1	0	Covered	T1,T2,T3

 LINE       630
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(7 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       630
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T16,T56,T57
1	0	Covered	T1,T2,T3

 LINE       713
 EXPRESSION (fault_errs ? 1'b1 : (fault_err_ack ? 1'b0 : fault_err_req_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T36,T35

 LINE       713
 SUB-EXPRESSION (fault_err_ack ? 1'b0 : fault_err_req_q)
                 ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       717
 EXPRESSION (op_errs ? 1'b1 : (op_err_ack ? 1'b0 : op_err_req_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       717
 SUB-EXPRESSION (op_err_ack ? 1'b0 : op_err_req_q)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       731
 EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T58,T59,T60
1	0	Covered	T1,T2,T3
1	1	Covered	T58,T59,T60

 LINE       748
 EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
             -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T58,T59,T60
1	0	Covered	T1,T2,T3
1	1	Covered	T58,T59,T60

---

Toggle Coverage for Module : keymgr

	Total	Covered	Percent
Totals	67	65	97.01
Total Bits	10068	10064	99.96
Total Bits 0->1	5034	5032	99.96
Total Bits 1->0	5034	5032	99.96

Ports	67	65	97.01
Port Bits	10068	10064	99.96
Port Bits 0->1	5034	5032	99.96
Port Bits 1->0	5034	5032	99.96

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T16,T36,T35	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T16,T36,T35	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T16,T36,T35	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T4,T15	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T20,T61	Yes	T2,T20,T61	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T35,T62,T63	Yes	T35,T62,T63	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1:0][255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.valid	Yes	Yes	T14,T20,T64	Yes	T14,T42,T20	OUTPUT
kmac_key_o.key[1:0][255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_key_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1:0][383:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_i.error	Yes	Yes	T28,T65,T66	Yes	T16,T35,T37	INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T3,T14,T16	Yes	T1,T2,T3	INPUT
kmac_en_masking_i	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_en_i[3:0]	Yes	Yes	T4,T36,T11	Yes	T1,T2,T4	INPUT
lc_keymgr_div_i[127:0]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
otp_key_i.owner_seed_valid	Yes	Yes	T63,T56,T28	Yes	T63,T56,T67	INPUT
otp_key_i.owner_seed[255:0]	Yes	Yes	T16,T63,T68	Yes	T63,T28,T69	INPUT
otp_key_i.creator_seed_valid	Yes	Yes	T70,T63,T69	Yes	T70,T63,T71	INPUT
otp_key_i.creator_seed[255:0]	Yes	Yes	T63,T68,T71	Yes	T16,T63,T67	INPUT
otp_key_i.creator_root_key_share1_valid	No	No		No		INPUT
otp_key_i.creator_root_key_share1[255:0]	Yes	Yes	T70,T63,T56	Yes	T16,T70,T63	INPUT
otp_key_i.creator_root_key_share0_valid	No	No		No		INPUT
otp_key_i.creator_root_key_share0[255:0]	Yes	Yes	T70,T56,T67	Yes	T70,T56,T69	INPUT
otp_device_id_i[255:0]	Yes	Yes	T4,T16,T18	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][0]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][1]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][3:2]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][4]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][5]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][6]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][7]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][8]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][9]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][10]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][11]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][14:12]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][15]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][16]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][17]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][18]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][19]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][20]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][21]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][23:22]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][24]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][25]	Yes	Yes	T1,T4,T18	Yes	T1,T4,T18	INPUT
flash_i.seeds[0][26]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][28:27]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][29]	Yes	Yes	T1,T4,T18	Yes	T1,T4,T18	INPUT
flash_i.seeds[0][30]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][31]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][34:32]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][35]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][36]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][37]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][38]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][39]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][40]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][41]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][42]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][43]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][45:44]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][46]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][47]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][48]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][49]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][50]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][52:51]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][53]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][54]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][55]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][56]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][57]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][58]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][60:59]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][61]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][62]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][63]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][65:64]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][67:66]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][68]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][69]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][70]	Yes	Yes	T1,T16,T18	Yes	T1,T16,T18	INPUT
flash_i.seeds[0][71]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][72]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][73]	Yes	Yes	T1,T4,T18	Yes	T1,T4,T18	INPUT
flash_i.seeds[0][74]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][75]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][76]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][77]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][78]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][79]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][80]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][81]	Yes	Yes	T1,T16,T18	Yes	T1,T16,T18	INPUT
flash_i.seeds[0][83:82]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][84]	Yes	Yes	T1,T16,T18	Yes	T1,T16,T18	INPUT
flash_i.seeds[0][85]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][86]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][87]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][88]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][89]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][90]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][91]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][93:92]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][95:94]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][96]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][97]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][98]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][99]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][100]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][101]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][102]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][103]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][104]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][105]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][106]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][107]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][108]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][109]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][110]	Yes	Yes	T4,T16,T19	Yes	T4,T16,T19	INPUT
flash_i.seeds[0][112:111]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][113]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][114]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][117:115]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][118]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][119]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][120]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][121]	Yes	Yes	T4,T16,T19	Yes	T4,T16,T19	INPUT
flash_i.seeds[0][122]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][123]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][124]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][125]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][126]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][127]	Yes	Yes	T16,T18,T19	Yes	T16,T18,T19	INPUT
flash_i.seeds[0][128]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][129]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][130]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][131]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][132]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][133]	Yes	Yes	T1,T4,T18	Yes	T1,T4,T18	INPUT
flash_i.seeds[0][134]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][135]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][136]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][138:137]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][139]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][140]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][141]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][142]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][143]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][144]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][145]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][146]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][147]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][148]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][149]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][150]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][151]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][152]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][155:153]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][156]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][157]	Yes	Yes	T1,T4,T18	Yes	T1,T4,T18	INPUT
flash_i.seeds[0][158]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][159]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][160]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][161]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][162]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][163]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][164]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][165]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][166]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][167]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][168]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][169]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][171:170]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][172]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][174:173]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][175]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][176]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][177]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][178]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][182:179]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][183]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][184]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][185]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][186]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][187]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][188]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][189]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][190]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][191]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][192]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][193]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][194]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][195]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][196]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][197]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][198]	Yes	Yes	T4,T18,T36	Yes	T4,T18,T36	INPUT
flash_i.seeds[0][199]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][200]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][201]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][202]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][203]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][204]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][205]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][206]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][207]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][208]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][210:209]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][211]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][212]	Yes	Yes	T1,T4,T18	Yes	T1,T4,T18	INPUT
flash_i.seeds[0][213]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][214]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][215]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][216]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][217]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][218]	Yes	Yes	T4,T18,T42	Yes	T4,T18,T42	INPUT
flash_i.seeds[0][219]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][220]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][221]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][222]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][223]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][224]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][225]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][226]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][227]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][228]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][229]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][231:230]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][234:232]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][235]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][236]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][237]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][238]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][240:239]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][241]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][242]	Yes	Yes	T4,T16,T19	Yes	T4,T16,T19	INPUT
flash_i.seeds[0][243]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][244]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][245]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][247:246]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][248]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][249]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][250]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[0][251]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][252]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][253]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][254]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[0][255]	Yes	Yes	T4,T18,T19	Yes	T4,T18,T19	INPUT
flash_i.seeds[1][0]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][1]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][2]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][3]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][4]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][5]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][6]	Yes	Yes	T1,T16,T18	Yes	T1,T16,T18	INPUT
flash_i.seeds[1][7]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][8]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][9]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][10]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][11]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][12]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][13]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][14]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][15]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][16]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][17]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][18]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][19]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][20]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][22:21]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][23]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][24]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][25]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][26]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][27]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][28]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][29]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][30]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][31]	Yes	Yes	T4,T18,T19	Yes	T4,T18,T19	INPUT
flash_i.seeds[1][32]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][33]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][34]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][35]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][36]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][37]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][38]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][39]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][40]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][41]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][43:42]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][44]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][45]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][46]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][48:47]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][49]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][50]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][51]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][52]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][53]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][54]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][55]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][56]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][57]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][58]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][59]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][60]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][61]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][62]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][63]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][64]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][65]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][66]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][67]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][68]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][70:69]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][71]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][72]	Yes	Yes	T1,T16,T18	Yes	T1,T16,T18	INPUT
flash_i.seeds[1][73]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][74]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][75]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][76]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][77]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][78]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][79]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][80]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][81]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][82]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][83]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][84]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][86:85]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][87]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][89:88]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][90]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][91]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][92]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][93]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][94]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][96:95]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][97]	Yes	Yes	T1,T16,T18	Yes	T1,T16,T18	INPUT
flash_i.seeds[1][98]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][99]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][100]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][101]	Yes	Yes	T4,T16,T19	Yes	T4,T16,T19	INPUT
flash_i.seeds[1][102]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][103]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][104]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][105]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][106]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][107]	Yes	Yes	T4,T18,T19	Yes	T4,T18,T19	INPUT
flash_i.seeds[1][108]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][109]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][110]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][111]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][112]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][113]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][114]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][115]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][116]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][117]	Yes	Yes	T16,T18,T19	Yes	T16,T18,T19	INPUT
flash_i.seeds[1][118]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][119]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][120]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][121]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][122]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][123]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][124]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][125]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][126]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][127]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][128]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][129]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][130]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][131]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][132]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][133]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][134]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][135]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][136]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][137]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][138]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][139]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][140]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][141]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][142]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][143]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][144]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][145]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][146]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][147]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][149:148]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][150]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][151]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][152]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][153]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][154]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][155]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][156]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][157]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][158]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][159]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][161:160]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][162]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][164:163]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][165]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][166]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][167]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][169:168]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][170]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][171]	Yes	Yes	T16,T18,T19	Yes	T16,T18,T19	INPUT
flash_i.seeds[1][172]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][173]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][174]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][175]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][176]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][177]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][178]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][179]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][180]	Yes	Yes	T1,T4,T18	Yes	T1,T4,T18	INPUT
flash_i.seeds[1][181]	Yes	Yes	T16,T19,T42	Yes	T16,T19,T42	INPUT
flash_i.seeds[1][183:182]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][184]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][186:185]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][187]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][188]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][189]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][191:190]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][192]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][193]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][194]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][195]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][196]	Yes	Yes	T16,T18,T19	Yes	T16,T18,T19	INPUT
flash_i.seeds[1][197]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][198]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][199]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][200]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][201]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][202]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][203]	Yes	Yes	T1,T16,T18	Yes	T1,T16,T18	INPUT
flash_i.seeds[1][204]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][205]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][206]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][207]	Yes	Yes	T1,T16,T18	Yes	T1,T16,T18	INPUT
flash_i.seeds[1][208]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][209]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][210]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][211]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][212]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][214:213]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][215]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][216]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][217]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][218]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][219]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][220]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][221]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][222]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][223]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][224]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][225]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][226]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][227]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][228]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][230:229]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][231]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][232]	Yes	Yes	T1,T16,T18	Yes	T1,T16,T18	INPUT
flash_i.seeds[1][233]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][234]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][235]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][236]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][237]	Yes	Yes	T1,T4,T18	Yes	T1,T4,T18	INPUT
flash_i.seeds[1][238]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][239]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][240]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][241]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][242]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][244:243]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][245]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][246]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][247]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][249:248]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][250]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][251]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][252]	Yes	Yes	T1,T4,T16	Yes	T1,T4,T16	INPUT
flash_i.seeds[1][253]	Yes	Yes	T16,T18,T19	Yes	T16,T18,T19	INPUT
flash_i.seeds[1][254]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
flash_i.seeds[1][255]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
edn_i.edn_fips	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_digest_i.valid	Yes	Yes	T24,T25,T48	Yes	T24,T25,T48	INPUT
rom_digest_i.data[255:0]	Yes	Yes	T4,T16,T18	Yes	T4,T16,T18	INPUT
intr_op_done_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T16,T36,T35	Yes	T16,T36,T35	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T16,T36,T35	Yes	T16,T36,T35	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : keymgr

	Line No.	Total	Covered	Percent
Branches		49	47	95.92
TERNARY	399	3	2	66.67
TERNARY	482	4	4	100.00
TERNARY	487	2	2	100.00
TERNARY	713	3	2	66.67
TERNARY	717	3	3	100.00
TERNARY	623	2	2	100.00
TERNARY	630	2	2	100.00
TERNARY	623	2	2	100.00
TERNARY	630	2	2	100.00
TERNARY	623	2	2	100.00
TERNARY	630	2	2	100.00
TERNARY	623	2	2	100.00
TERNARY	630	2	2	100.00
TERNARY	623	2	2	100.00
TERNARY	630	2	2	100.00
TERNARY	623	2	2	100.00
TERNARY	630	2	2	100.00
TERNARY	623	2	2	100.00
TERNARY	630	2	2	100.00
TERNARY	623	2	2	100.00
TERNARY	630	2	2	100.00
IF	721	2	2	100.00

399          assign sw_binding = (cdi_sel == 0) ? reg2hw.sealing_sw_binding :
                                                -1-  
                                                ==>  
400                              (cdi_sel == 1) ? reg2hw.attest_sw_binding  : RndCnstCdi;
                                                -2-  
                                                ==>  
                                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

482          assign dest_seed = dest_sel == Aes  ? aes_seed  :
                                                 -1-  
                                                 ==>  
483                               dest_sel == Kmac ? kmac_seed :
                                                   -2-  
                                                   ==>  
484                               dest_sel == Otbn ? otbn_seed : none_seed;
                                                   -3-  
                                                   ==>  
                                                   ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T3,T4,T14
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

487          assign gen_in = invalid_stage_sel ? {GenLfsrCopies{lfsr[31:0]}} : {reg2hw.key_version,
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

713          assign fault_err_req_d = fault_errs    ? 1'b1 :
                                                    -1-  
                                                    ==>  
714                                   fault_err_ack ? 1'b0 : fault_err_req_q;
                                                    -2-  
                                                    ==>  
                                                    ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T36,T35
0	1	Not Covered
0	0	Covered	T1,T2,T3

717          assign op_err_req_d = op_errs    ? 1'b1 :
                                              -1-  
                                              ==>  
718                                op_err_ack ? 1'b0 : op_err_req_q;
                                              -2-  
                                              ==>  
                                              ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

623            ) u_prim_buf_share0_d (
                                      
624              .in_i(~data_sw_en | wipe_key ? data_rand[0] : kmac_data[0][i*32 +: 32]),
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

630            ) u_prim_buf_share1_d (
                                      
631              .in_i(~data_sw_en | wipe_key ? data_rand[1] : kmac_data[1][i*32 +: 32]),
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

623            ) u_prim_buf_share0_d (
                                      
624              .in_i(~data_sw_en | wipe_key ? data_rand[0] : kmac_data[0][i*32 +: 32]),
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

630            ) u_prim_buf_share1_d (
                                      
631              .in_i(~data_sw_en | wipe_key ? data_rand[1] : kmac_data[1][i*32 +: 32]),
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

623            ) u_prim_buf_share0_d (
                                      
624              .in_i(~data_sw_en | wipe_key ? data_rand[0] : kmac_data[0][i*32 +: 32]),
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

630            ) u_prim_buf_share1_d (
                                      
631              .in_i(~data_sw_en | wipe_key ? data_rand[1] : kmac_data[1][i*32 +: 32]),
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

623            ) u_prim_buf_share0_d (
                                      
624              .in_i(~data_sw_en | wipe_key ? data_rand[0] : kmac_data[0][i*32 +: 32]),
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

630            ) u_prim_buf_share1_d (
                                      
631              .in_i(~data_sw_en | wipe_key ? data_rand[1] : kmac_data[1][i*32 +: 32]),
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

623            ) u_prim_buf_share0_d (
                                      
624              .in_i(~data_sw_en | wipe_key ? data_rand[0] : kmac_data[0][i*32 +: 32]),
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

630            ) u_prim_buf_share1_d (
                                      
631              .in_i(~data_sw_en | wipe_key ? data_rand[1] : kmac_data[1][i*32 +: 32]),
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

623            ) u_prim_buf_share0_d (
                                      
624              .in_i(~data_sw_en | wipe_key ? data_rand[0] : kmac_data[0][i*32 +: 32]),
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

630            ) u_prim_buf_share1_d (
                                      
631              .in_i(~data_sw_en | wipe_key ? data_rand[1] : kmac_data[1][i*32 +: 32]),
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

623            ) u_prim_buf_share0_d (
                                      
624              .in_i(~data_sw_en | wipe_key ? data_rand[0] : kmac_data[0][i*32 +: 32]),
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

630            ) u_prim_buf_share1_d (
                                      
631              .in_i(~data_sw_en | wipe_key ? data_rand[1] : kmac_data[1][i*32 +: 32]),
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

623            ) u_prim_buf_share0_d (
                                      
624              .in_i(~data_sw_en | wipe_key ? data_rand[0] : kmac_data[0][i*32 +: 32]),
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

630            ) u_prim_buf_share1_d (
                                      
631              .in_i(~data_sw_en | wipe_key ? data_rand[1] : kmac_data[1][i*32 +: 32]),
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

721            if (!rst_ni) begin
               -1-  
722              fault_err_req_q <= '0;
                 ==>
723              op_err_req_q <= '0;
724            end else begin
725              fault_err_req_q <= fault_err_req_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keymgr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AdvDataWidth_A	874	874	0	0
AesKeyKnownO_A	20641695	20475249	0	0
AlertKnownO_A	20641695	20475249	0	0
ErrCntMatch_A	874	874	0	0
FaultCntMatch_A	874	874	0	0
FpvSecCmCtrlCntAlertCheck_A	20641695	80	0	0
FpvSecCmCtrlDataFsmCheck_A	20641695	80	0	0
FpvSecCmCtrlMainFsmCheck_A	20641695	80	0	0
FpvSecCmCtrlOpFsmCheck_A	20641695	80	0	0
FpvSecCmKmacIfCntAlertCheck_A	20641695	80	0	0
FpvSecCmKmacIfFsmCheck_A	20641695	80	0	0
FpvSecCmRegWeOnehotCheck_A	20641695	80	0	0
FpvSecCmReseedCtrlCntAlertCheck_A	20641695	80	0	0
FpvSecCmSideloadCtrlFsmCheck_A	20641695	80	0	0
GenDataWidth_A	874	874	0	0
IdDataWidth_A	874	874	0	0
IntrKnownO_A	20641695	20475249	0	0
KmacDataKnownO_A	20205337	20060731	0	0
KmacKeyKnownO_A	20641695	20475249	0	0
KmacMaskCheck_A	874	874	0	0
LfsrWidth_A	874	874	0	0
OtbnKeyKnownO_A	20641695	20475249	0	0
OutputKeyDiff_A	874	874	0	0
StageMatch_A	874	874	0	0
TlAReadyKnownO_A	20641695	20475249	0	0
TlDValidKnownO_A	20641695	20475249	0	0

AdvDataWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

AesKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20641695	20475249	0	0
T1	1734	1634	0	0
T2	6163	6110	0	0
T3	9322	9236	0	0
T4	8402	8333	0	0
T14	16215	16161	0	0
T15	5852	5791	0	0
T16	7308	7114	0	0
T17	24577	24504	0	0
T18	30563	30467	0	0
T19	13383	13324	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20641695	20475249	0	0
T1	1734	1634	0	0
T2	6163	6110	0	0
T3	9322	9236	0	0
T4	8402	8333	0	0
T14	16215	16161	0	0
T15	5852	5791	0	0
T16	7308	7114	0	0
T17	24577	24504	0	0
T18	30563	30467	0	0
T19	13383	13324	0	0

ErrCntMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

FaultCntMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

FpvSecCmCtrlCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20641695	80	0	0
T11	55244	20	0	0
T12	0	10	0	0
T13	0	20	0	0
T21	1210	0	0	0
T24	53570	0	0	0
T25	30415	0	0	0
T41	0	20	0	0
T47	9723	0	0	0
T62	36359	0	0	0
T72	0	10	0	0
T73	8829	0	0	0
T74	13471	0	0	0
T75	83426	0	0	0
T76	7077	0	0	0

FpvSecCmCtrlDataFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20641695	80	0	0
T11	55244	20	0	0
T12	0	10	0	0
T13	0	20	0	0
T21	1210	0	0	0
T24	53570	0	0	0
T25	30415	0	0	0
T41	0	20	0	0
T47	9723	0	0	0
T62	36359	0	0	0
T72	0	10	0	0
T73	8829	0	0	0
T74	13471	0	0	0
T75	83426	0	0	0
T76	7077	0	0	0

FpvSecCmCtrlMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20641695	80	0	0
T11	55244	20	0	0
T12	0	10	0	0
T13	0	20	0	0
T21	1210	0	0	0
T24	53570	0	0	0
T25	30415	0	0	0
T41	0	20	0	0
T47	9723	0	0	0
T62	36359	0	0	0
T72	0	10	0	0
T73	8829	0	0	0
T74	13471	0	0	0
T75	83426	0	0	0
T76	7077	0	0	0

FpvSecCmCtrlOpFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20641695	80	0	0
T11	55244	20	0	0
T12	0	10	0	0
T13	0	20	0	0
T21	1210	0	0	0
T24	53570	0	0	0
T25	30415	0	0	0
T41	0	20	0	0
T47	9723	0	0	0
T62	36359	0	0	0
T72	0	10	0	0
T73	8829	0	0	0
T74	13471	0	0	0
T75	83426	0	0	0
T76	7077	0	0	0

FpvSecCmKmacIfCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20641695	80	0	0
T11	55244	20	0	0
T12	0	10	0	0
T13	0	20	0	0
T21	1210	0	0	0
T24	53570	0	0	0
T25	30415	0	0	0
T41	0	20	0	0
T47	9723	0	0	0
T62	36359	0	0	0
T72	0	10	0	0
T73	8829	0	0	0
T74	13471	0	0	0
T75	83426	0	0	0
T76	7077	0	0	0

FpvSecCmKmacIfFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20641695	80	0	0
T11	55244	20	0	0
T12	0	10	0	0
T13	0	20	0	0
T21	1210	0	0	0
T24	53570	0	0	0
T25	30415	0	0	0
T41	0	20	0	0
T47	9723	0	0	0
T62	36359	0	0	0
T72	0	10	0	0
T73	8829	0	0	0
T74	13471	0	0	0
T75	83426	0	0	0
T76	7077	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20641695	80	0	0
T11	55244	20	0	0
T12	0	10	0	0
T13	0	20	0	0
T21	1210	0	0	0
T24	53570	0	0	0
T25	30415	0	0	0
T41	0	20	0	0
T47	9723	0	0	0
T62	36359	0	0	0
T72	0	10	0	0
T73	8829	0	0	0
T74	13471	0	0	0
T75	83426	0	0	0
T76	7077	0	0	0

FpvSecCmReseedCtrlCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20641695	80	0	0
T11	55244	20	0	0
T12	0	10	0	0
T13	0	20	0	0
T21	1210	0	0	0
T24	53570	0	0	0
T25	30415	0	0	0
T41	0	20	0	0
T47	9723	0	0	0
T62	36359	0	0	0
T72	0	10	0	0
T73	8829	0	0	0
T74	13471	0	0	0
T75	83426	0	0	0
T76	7077	0	0	0

FpvSecCmSideloadCtrlFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20641695	80	0	0
T11	55244	20	0	0
T12	0	10	0	0
T13	0	20	0	0
T21	1210	0	0	0
T24	53570	0	0	0
T25	30415	0	0	0
T41	0	20	0	0
T47	9723	0	0	0
T62	36359	0	0	0
T72	0	10	0	0
T73	8829	0	0	0
T74	13471	0	0	0
T75	83426	0	0	0
T76	7077	0	0	0

GenDataWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

IdDataWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

IntrKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20641695	20475249	0	0
T1	1734	1634	0	0
T2	6163	6110	0	0
T3	9322	9236	0	0
T4	8402	8333	0	0
T14	16215	16161	0	0
T15	5852	5791	0	0
T16	7308	7114	0	0
T17	24577	24504	0	0
T18	30563	30467	0	0
T19	13383	13324	0	0

KmacDataKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20205337	20060731	0	0
T1	1734	1634	0	0
T2	6163	6110	0	0
T3	9322	9236	0	0
T4	8402	8333	0	0
T14	16215	16161	0	0
T15	5852	5791	0	0
T16	7308	7114	0	0
T17	24577	24504	0	0
T18	30563	30467	0	0
T19	13383	13324	0	0

KmacKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20641695	20475249	0	0
T1	1734	1634	0	0
T2	6163	6110	0	0
T3	9322	9236	0	0
T4	8402	8333	0	0
T14	16215	16161	0	0
T15	5852	5791	0	0
T16	7308	7114	0	0
T17	24577	24504	0	0
T18	30563	30467	0	0
T19	13383	13324	0	0

KmacMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

LfsrWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OtbnKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20641695	20475249	0	0
T1	1734	1634	0	0
T2	6163	6110	0	0
T3	9322	9236	0	0
T4	8402	8333	0	0
T14	16215	16161	0	0
T15	5852	5791	0	0
T16	7308	7114	0	0
T17	24577	24504	0	0
T18	30563	30467	0	0
T19	13383	13324	0	0

OutputKeyDiff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

StageMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20641695	20475249	0	0
T1	1734	1634	0	0
T2	6163	6110	0	0
T3	9322	9236	0	0
T4	8402	8333	0	0
T14	16215	16161	0	0
T15	5852	5791	0	0
T16	7308	7114	0	0
T17	24577	24504	0	0
T18	30563	30467	0	0
T19	13383	13324	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20641695	20475249	0	0
T1	1734	1634	0	0
T2	6163	6110	0	0
T3	9322	9236	0	0
T4	8402	8333	0	0
T14	16215	16161	0	0
T15	5852	5791	0	0
T16	7308	7114	0	0
T17	24577	24504	0	0
T18	30563	30467	0	0
T19	13383	13324	0	0