Unified Coverage Report :: Module

Line Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=3,SwAccess=0,RESVAL,Mubi=0 + DW=2,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=5,RESVAL,Mubi=0 + DW=16,SwAccess=0,RESVAL,Mubi=0 + DW=32,SwAccess=0,RESVAL,Mubi=0 + DW=3,SwAccess=1,RESVAL=0,Mubi=0 + DW=2,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=1,RESVAL=0,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_start

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_control_shadowed_operation.staged_reg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_control_shadowed_operation.shadow_reg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_control_shadowed_operation.committed_reg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_control_shadowed_cdi_sel.staged_reg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_control_shadowed_cdi_sel.shadow_reg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_control_shadowed_cdi_sel.committed_reg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_control_shadowed_dest_sel.staged_reg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_control_shadowed_dest_sel.shadow_reg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_control_shadowed_dest_sel.committed_reg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sideload_clear

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_reseed_interval_regwen

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_reseed_interval_shadowed.staged_reg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_reseed_interval_shadowed.shadow_reg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_reseed_interval_shadowed.committed_reg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_0

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_1

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_2

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_3

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_4

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_5

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_6

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_7

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_0

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_1

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_2

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_3

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_4

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_5

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_6

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_7

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_salt_0

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_salt_1

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_salt_2

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_salt_3

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_salt_4

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_salt_5

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_salt_6

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_salt_7

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_version

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_regwen

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_shadowed.staged_reg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_shadowed.shadow_reg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_shadowed.committed_reg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_regwen

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.staged_reg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.shadow_reg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.committed_reg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_regwen

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_shadowed.staged_reg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_shadowed.shadow_reg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_shadowed.committed_reg

SCORE	LINE
65.24	85.71

tb.dut.u_reg.u_working_state

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_op_status

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_err_code_invalid_op

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_err_code_invalid_kmac_input

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_err_code_invalid_shadow_update

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fault_status_cmd

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fault_status_kmac_fsm

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fault_status_kmac_done

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fault_status_kmac_op

SCORE	LINE
65.24	85.71

tb.dut.u_reg.u_fault_status_kmac_out

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fault_status_regfile_intg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fault_status_shadow

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fault_status_ctrl_fsm_intg

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fault_status_ctrl_fsm_chk

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fault_status_ctrl_fsm_cnt

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fault_status_reseed_cnt

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fault_status_side_ctrl_fsm

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fault_status_side_ctrl_sel

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fault_status_key_ecc

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_debug_invalid_creator_seed

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_debug_invalid_owner_seed

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_debug_invalid_dev_id

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_debug_invalid_health_state

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_debug_invalid_key_version

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_debug_invalid_key

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_debug_invalid_digest

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00



55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T1 T2 T3 
65         1/1            assign qe = wr_en;
           Tests:       T1 T2 T3 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T1 T2 T3

Line Coverage for Module : prim_subreg ( parameter DW=32,SwAccess=6,RESVAL=0,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_0

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_1

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_2

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_3

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_4

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_5

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_6

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_7

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_0

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_1

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_2

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_3

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_4

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_5

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_6

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_7

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	70	1	1	100.00



55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T1 T2 T3 
65         1/1            assign qe = wr_en;
           Tests:       T1 T2 T3 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70         1/1              assign qs = de && we ? d : q;
           Tests:       T1 T2 T3

Cond Coverage for Module : prim_subreg ( parameter DW=32,SwAccess=6,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_7

	Total	Covered	Percent
Conditions	7	7	100.00
Logical	7	7	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       70
 EXPRESSION ((de && we) ? d : q)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T13,T14

 LINE       70
 SUB-EXPRESSION (de && we)
                 -1    -2

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T13,T14

Cond Coverage for Module : prim_subreg ( parameter DW=32,SwAccess=0,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_salt_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_salt_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_salt_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_salt_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_salt_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_salt_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_salt_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_salt_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_version

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_shadowed.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_shadowed.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_shadowed.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_shadowed.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_shadowed.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_shadowed.committed_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

Cond Coverage for Module : prim_subreg ( parameter DW=2,SwAccess=0,RESVAL,Mubi=0 + DW=2,SwAccess=3,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_control_shadowed_dest_sel.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_control_shadowed_dest_sel.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_control_shadowed_dest_sel.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_op_status

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=16,SwAccess=0,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_reseed_interval_shadowed.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_reseed_interval_shadowed.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_reseed_interval_shadowed.committed_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=3,SwAccess=0,RESVAL,Mubi=0 + DW=3,SwAccess=1,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_control_shadowed_operation.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_control_shadowed_operation.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_control_shadowed_operation.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sideload_clear

SCORE	COND
65.24	50.00

tb.dut.u_reg.u_working_state

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=5,RESVAL,Mubi=0 + DW=1,SwAccess=1,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_err_code_invalid_op

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_err_code_invalid_kmac_input

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_err_code_invalid_shadow_update

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_start

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_control_shadowed_cdi_sel.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_control_shadowed_cdi_sel.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_control_shadowed_cdi_sel.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_reseed_interval_regwen

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_regwen

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_regwen

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_regwen

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_debug_invalid_creator_seed

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_debug_invalid_owner_seed

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_debug_invalid_dev_id

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_debug_invalid_health_state

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_debug_invalid_key_version

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_debug_invalid_key

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_debug_invalid_digest

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fault_status_cmd

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fault_status_kmac_fsm

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fault_status_kmac_done

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fault_status_kmac_op

SCORE	COND
65.24	50.00

tb.dut.u_reg.u_fault_status_kmac_out

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fault_status_regfile_intg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fault_status_shadow

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fault_status_ctrl_fsm_intg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fault_status_ctrl_fsm_chk

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fault_status_ctrl_fsm_cnt

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fault_status_reseed_cnt

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fault_status_side_ctrl_fsm

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fault_status_side_ctrl_sel

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fault_status_key_ecc

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Branch Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=3,SwAccess=0,RESVAL,Mubi=0 + DW=2,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=5,RESVAL,Mubi=0 + DW=16,SwAccess=0,RESVAL,Mubi=0 + DW=32,SwAccess=0,RESVAL,Mubi=0 + DW=3,SwAccess=1,RESVAL=0,Mubi=0 + DW=2,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=1,RESVAL=0,Mubi=0 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_state

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_err_code_invalid_op

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_err_code_invalid_kmac_input

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_err_code_invalid_shadow_update

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_intr_enable

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_start

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_control_shadowed_cdi_sel.staged_reg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_control_shadowed_cdi_sel.shadow_reg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_control_shadowed_cdi_sel.committed_reg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_control_shadowed_operation.staged_reg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_control_shadowed_operation.shadow_reg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_control_shadowed_operation.committed_reg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sideload_clear

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_control_shadowed_dest_sel.staged_reg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_control_shadowed_dest_sel.shadow_reg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_control_shadowed_dest_sel.committed_reg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_reseed_interval_regwen

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_regwen

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_regwen

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_regwen

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_debug_invalid_creator_seed

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_debug_invalid_owner_seed

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_debug_invalid_dev_id

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_debug_invalid_health_state

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_debug_invalid_key_version

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_debug_invalid_key

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_debug_invalid_digest

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_reseed_interval_shadowed.staged_reg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_reseed_interval_shadowed.shadow_reg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_reseed_interval_shadowed.committed_reg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_0

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_1

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_2

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_3

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_4

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_5

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_6

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_7

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_0

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_1

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_2

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_3

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_4

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_5

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_6

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_7

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_salt_0

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_salt_1

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_salt_2

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_salt_3

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_salt_4

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_salt_5

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_salt_6

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_salt_7

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_key_version

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_shadowed.staged_reg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_shadowed.shadow_reg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_shadowed.committed_reg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.staged_reg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.shadow_reg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.committed_reg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_shadowed.staged_reg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_shadowed.shadow_reg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_shadowed.committed_reg

SCORE	BRANCH
65.24	60.00

tb.dut.u_reg.u_working_state

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_op_status

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fault_status_cmd

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fault_status_kmac_fsm

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fault_status_kmac_done

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fault_status_kmac_op

SCORE	BRANCH
65.24	60.00

tb.dut.u_reg.u_fault_status_kmac_out

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fault_status_regfile_intg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fault_status_shadow

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fault_status_ctrl_fsm_intg

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fault_status_ctrl_fsm_chk

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fault_status_ctrl_fsm_cnt

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fault_status_reseed_cnt

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fault_status_side_ctrl_fsm

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fault_status_side_ctrl_sel

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_fault_status_key_ecc

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

Branch Coverage for Module : prim_subreg ( parameter DW=32,SwAccess=6,RESVAL=0,Mubi=0 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_0

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_1

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_2

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_3

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_4

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_5

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_6

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_7

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_0

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_1

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_2

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_3

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_4

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_5

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_6

SCORE	BRANCH
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_7

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	64	2	2	100.00
TERNARY	70	2	2	100.00
IF	56	3	3	100.00



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



70             assign qs = de && we ? d : q;
                                    -1-  
                                    ==>  
                                    ==>

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_working_state	65.24	85.71	50.00			60.00
tb.dut.u_reg.u_fault_status_kmac_out	65.24	85.71	50.00			60.00
tb.dut.u_reg.u_intr_state	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_start	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_shadowed_operation.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_shadowed_operation.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_shadowed_operation.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sideload_clear	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_reseed_interval_regwen	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_reseed_interval_shadowed.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_reseed_interval_shadowed.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_reseed_interval_shadowed.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sealing_sw_binding_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sealing_sw_binding_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sealing_sw_binding_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sealing_sw_binding_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sealing_sw_binding_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sealing_sw_binding_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sealing_sw_binding_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sealing_sw_binding_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_attest_sw_binding_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_attest_sw_binding_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_attest_sw_binding_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_attest_sw_binding_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_attest_sw_binding_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_attest_sw_binding_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_attest_sw_binding_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_attest_sw_binding_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_salt_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_salt_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_salt_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_salt_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_salt_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_salt_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_salt_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_salt_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_version	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_creator_key_ver_regwen	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_owner_int_key_ver_regwen	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_owner_key_ver_regwen	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sw_share0_output_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sw_share0_output_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sw_share0_output_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sw_share0_output_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sw_share0_output_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sw_share0_output_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sw_share0_output_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sw_share0_output_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sw_share1_output_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sw_share1_output_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sw_share1_output_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sw_share1_output_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sw_share1_output_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sw_share1_output_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sw_share1_output_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sw_share1_output_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_op_status	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_err_code_invalid_op	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_err_code_invalid_kmac_input	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_err_code_invalid_shadow_update	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fault_status_cmd	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fault_status_kmac_fsm	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fault_status_kmac_done	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fault_status_kmac_op	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fault_status_regfile_intg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fault_status_shadow	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fault_status_ctrl_fsm_intg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fault_status_ctrl_fsm_chk	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fault_status_ctrl_fsm_cnt	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fault_status_reseed_cnt	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fault_status_side_ctrl_fsm	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fault_status_side_ctrl_sel	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fault_status_key_ecc	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_debug_invalid_creator_seed	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_debug_invalid_owner_seed	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_debug_invalid_dev_id	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_debug_invalid_health_state	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_debug_invalid_key_version	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_debug_invalid_key	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_debug_invalid_digest	100.00	100.00	100.00			100.00