Line Coverage for Instance : tb.dut.u_reg.u_fault_status_shadow
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T93 T86 T94
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T1 T2 T3
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_fault_status_shadow
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T93,T86,T94 |
Branch Coverage for Instance : tb.dut.u_reg.u_fault_status_shadow
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T93,T86,T94 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T93,T86,T94 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_fault_status_ctrl_fsm_intg
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T12 T13 T14
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T1 T2 T3
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_fault_status_ctrl_fsm_intg
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T12,T13,T14 |
Branch Coverage for Instance : tb.dut.u_reg.u_fault_status_ctrl_fsm_intg
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T12,T13,T14 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T12,T13,T14 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_fault_status_ctrl_fsm_chk
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T20 T9 T8
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T1 T2 T3
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_fault_status_ctrl_fsm_chk
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T9,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_fault_status_ctrl_fsm_chk
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T9,T8 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T20,T9,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_fault_status_ctrl_fsm_cnt
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T12 T13 T14
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T1 T2 T3
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_fault_status_ctrl_fsm_cnt
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T12,T13,T14 |
Branch Coverage for Instance : tb.dut.u_reg.u_fault_status_ctrl_fsm_cnt
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T12,T13,T14 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T12,T13,T14 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_fault_status_reseed_cnt
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T12 T13 T14
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T1 T2 T3
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_fault_status_reseed_cnt
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T12,T13,T14 |
Branch Coverage for Instance : tb.dut.u_reg.u_fault_status_reseed_cnt
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T12,T13,T14 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T12,T13,T14 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_fault_status_side_ctrl_fsm
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T12 T13 T14
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T1 T2 T3
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_fault_status_side_ctrl_fsm
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T12,T13,T14 |
Branch Coverage for Instance : tb.dut.u_reg.u_fault_status_side_ctrl_fsm
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T12,T13,T14 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T12,T13,T14 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_fault_status_side_ctrl_sel
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T40 T41 T42
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T1 T2 T3
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_fault_status_side_ctrl_sel
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T40,T41,T42 |
Branch Coverage for Instance : tb.dut.u_reg.u_fault_status_side_ctrl_sel
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T40,T41,T42 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T40,T41,T42 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_fault_status_key_ecc
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T71 T189 T145
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T1 T2 T3
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_fault_status_key_ecc
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T71,T189,T145 |
Branch Coverage for Instance : tb.dut.u_reg.u_fault_status_key_ecc
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T71,T189,T145 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T71,T189,T145 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_debug_invalid_creator_seed
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T5 T21 T28
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T1 T2 T3
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_debug_invalid_creator_seed
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T21,T28 |
Branch Coverage for Instance : tb.dut.u_reg.u_debug_invalid_creator_seed
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T21,T28 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T21,T28 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_debug_invalid_owner_seed
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T5 T21 T28
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T1 T2 T3
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_debug_invalid_owner_seed
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T21,T28 |
Branch Coverage for Instance : tb.dut.u_reg.u_debug_invalid_owner_seed
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T21,T28 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T21,T28 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_debug_invalid_dev_id
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T5 T21 T28
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T1 T2 T3
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_debug_invalid_dev_id
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T21,T28 |
Branch Coverage for Instance : tb.dut.u_reg.u_debug_invalid_dev_id
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T21,T28 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T21,T28 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_debug_invalid_health_state
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T5 T21 T28
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T1 T2 T3
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_debug_invalid_health_state
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T21,T28 |
Branch Coverage for Instance : tb.dut.u_reg.u_debug_invalid_health_state
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T21,T28 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T21,T28 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_debug_invalid_key_version
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T5 T21 T28
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T1 T2 T3
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_debug_invalid_key_version
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T21,T28 |
Branch Coverage for Instance : tb.dut.u_reg.u_debug_invalid_key_version
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T21,T28 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T21,T28 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_debug_invalid_key
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T5 T21 T28
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T1 T2 T3
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_debug_invalid_key
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T21,T28 |
Branch Coverage for Instance : tb.dut.u_reg.u_debug_invalid_key
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T21,T28 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T21,T28 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_debug_invalid_digest
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
57 1/1 q <= RESVAL;
Tests: T1 T2 T3
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T3
59 1/1 q <= wr_data;
Tests: T5 T21 T28
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T1 T2 T3
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_debug_invalid_digest
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T21,T28 |
Branch Coverage for Instance : tb.dut.u_reg.u_debug_invalid_digest
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T21,T28 |
| 0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T21,T28 |
| 0 |
0 |
Covered |
T1,T2,T3 |