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Module Instance : tb.dut.u_reg.u_max_owner_key_ver_shadowed.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.04 100.00 96.15 100.00 100.00 u_max_owner_key_ver_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_max_owner_key_ver_shadowed.staged_reg.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_max_owner_key_ver_shadowed.shadow_reg.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_max_owner_key_ver_shadowed.committed_reg.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_share0_output_0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sw_share0_output_0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_share0_output_1.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sw_share0_output_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_share0_output_2.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sw_share0_output_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_share0_output_3.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sw_share0_output_3


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_share0_output_4.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sw_share0_output_4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_share0_output_5.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sw_share0_output_5


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.u_reg.u_sw_share0_output_6.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sw_share0_output_6


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.u_reg.u_sw_share0_output_7.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sw_share0_output_7


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.u_reg.u_sw_share1_output_0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sw_share1_output_0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_share1_output_1.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sw_share1_output_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_share1_output_2.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sw_share1_output_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.u_reg.u_sw_share1_output_3.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sw_share1_output_3


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_share1_output_4.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sw_share1_output_4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_share1_output_5.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sw_share1_output_5


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_share1_output_6.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sw_share1_output_6


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg.u_max_owner_key_ver_shadowed.wr_en_data_arb
tb.dut.u_reg.u_max_owner_key_ver_shadowed.staged_reg.wr_en_data_arb
tb.dut.u_reg.u_max_owner_key_ver_shadowed.shadow_reg.wr_en_data_arb
tb.dut.u_reg.u_max_owner_key_ver_shadowed.committed_reg.wr_en_data_arb
tb.dut.u_reg.u_sw_share0_output_0.wr_en_data_arb
tb.dut.u_reg.u_sw_share0_output_1.wr_en_data_arb
tb.dut.u_reg.u_sw_share0_output_2.wr_en_data_arb
tb.dut.u_reg.u_sw_share0_output_3.wr_en_data_arb
tb.dut.u_reg.u_sw_share0_output_4.wr_en_data_arb
tb.dut.u_reg.u_sw_share0_output_5.wr_en_data_arb
tb.dut.u_reg.u_sw_share0_output_6.wr_en_data_arb
tb.dut.u_reg.u_sw_share0_output_7.wr_en_data_arb
tb.dut.u_reg.u_sw_share1_output_0.wr_en_data_arb
tb.dut.u_reg.u_sw_share1_output_1.wr_en_data_arb
tb.dut.u_reg.u_sw_share1_output_2.wr_en_data_arb
tb.dut.u_reg.u_sw_share1_output_3.wr_en_data_arb
tb.dut.u_reg.u_sw_share1_output_4.wr_en_data_arb
tb.dut.u_reg.u_sw_share1_output_5.wr_en_data_arb
tb.dut.u_reg.u_sw_share1_output_6.wr_en_data_arb
Line Coverage for Instance : tb.dut.u_reg.u_max_owner_key_ver_shadowed.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T2 T3 T17  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_max_owner_key_ver_shadowed.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T3,T17

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T17

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T17

Branch Coverage for Instance : tb.dut.u_reg.u_max_owner_key_ver_shadowed.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T17
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_max_owner_key_ver_shadowed.staged_reg.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T2 T3 T17  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T2 T3 T17  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_max_owner_key_ver_shadowed.staged_reg.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T3,T17

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T17

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T17

Branch Coverage for Instance : tb.dut.u_reg.u_max_owner_key_ver_shadowed.staged_reg.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T17
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_max_owner_key_ver_shadowed.shadow_reg.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T2 T3 T17  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_max_owner_key_ver_shadowed.shadow_reg.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T3,T17

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T17

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T17

Branch Coverage for Instance : tb.dut.u_reg.u_max_owner_key_ver_shadowed.shadow_reg.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T17
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_max_owner_key_ver_shadowed.committed_reg.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T2 T3 T17  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T2 T3 T17  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_max_owner_key_ver_shadowed.committed_reg.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T3,T17

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T17

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T17

Branch Coverage for Instance : tb.dut.u_reg.u_max_owner_key_ver_shadowed.committed_reg.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T17
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16800

139 // WARN: we signal is actually read signal not write enable. 140 1/1 assign wr_en = we | de; Tests: T1 T2 T3  141 if (Mubi) begin : gen_mubi 142 if (DW == 4) begin : gen_mubi4 143 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 144 (we ? prim_mubi_pkg::MuBi4False : 145 prim_mubi_pkg::MuBi4True)); 146 end else if (DW == 8) begin : gen_mubi8 147 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 148 (we ? prim_mubi_pkg::MuBi8False : 149 prim_mubi_pkg::MuBi8True)); 150 end else if (DW == 12) begin : gen_mubi12 151 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 152 (we ? prim_mubi_pkg::MuBi12False : 153 prim_mubi_pkg::MuBi12True)); 154 end else if (DW == 16) begin : gen_mubi16 155 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 156 (we ? prim_mubi_pkg::mubi16_t'(wd) : 157 prim_mubi_pkg::MuBi16True)); 158 end else begin : gen_invalid_mubi 159 $error("%m: Invalid width for MuBi"); 160 end 161 end else begin : gen_non_mubi 162 1/1 assign wr_data = (de ? d : q) & (we ? '0 : '1); Tests: T1 T2 T3  163 end 164 // Unused wd - Prevent lint errors. 165 logic [DW-1:0] unused_wd; 166 //VCS coverage off 167 // pragma coverage off 168 unreachable assign unused_wd = wd;

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_0.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       140
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_1.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16800

139 // WARN: we signal is actually read signal not write enable. 140 1/1 assign wr_en = we | de; Tests: T1 T2 T3  141 if (Mubi) begin : gen_mubi 142 if (DW == 4) begin : gen_mubi4 143 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 144 (we ? prim_mubi_pkg::MuBi4False : 145 prim_mubi_pkg::MuBi4True)); 146 end else if (DW == 8) begin : gen_mubi8 147 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 148 (we ? prim_mubi_pkg::MuBi8False : 149 prim_mubi_pkg::MuBi8True)); 150 end else if (DW == 12) begin : gen_mubi12 151 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 152 (we ? prim_mubi_pkg::MuBi12False : 153 prim_mubi_pkg::MuBi12True)); 154 end else if (DW == 16) begin : gen_mubi16 155 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 156 (we ? prim_mubi_pkg::mubi16_t'(wd) : 157 prim_mubi_pkg::MuBi16True)); 158 end else begin : gen_invalid_mubi 159 $error("%m: Invalid width for MuBi"); 160 end 161 end else begin : gen_non_mubi 162 1/1 assign wr_data = (de ? d : q) & (we ? '0 : '1); Tests: T1 T2 T3  163 end 164 // Unused wd - Prevent lint errors. 165 logic [DW-1:0] unused_wd; 166 //VCS coverage off 167 // pragma coverage off 168 unreachable assign unused_wd = wd;

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_1.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       140
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_2.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16800

139 // WARN: we signal is actually read signal not write enable. 140 1/1 assign wr_en = we | de; Tests: T1 T2 T3  141 if (Mubi) begin : gen_mubi 142 if (DW == 4) begin : gen_mubi4 143 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 144 (we ? prim_mubi_pkg::MuBi4False : 145 prim_mubi_pkg::MuBi4True)); 146 end else if (DW == 8) begin : gen_mubi8 147 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 148 (we ? prim_mubi_pkg::MuBi8False : 149 prim_mubi_pkg::MuBi8True)); 150 end else if (DW == 12) begin : gen_mubi12 151 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 152 (we ? prim_mubi_pkg::MuBi12False : 153 prim_mubi_pkg::MuBi12True)); 154 end else if (DW == 16) begin : gen_mubi16 155 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 156 (we ? prim_mubi_pkg::mubi16_t'(wd) : 157 prim_mubi_pkg::MuBi16True)); 158 end else begin : gen_invalid_mubi 159 $error("%m: Invalid width for MuBi"); 160 end 161 end else begin : gen_non_mubi 162 1/1 assign wr_data = (de ? d : q) & (we ? '0 : '1); Tests: T1 T2 T3  163 end 164 // Unused wd - Prevent lint errors. 165 logic [DW-1:0] unused_wd; 166 //VCS coverage off 167 // pragma coverage off 168 unreachable assign unused_wd = wd;

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_2.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       140
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_3.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16800

139 // WARN: we signal is actually read signal not write enable. 140 1/1 assign wr_en = we | de; Tests: T1 T2 T3  141 if (Mubi) begin : gen_mubi 142 if (DW == 4) begin : gen_mubi4 143 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 144 (we ? prim_mubi_pkg::MuBi4False : 145 prim_mubi_pkg::MuBi4True)); 146 end else if (DW == 8) begin : gen_mubi8 147 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 148 (we ? prim_mubi_pkg::MuBi8False : 149 prim_mubi_pkg::MuBi8True)); 150 end else if (DW == 12) begin : gen_mubi12 151 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 152 (we ? prim_mubi_pkg::MuBi12False : 153 prim_mubi_pkg::MuBi12True)); 154 end else if (DW == 16) begin : gen_mubi16 155 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 156 (we ? prim_mubi_pkg::mubi16_t'(wd) : 157 prim_mubi_pkg::MuBi16True)); 158 end else begin : gen_invalid_mubi 159 $error("%m: Invalid width for MuBi"); 160 end 161 end else begin : gen_non_mubi 162 1/1 assign wr_data = (de ? d : q) & (we ? '0 : '1); Tests: T1 T2 T3  163 end 164 // Unused wd - Prevent lint errors. 165 logic [DW-1:0] unused_wd; 166 //VCS coverage off 167 // pragma coverage off 168 unreachable assign unused_wd = wd;

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_3.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       140
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_4.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16800

139 // WARN: we signal is actually read signal not write enable. 140 1/1 assign wr_en = we | de; Tests: T1 T2 T3  141 if (Mubi) begin : gen_mubi 142 if (DW == 4) begin : gen_mubi4 143 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 144 (we ? prim_mubi_pkg::MuBi4False : 145 prim_mubi_pkg::MuBi4True)); 146 end else if (DW == 8) begin : gen_mubi8 147 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 148 (we ? prim_mubi_pkg::MuBi8False : 149 prim_mubi_pkg::MuBi8True)); 150 end else if (DW == 12) begin : gen_mubi12 151 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 152 (we ? prim_mubi_pkg::MuBi12False : 153 prim_mubi_pkg::MuBi12True)); 154 end else if (DW == 16) begin : gen_mubi16 155 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 156 (we ? prim_mubi_pkg::mubi16_t'(wd) : 157 prim_mubi_pkg::MuBi16True)); 158 end else begin : gen_invalid_mubi 159 $error("%m: Invalid width for MuBi"); 160 end 161 end else begin : gen_non_mubi 162 1/1 assign wr_data = (de ? d : q) & (we ? '0 : '1); Tests: T1 T2 T3  163 end 164 // Unused wd - Prevent lint errors. 165 logic [DW-1:0] unused_wd; 166 //VCS coverage off 167 // pragma coverage off 168 unreachable assign unused_wd = wd;

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_4.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       140
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_5.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16800

139 // WARN: we signal is actually read signal not write enable. 140 1/1 assign wr_en = we | de; Tests: T1 T2 T3  141 if (Mubi) begin : gen_mubi 142 if (DW == 4) begin : gen_mubi4 143 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 144 (we ? prim_mubi_pkg::MuBi4False : 145 prim_mubi_pkg::MuBi4True)); 146 end else if (DW == 8) begin : gen_mubi8 147 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 148 (we ? prim_mubi_pkg::MuBi8False : 149 prim_mubi_pkg::MuBi8True)); 150 end else if (DW == 12) begin : gen_mubi12 151 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 152 (we ? prim_mubi_pkg::MuBi12False : 153 prim_mubi_pkg::MuBi12True)); 154 end else if (DW == 16) begin : gen_mubi16 155 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 156 (we ? prim_mubi_pkg::mubi16_t'(wd) : 157 prim_mubi_pkg::MuBi16True)); 158 end else begin : gen_invalid_mubi 159 $error("%m: Invalid width for MuBi"); 160 end 161 end else begin : gen_non_mubi 162 1/1 assign wr_data = (de ? d : q) & (we ? '0 : '1); Tests: T1 T2 T3  163 end 164 // Unused wd - Prevent lint errors. 165 logic [DW-1:0] unused_wd; 166 //VCS coverage off 167 // pragma coverage off 168 unreachable assign unused_wd = wd;

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_5.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       140
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_6.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16800

139 // WARN: we signal is actually read signal not write enable. 140 1/1 assign wr_en = we | de; Tests: T1 T2 T3  141 if (Mubi) begin : gen_mubi 142 if (DW == 4) begin : gen_mubi4 143 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 144 (we ? prim_mubi_pkg::MuBi4False : 145 prim_mubi_pkg::MuBi4True)); 146 end else if (DW == 8) begin : gen_mubi8 147 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 148 (we ? prim_mubi_pkg::MuBi8False : 149 prim_mubi_pkg::MuBi8True)); 150 end else if (DW == 12) begin : gen_mubi12 151 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 152 (we ? prim_mubi_pkg::MuBi12False : 153 prim_mubi_pkg::MuBi12True)); 154 end else if (DW == 16) begin : gen_mubi16 155 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 156 (we ? prim_mubi_pkg::mubi16_t'(wd) : 157 prim_mubi_pkg::MuBi16True)); 158 end else begin : gen_invalid_mubi 159 $error("%m: Invalid width for MuBi"); 160 end 161 end else begin : gen_non_mubi 162 1/1 assign wr_data = (de ? d : q) & (we ? '0 : '1); Tests: T1 T2 T3  163 end 164 // Unused wd - Prevent lint errors. 165 logic [DW-1:0] unused_wd; 166 //VCS coverage off 167 // pragma coverage off 168 unreachable assign unused_wd = wd;

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_6.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       140
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_7.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16800

139 // WARN: we signal is actually read signal not write enable. 140 1/1 assign wr_en = we | de; Tests: T1 T2 T3  141 if (Mubi) begin : gen_mubi 142 if (DW == 4) begin : gen_mubi4 143 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 144 (we ? prim_mubi_pkg::MuBi4False : 145 prim_mubi_pkg::MuBi4True)); 146 end else if (DW == 8) begin : gen_mubi8 147 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 148 (we ? prim_mubi_pkg::MuBi8False : 149 prim_mubi_pkg::MuBi8True)); 150 end else if (DW == 12) begin : gen_mubi12 151 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 152 (we ? prim_mubi_pkg::MuBi12False : 153 prim_mubi_pkg::MuBi12True)); 154 end else if (DW == 16) begin : gen_mubi16 155 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 156 (we ? prim_mubi_pkg::mubi16_t'(wd) : 157 prim_mubi_pkg::MuBi16True)); 158 end else begin : gen_invalid_mubi 159 $error("%m: Invalid width for MuBi"); 160 end 161 end else begin : gen_non_mubi 162 1/1 assign wr_data = (de ? d : q) & (we ? '0 : '1); Tests: T1 T2 T3  163 end 164 // Unused wd - Prevent lint errors. 165 logic [DW-1:0] unused_wd; 166 //VCS coverage off 167 // pragma coverage off 168 unreachable assign unused_wd = wd;

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_7.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       140
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16800

139 // WARN: we signal is actually read signal not write enable. 140 1/1 assign wr_en = we | de; Tests: T1 T2 T3  141 if (Mubi) begin : gen_mubi 142 if (DW == 4) begin : gen_mubi4 143 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 144 (we ? prim_mubi_pkg::MuBi4False : 145 prim_mubi_pkg::MuBi4True)); 146 end else if (DW == 8) begin : gen_mubi8 147 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 148 (we ? prim_mubi_pkg::MuBi8False : 149 prim_mubi_pkg::MuBi8True)); 150 end else if (DW == 12) begin : gen_mubi12 151 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 152 (we ? prim_mubi_pkg::MuBi12False : 153 prim_mubi_pkg::MuBi12True)); 154 end else if (DW == 16) begin : gen_mubi16 155 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 156 (we ? prim_mubi_pkg::mubi16_t'(wd) : 157 prim_mubi_pkg::MuBi16True)); 158 end else begin : gen_invalid_mubi 159 $error("%m: Invalid width for MuBi"); 160 end 161 end else begin : gen_non_mubi 162 1/1 assign wr_data = (de ? d : q) & (we ? '0 : '1); Tests: T1 T2 T3  163 end 164 // Unused wd - Prevent lint errors. 165 logic [DW-1:0] unused_wd; 166 //VCS coverage off 167 // pragma coverage off 168 unreachable assign unused_wd = wd;

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_0.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       140
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_1.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16800

139 // WARN: we signal is actually read signal not write enable. 140 1/1 assign wr_en = we | de; Tests: T1 T2 T3  141 if (Mubi) begin : gen_mubi 142 if (DW == 4) begin : gen_mubi4 143 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 144 (we ? prim_mubi_pkg::MuBi4False : 145 prim_mubi_pkg::MuBi4True)); 146 end else if (DW == 8) begin : gen_mubi8 147 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 148 (we ? prim_mubi_pkg::MuBi8False : 149 prim_mubi_pkg::MuBi8True)); 150 end else if (DW == 12) begin : gen_mubi12 151 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 152 (we ? prim_mubi_pkg::MuBi12False : 153 prim_mubi_pkg::MuBi12True)); 154 end else if (DW == 16) begin : gen_mubi16 155 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 156 (we ? prim_mubi_pkg::mubi16_t'(wd) : 157 prim_mubi_pkg::MuBi16True)); 158 end else begin : gen_invalid_mubi 159 $error("%m: Invalid width for MuBi"); 160 end 161 end else begin : gen_non_mubi 162 1/1 assign wr_data = (de ? d : q) & (we ? '0 : '1); Tests: T1 T2 T3  163 end 164 // Unused wd - Prevent lint errors. 165 logic [DW-1:0] unused_wd; 166 //VCS coverage off 167 // pragma coverage off 168 unreachable assign unused_wd = wd;

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_1.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       140
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_2.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16800

139 // WARN: we signal is actually read signal not write enable. 140 1/1 assign wr_en = we | de; Tests: T1 T2 T3  141 if (Mubi) begin : gen_mubi 142 if (DW == 4) begin : gen_mubi4 143 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 144 (we ? prim_mubi_pkg::MuBi4False : 145 prim_mubi_pkg::MuBi4True)); 146 end else if (DW == 8) begin : gen_mubi8 147 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 148 (we ? prim_mubi_pkg::MuBi8False : 149 prim_mubi_pkg::MuBi8True)); 150 end else if (DW == 12) begin : gen_mubi12 151 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 152 (we ? prim_mubi_pkg::MuBi12False : 153 prim_mubi_pkg::MuBi12True)); 154 end else if (DW == 16) begin : gen_mubi16 155 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 156 (we ? prim_mubi_pkg::mubi16_t'(wd) : 157 prim_mubi_pkg::MuBi16True)); 158 end else begin : gen_invalid_mubi 159 $error("%m: Invalid width for MuBi"); 160 end 161 end else begin : gen_non_mubi 162 1/1 assign wr_data = (de ? d : q) & (we ? '0 : '1); Tests: T1 T2 T3  163 end 164 // Unused wd - Prevent lint errors. 165 logic [DW-1:0] unused_wd; 166 //VCS coverage off 167 // pragma coverage off 168 unreachable assign unused_wd = wd;

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_2.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       140
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_3.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16800

139 // WARN: we signal is actually read signal not write enable. 140 1/1 assign wr_en = we | de; Tests: T1 T2 T3  141 if (Mubi) begin : gen_mubi 142 if (DW == 4) begin : gen_mubi4 143 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 144 (we ? prim_mubi_pkg::MuBi4False : 145 prim_mubi_pkg::MuBi4True)); 146 end else if (DW == 8) begin : gen_mubi8 147 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 148 (we ? prim_mubi_pkg::MuBi8False : 149 prim_mubi_pkg::MuBi8True)); 150 end else if (DW == 12) begin : gen_mubi12 151 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 152 (we ? prim_mubi_pkg::MuBi12False : 153 prim_mubi_pkg::MuBi12True)); 154 end else if (DW == 16) begin : gen_mubi16 155 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 156 (we ? prim_mubi_pkg::mubi16_t'(wd) : 157 prim_mubi_pkg::MuBi16True)); 158 end else begin : gen_invalid_mubi 159 $error("%m: Invalid width for MuBi"); 160 end 161 end else begin : gen_non_mubi 162 1/1 assign wr_data = (de ? d : q) & (we ? '0 : '1); Tests: T1 T2 T3  163 end 164 // Unused wd - Prevent lint errors. 165 logic [DW-1:0] unused_wd; 166 //VCS coverage off 167 // pragma coverage off 168 unreachable assign unused_wd = wd;

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_3.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       140
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_4.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16800

139 // WARN: we signal is actually read signal not write enable. 140 1/1 assign wr_en = we | de; Tests: T1 T2 T3  141 if (Mubi) begin : gen_mubi 142 if (DW == 4) begin : gen_mubi4 143 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 144 (we ? prim_mubi_pkg::MuBi4False : 145 prim_mubi_pkg::MuBi4True)); 146 end else if (DW == 8) begin : gen_mubi8 147 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 148 (we ? prim_mubi_pkg::MuBi8False : 149 prim_mubi_pkg::MuBi8True)); 150 end else if (DW == 12) begin : gen_mubi12 151 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 152 (we ? prim_mubi_pkg::MuBi12False : 153 prim_mubi_pkg::MuBi12True)); 154 end else if (DW == 16) begin : gen_mubi16 155 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 156 (we ? prim_mubi_pkg::mubi16_t'(wd) : 157 prim_mubi_pkg::MuBi16True)); 158 end else begin : gen_invalid_mubi 159 $error("%m: Invalid width for MuBi"); 160 end 161 end else begin : gen_non_mubi 162 1/1 assign wr_data = (de ? d : q) & (we ? '0 : '1); Tests: T1 T2 T3  163 end 164 // Unused wd - Prevent lint errors. 165 logic [DW-1:0] unused_wd; 166 //VCS coverage off 167 // pragma coverage off 168 unreachable assign unused_wd = wd;

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_4.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       140
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_5.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16800

139 // WARN: we signal is actually read signal not write enable. 140 1/1 assign wr_en = we | de; Tests: T1 T2 T3  141 if (Mubi) begin : gen_mubi 142 if (DW == 4) begin : gen_mubi4 143 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 144 (we ? prim_mubi_pkg::MuBi4False : 145 prim_mubi_pkg::MuBi4True)); 146 end else if (DW == 8) begin : gen_mubi8 147 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 148 (we ? prim_mubi_pkg::MuBi8False : 149 prim_mubi_pkg::MuBi8True)); 150 end else if (DW == 12) begin : gen_mubi12 151 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 152 (we ? prim_mubi_pkg::MuBi12False : 153 prim_mubi_pkg::MuBi12True)); 154 end else if (DW == 16) begin : gen_mubi16 155 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 156 (we ? prim_mubi_pkg::mubi16_t'(wd) : 157 prim_mubi_pkg::MuBi16True)); 158 end else begin : gen_invalid_mubi 159 $error("%m: Invalid width for MuBi"); 160 end 161 end else begin : gen_non_mubi 162 1/1 assign wr_data = (de ? d : q) & (we ? '0 : '1); Tests: T1 T2 T3  163 end 164 // Unused wd - Prevent lint errors. 165 logic [DW-1:0] unused_wd; 166 //VCS coverage off 167 // pragma coverage off 168 unreachable assign unused_wd = wd;

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_5.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       140
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_6.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16800

139 // WARN: we signal is actually read signal not write enable. 140 1/1 assign wr_en = we | de; Tests: T1 T2 T3  141 if (Mubi) begin : gen_mubi 142 if (DW == 4) begin : gen_mubi4 143 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 144 (we ? prim_mubi_pkg::MuBi4False : 145 prim_mubi_pkg::MuBi4True)); 146 end else if (DW == 8) begin : gen_mubi8 147 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 148 (we ? prim_mubi_pkg::MuBi8False : 149 prim_mubi_pkg::MuBi8True)); 150 end else if (DW == 12) begin : gen_mubi12 151 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 152 (we ? prim_mubi_pkg::MuBi12False : 153 prim_mubi_pkg::MuBi12True)); 154 end else if (DW == 16) begin : gen_mubi16 155 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 156 (we ? prim_mubi_pkg::mubi16_t'(wd) : 157 prim_mubi_pkg::MuBi16True)); 158 end else begin : gen_invalid_mubi 159 $error("%m: Invalid width for MuBi"); 160 end 161 end else begin : gen_non_mubi 162 1/1 assign wr_data = (de ? d : q) & (we ? '0 : '1); Tests: T1 T2 T3  163 end 164 // Unused wd - Prevent lint errors. 165 logic [DW-1:0] unused_wd; 166 //VCS coverage off 167 // pragma coverage off 168 unreachable assign unused_wd = wd;

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_6.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       140
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%