Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

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Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	14	35	71.43

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	13	22	62.86	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	46	1			T116	1		T47	1		T138	1
auto[OpGenId]	12	1			T28	1		T31	1		T29	1
auto[OpGenSwOut]	21	1			T90	1		T9	1		T218	1
auto[OpGenHwOut]	22	1			T5	1		T8	1		T38	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1743	1			T11	90		T27	1		T57	1
auto[StInit]	89	1			T116	1		T27	1		T57	1
auto[StCreatorRootKey]	51	1			T48	1		T134	1		T50	1
auto[StOwnerIntKey]	61	1			T37	1		T8	1		T41	1
auto[StOwnerKey]	39	1			T15	1		T18	1		T21	1
auto[StDisabled]	501	1			T30	1		T27	3		T57	4
auto[StInvalid]	49	1			T35	1		T36	1		T111	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3523

1

T1

1

T2

1

T3

1

auto[1]

101

1

T116

1

T5

1

T8

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1730	1			T11	90		T27	1		T57	1
auto[StReset]	auto[1]	13	1			T38	1		T138	1		T28	1
auto[StInit]	auto[0]	48	1			T27	1		T57	1		T48	1
auto[StInit]	auto[1]	41	1			T116	1		T5	1		T47	1
auto[StCreatorRootKey]	auto[0]	38	1			T48	1		T134	1		T50	1
auto[StCreatorRootKey]	auto[1]	13	1			T31	1		T6	1		T218	1
auto[StOwnerIntKey]	auto[0]	48	1			T37	1		T41	1		T128	1
auto[StOwnerIntKey]	auto[1]	13	1			T8	1		T90	1		T52	1
auto[StOwnerKey]	auto[0]	30	1			T15	1		T18	1		T21	1
auto[StOwnerKey]	auto[1]	9	1			T219	1		T220	1		T221	1
auto[StDisabled]	auto[0]	489	1			T30	1		T27	3		T57	4
auto[StDisabled]	auto[1]	12	1			T50	1		T132	1		T6	1
auto[StInvalid]	auto[0]	49	1			T35	1		T36	1		T111	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	13	22	62.86	13

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenSwOut]]	0	1	1
[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey]]	[auto[OpGenId]]	0	1	1
[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerKey] , auto[StDisabled]]	[auto[OpDisable]]	--	--	2

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	9	1			T138	1		T132	1		T32	1
auto[StReset]	auto[OpGenId]	2	1			T28	1		T29	1		-	-
auto[StReset]	auto[OpGenHwOut]	2	1			T38	1		T23	1		-	-
auto[StInit]	auto[OpAdvance]	14	1			T116	1		T47	1		T51	1
auto[StInit]	auto[OpGenId]	6	1			T129	1		T222	1		T214	1
auto[StInit]	auto[OpGenSwOut]	10	1			T223	1		T224	1		T225	1
auto[StInit]	auto[OpGenHwOut]	11	1			T5	1		T226	1		T149	2
auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T6	1		T227	1		T153	1
auto[StCreatorRootKey]	auto[OpGenId]	1	1			T31	1		-	-		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T218	1		T228	1		T131	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	1	1			T196	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T52	1		T229	1		T230	1
auto[StOwnerIntKey]	auto[OpGenSwOut]	2	1			T90	1		T9	1		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	3	1			T8	1		T7	1		T231	1
auto[StOwnerKey]	auto[OpAdvance]	4	1			T219	1		T221	1		T232	1
auto[StOwnerKey]	auto[OpGenId]	1	1			T233	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T220	1		T234	1		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	2	1			T235	1		T236	1		-	-
auto[StDisabled]	auto[OpAdvance]	5	1			T50	1		T132	1		T237	1
auto[StDisabled]	auto[OpGenId]	2	1			T225	1		T238	1		-	-
auto[StDisabled]	auto[OpGenSwOut]	2	1			T177	1		T214	1		-	-
auto[StDisabled]	auto[OpGenHwOut]	3	1			T6	1		T239	1		T240	1