Design Module List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.16 99.52 97.60 99.95 89.58 98.33 97.97


Total modules in report: 52
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_packer_fifo 73.33 100.00 93.33 100.00 0.00
keymgr_data_en_state 83.78 96.67 33.33 100.00 88.89 100.00
keymgr_kmac_if 87.66 100.00 90.91 54.55 92.86 100.00
tlul_rsp_intg_gen 91.67 83.33 100.00
tlul_rsp_intg_gen 100.00 100.00
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 ) 66.67 66.67
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 ) 100.00 100.00
keymgr_err 94.81 100.00 84.44 100.00
keymgr_sideload_key 95.83 100.00 87.50 100.00
keymgr_sideload_key 100.00 100.00 100.00
keymgr_sideload_key ( parameter Width=256,EntropyCopies=8 ) 87.50 87.50
keymgr_sideload_key ( parameter Width=384,EntropyCopies=12 ) 87.50 87.50
prim_sync_reqack 95.83 100.00 83.33 100.00 100.00
keymgr_reseed_ctrl 97.78 100.00 93.33 100.00
tlul_assert 97.90 97.90
keymgr 98.05 96.00 98.36 99.96 95.92 100.00
prim_edn_req 98.08 100.00 92.31 100.00 100.00
tlul_adapter_reg 98.98 100.00 95.92 100.00 100.00
prim_subreg_shadow 99.04 100.00 96.15 100.00 100.00
prim_secded_inv_72_64_dec 99.32 99.32
keymgr_ctrl 99.62 100.00 98.11 100.00 100.00 100.00
keymgr_reg_top 99.80 100.00 99.22 100.00 100.00
prim_lc_sync 100.00 100.00 100.00
tlul_data_integ_dec 100.00 100.00
prim_count 100.00 100.00
prim_count ( parameter Width=16,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 ) 100.00 100.00
prim_count ( parameter Width=3,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 ) 100.00 100.00
prim_count ( parameter Width=5,ResetValue=31,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 ) 100.00 100.00
prim_sparse_fsm_flop 100.00 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
prim_alert_sender 100.00 100.00
prim_mubi4_sender 100.00 100.00 100.00
keymgr_sideload_key_ctrl 100.00 100.00 100.00 100.00 100.00 100.00
prim_msb_extend 100.00 100.00 100.00
prim_msb_extend 100.00 100.00
prim_msb_extend ( parameter InWidth=128,OutWidth=256,WidthDiff=128 ) 100.00 100.00
prim_msb_extend ( parameter InWidth=256,OutWidth=256,WidthDiff=0 ) 100.00 100.00
prim_onehot_check 100.00 100.00
prim_subreg 100.00 100.00 100.00 100.00
prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=5,RESVAL,Mubi=0 + DW=1,SwAccess=1,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=3,SwAccess=0,RESVAL,Mubi=0 + DW=2,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=5,RESVAL,Mubi=0 + DW=16,SwAccess=0,RESVAL,Mubi=0 + DW=32,SwAccess=0,RESVAL,Mubi=0 + DW=3,SwAccess=1,RESVAL=0,Mubi=0 + DW=2,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=1,RESVAL=0,Mubi=0 ) 100.00 100.00 100.00
prim_subreg ( parameter DW=16,SwAccess=0,RESVAL,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=2,SwAccess=0,RESVAL,Mubi=0 + DW=2,SwAccess=3,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=3,SwAccess=0,RESVAL,Mubi=0 + DW=3,SwAccess=1,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=32,SwAccess=0,RESVAL,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=32,SwAccess=6,RESVAL=0,Mubi=0 ) 100.00 100.00 100.00 100.00
prim_secded_inv_39_32_dec 100.00 100.00
prim_generic_buf 100.00 100.00
prim_intr_hw 100.00 100.00 100.00 100.00 100.00
prim_subreg_arb 100.00 100.00 100.00 100.00
prim_subreg_arb 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=3,SwAccess=0,Mubi=0 + DW=2,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=32,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 + DW=2,SwAccess=3,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 ) 100.00 100.00 100.00
prim_subreg_arb ( parameter DW=16,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=2,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=3,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=3,SwAccess=1,Mubi=0 + DW=1,SwAccess=1,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=32,SwAccess=6,Mubi=0 ) 100.00 100.00 100.00
keymgr_op_state_ctrl 100.00 100.00 100.00 100.00 100.00 100.00
keymgr_csr_assert_fpv 100.00 100.00
prim_subreg_ext 100.00 100.00
keymgr_input_checks 100.00 100.00
prim_secded_inv_39_32_enc 100.00 100.00
tlul_err 100.00 100.00 100.00 100.00 100.00
prim_lfsr 100.00 100.00
prim_secded_inv_64_57_enc 100.00 100.00
prim_secded_inv_64_57_dec 100.00 100.00
prim_sync_reqack_data 100.00 100.00 100.00
prim_generic_flop 100.00 100.00 100.00
keymgr_cfg_en 100.00 100.00 100.00 100.00
prim_mubi4_sync 100.00 100.00 100.00
prim_mubi4_sync 100.00 100.00
prim_mubi4_sync ( parameter NumCopies=2,AsyncOn=0,StabilityCheck=0,ResetValue=9 ) 100.00 100.00
prim_mubi4_sync ( parameter NumCopies=3,AsyncOn=0,StabilityCheck=0,ResetValue=9 ) 100.00 100.00
tlul_data_integ_enc
prim_reg_we_check
prim_buf
prim_generic_flop_2sync
prim_flop
prim_flop_2sync
tb
prim_sec_anchor_buf
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