Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5138

1

T1

6

T3

10

T14

9

auto[1]

598

1

T44

3

T45

3

T113

5

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5138

1

T1

6

T3

10

T14

9

auto[1]

598

1

T44

3

T45

3

T113

5

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5143

1

T1

5

T3

10

T14

6

auto[1]

593

1

T1

1

T14

3

T67

2

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5143

1

T1

5

T3

10

T14

6

auto[1]

593

1

T1

1

T14

3

T67

2

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	474	1			T3	5		T15	1		T16	1
auto[OpGenId]	1281	1			T1	1		T3	4		T19	1
auto[OpGenSwOut]	1239	1			T1	4		T3	1		T15	1
auto[OpGenHwOut]	2665	1			T1	1		T14	9		T16	3
auto[OpDisable]	77	1			T57	1		T241	1		T49	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	474	1			T3	5		T15	1		T16	1
auto[OpGenId]	1281	1			T1	1		T3	4		T19	1
auto[OpGenSwOut]	1239	1			T1	4		T3	1		T15	1
auto[OpGenHwOut]	2665	1			T1	1		T14	9		T16	3
auto[OpDisable]	77	1			T57	1		T241	1		T49	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5191

1

T1

6

T3

9

T14

9

auto[1]

545

1

T3

1

T19

3

T30

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5191

1

T1

6

T3

9

T14

9

auto[1]

545

1

T3

1

T19

3

T30

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5431

1

T1

6

T3

5

T14

9

auto[1]

305

1

T3

5

T86

3

T87

3

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1946	1			T1	1		T3	4		T14	2
auto[1]	774	1			T3	1		T14	2		T16	2
auto[2]	773	1			T1	1		T19	1		T30	1
auto[3]	779	1			T1	2		T19	2		T35	1
auto[4]	421	1			T14	1		T19	1		T66	1
auto[5]	331	1			T3	5		T14	2		T35	2
auto[6]	349	1			T14	2		T15	1		T16	1
auto[7]	363	1			T1	2		T16	1		T66	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1464	1			T1	2		T3	5		T14	5
clear_one[1]	774	1			T3	1		T14	2		T16	2
clear_one[2]	773	1			T1	1		T19	1		T30	1
clear_one[3]	779	1			T1	2		T19	2		T35	1
clear_none	1946	1			T1	1		T3	4		T14	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1128	1			T1	2		T14	1		T16	3
auto[StInit]	667	1			T3	2		T14	1		T15	1
auto[StCreatorRootKey]	608	1			T3	2		T14	1		T19	1
auto[StOwnerIntKey]	567	1			T1	1		T3	1		T14	1
auto[StOwnerKey]	506	1			T14	1		T15	1		T64	1
auto[StDisabled]	1948	1			T1	3		T3	5		T14	4
auto[StInvalid]	312	1			T16	3		T35	8		T36	6

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1128	1			T1	2		T14	1		T16	3
auto[StInit]	667	1			T3	2		T14	1		T15	1
auto[StCreatorRootKey]	608	1			T3	2		T14	1		T19	1
auto[StOwnerIntKey]	567	1			T1	1		T3	1		T14	1
auto[StOwnerKey]	506	1			T14	1		T15	1		T64	1
auto[StDisabled]	1948	1			T1	3		T3	5		T14	4
auto[StInvalid]	312	1			T16	3		T35	8		T36	6

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[1] - auto[2]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[1] - auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[3]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[4] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	4
[auto[4] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	4
[auto[4] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	16
[auto[4] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	4

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	1	1			T242	1		-	-		-	-
auto[0]	auto[StReset]	auto[OpGenId]	179	1			T35	1		T117	1		T27	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	201	1			T1	1		T16	1		T19	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	284	1			T14	1		T64	1		T45	1
auto[0]	auto[StInit]	auto[OpAdvance]	46	1			T3	1		T70	1		T243	1
auto[0]	auto[StInit]	auto[OpGenId]	113	1			T44	1		T27	1		T87	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	69	1			T3	1		T15	1		T86	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	187	1			T116	1		T56	1		T57	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	30	1			T3	1		T88	1		T206	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	53	1			T57	1		T142	1		T244	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	44	1			T30	1		T27	1		T87	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	81	1			T14	1		T213	1		T49	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	18	1			T86	1		T90	1		T71	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	31	1			T187	1		T245	1		T193	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	36	1			T66	1		T69	1		T6	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	53	1			T72	1		T246	1		T137	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T247	1		T243	1		T248	2
auto[0]	auto[StOwnerKey]	auto[OpGenId]	21	1			T66	1		T86	1		T27	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T50	1		T39	1		T6	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	52	1			T210	1		T249	1		T52	2
auto[0]	auto[StDisabled]	auto[OpAdvance]	33	1			T50	1		T250	1		T251	1
auto[0]	auto[StDisabled]	auto[OpGenId]	78	1			T3	1		T44	1		T60	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	55	1			T66	1		T207	1		T90	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	160	1			T64	1		T45	1		T114	2
auto[0]	auto[StDisabled]	auto[OpDisable]	20	1			T144	1		T252	1		T141	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	8	1			T253	1		T254	1		T255	1
auto[0]	auto[StInvalid]	auto[OpGenId]	22	1			T35	1		T36	2		T140	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	29	1			T35	1		T36	1		T256	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	20	1			T16	1		T35	1		T257	1
auto[1]	auto[StReset]	auto[OpGenId]	20	1			T75	1		T218	1		T258	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	27	1			T259	1		T107	1		T260	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	48	1			T16	1		T64	1		T114	1
auto[1]	auto[StInit]	auto[OpAdvance]	4	1			T261	1		T262	1		T263	1
auto[1]	auto[StInit]	auto[OpGenId]	14	1			T20	1		T218	1		T264	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	8	1			T54	1		T7	1		T149	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	16	1			T64	1		T113	1		T265	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T266	1		T149	1		T267	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T51	1		T268	1		T269	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	16	1			T270	1		T6	1		T251	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	45	1			T64	1		T8	1		T42	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T270	1		T271	1		T269	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	18	1			T198	1		T265	1		T52	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T6	2		T141	1		T261	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	43	1			T14	1		T212	1		T48	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T89	1		T141	1		T272	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	9	1			T90	1		T273	1		T240	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T89	1		T69	1		T274	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	49	1			T14	1		T155	1		T212	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	30	1			T19	1		T86	1		T206	1
auto[1]	auto[StDisabled]	auto[OpGenId]	67	1			T3	1		T27	2		T89	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	79	1			T19	1		T27	1		T57	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	157	1			T64	2		T45	2		T67	1
auto[1]	auto[StDisabled]	auto[OpDisable]	13	1			T275	1		T276	1		T54	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	10	1			T16	1		T35	1		T277	1
auto[1]	auto[StInvalid]	auto[OpGenId]	11	1			T111	1		T42	2		T256	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T278	1		T96	2		T279	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	16	1			T35	1		T36	1		T97	1
auto[2]	auto[StReset]	auto[OpGenId]	17	1			T280	1		T50	1		T281	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	25	1			T59	1		T265	1		T278	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	47	1			T155	2		T111	2		T282	1
auto[2]	auto[StInit]	auto[OpAdvance]	4	1			T20	1		T283	1		T284	1
auto[2]	auto[StInit]	auto[OpGenId]	15	1			T47	1		T51	1		T252	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	9	1			T269	2		T149	1		T285	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	17	1			T8	1		T286	1		T279	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T287	1		T154	1		T284	2
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	28	1			T19	1		T247	1		T90	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T132	1		T288	1		T289	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	42	1			T115	1		T198	1		T290	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	15	1			T75	3		T291	1		T292	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T243	1		T269	2		T220	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	20	1			T57	1		T25	1		T293	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	44	1			T45	1		T67	1		T113	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T75	1		T6	1		T294	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	13	1			T57	1		T90	1		T50	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T90	1		T295	1		T296	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	51	1			T113	1		T199	1		T47	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	26	1			T199	2		T291	1		T297	1
auto[2]	auto[StDisabled]	auto[OpGenId]	56	1			T1	1		T27	1		T201	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	67	1			T30	1		T86	2		T207	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	154	1			T64	1		T44	2		T45	1
auto[2]	auto[StDisabled]	auto[OpDisable]	12	1			T241	1		T49	1		T6	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	4	1			T256	1		T260	1		T298	1
auto[2]	auto[StInvalid]	auto[OpGenId]	16	1			T35	1		T42	1		T95	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	20	1			T42	1		T95	1		T253	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T257	1		T256	1		T299	1
auto[3]	auto[StReset]	auto[OpAdvance]	1	1			T273	1		-	-		-	-
auto[3]	auto[StReset]	auto[OpGenId]	18	1			T57	1		T111	1		T198	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	29	1			T19	1		T27	1		T97	2
auto[3]	auto[StReset]	auto[OpGenHwOut]	50	1			T113	1		T97	1		T300	1
auto[3]	auto[StInit]	auto[OpAdvance]	5	1			T25	1		T225	1		T301	2
auto[3]	auto[StInit]	auto[OpGenId]	6	1			T187	1		T7	1		T220	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	10	1			T20	1		T50	1		T6	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	25	1			T19	1		T117	1		T20	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	13	1			T89	1		T302	1		T303	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T304	1		T273	2		T305	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T89	1		T280	1		T306	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	36	1			T27	1		T155	1		T307	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T308	1		T229	1		T301	2
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T44	1		T51	1		T53	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	27	1			T1	1		T208	1		T89	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	42	1			T64	1		T47	1		T244	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T245	1		T132	1		T309	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	21	1			T117	1		T87	1		T49	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T201	1		T265	1		T6	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	39	1			T290	1		T310	1		T311	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	30	1			T201	1		T49	1		T72	1
auto[3]	auto[StDisabled]	auto[OpGenId]	57	1			T87	1		T207	1		T312	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	66	1			T1	1		T198	1		T90	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	166	1			T67	1		T113	3		T155	1
auto[3]	auto[StDisabled]	auto[OpDisable]	12	1			T57	1		T313	1		T149	2
auto[3]	auto[StInvalid]	auto[OpAdvance]	10	1			T35	1		T257	1		T26	1
auto[3]	auto[StInvalid]	auto[OpGenId]	14	1			T97	1		T253	1		T278	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T111	2		T314	1		T93	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T36	1		T95	1		T253	1
auto[4]	auto[StReset]	auto[OpGenId]	8	1			T140	1		T138	1		T278	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	8	1			T54	1		T315	1		T316	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	23	1			T113	1		T155	1		T317	1
auto[4]	auto[StInit]	auto[OpAdvance]	8	1			T57	1		T26	1		T318	1
auto[4]	auto[StInit]	auto[OpGenId]	4	1			T25	1		T319	1		T320	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	4	1			T106	1		T153	1		T321	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	19	1			T14	1		T67	1		T141	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T199	1		T291	1		T322	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T208	1		T7	1		T258	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T323	1		T180	1		T324	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T45	1		T212	1		T186	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T115	1		T325	1		T326	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T90	1		T291	1		T239	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T49	1		T53	1		T327	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T300	1		T186	1		T328	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T132	1		T302	2		T292	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	12	1			T326	1		T6	1		T318	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T329	1		T258	2		T330	3
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T67	1		T114	1		T207	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	13	1			T56	1		T6	1		T318	1
auto[4]	auto[StDisabled]	auto[OpGenId]	35	1			T66	1		T265	1		T331	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	30	1			T19	1		T142	1		T49	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	91	1			T155	1		T247	1		T332	1
auto[4]	auto[StDisabled]	auto[OpDisable]	8	1			T137	1		T328	1		T54	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	5	1			T94	1		T333	1		T334	1
auto[4]	auto[StInvalid]	auto[OpGenId]	6	1			T140	1		T96	1		T335	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T97	1		T336	1		T316	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T91	1		T95	1		T135	1
auto[5]	auto[StReset]	auto[OpGenId]	4	1			T8	1		T337	1		T180	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	8	1			T208	1		T92	1		T108	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	22	1			T35	1		T47	1		T338	1
auto[5]	auto[StInit]	auto[OpAdvance]	5	1			T5	1		T31	1		T339	1
auto[5]	auto[StInit]	auto[OpGenId]	7	1			T142	1		T294	1		T340	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	9	1			T141	1		T7	1		T294	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	13	1			T300	1		T341	1		T249	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T3	1		T56	1		T153	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T187	1		T51	1		T342	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T343	1		T50	1		T344	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	15	1			T113	1		T114	1		T210	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T3	1		T297	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T345	1		T297	1		T346	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T59	1		T206	1		T52	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T290	1		T347	1		T348	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T151	1		T349	1		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	11	1			T350	1		T351	1		T352	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T27	1		T154	1		T231	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T142	1		T213	1		T190	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	10	1			T3	1		T203	1		T353	1
auto[5]	auto[StDisabled]	auto[OpGenId]	30	1			T3	2		T115	1		T57	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	19	1			T27	1		T57	1		T270	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	80	1			T14	2		T5	1		T212	1
auto[5]	auto[StDisabled]	auto[OpDisable]	2	1			T354	1		T355	1		-	-
auto[5]	auto[StInvalid]	auto[OpAdvance]	1	1			T277	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	7	1			T94	1		T135	1		T96	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T36	1		T316	1		T356	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T35	1		T140	1		T357	1
auto[6]	auto[StReset]	auto[OpGenId]	11	1			T358	1		T359	1		T360	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	11	1			T361	1		T362	1		T363	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	28	1			T16	1		T113	1		T300	1
auto[6]	auto[StInit]	auto[OpAdvance]	5	1			T221	1		T364	1		T365	1
auto[6]	auto[StInit]	auto[OpGenId]	10	1			T25	1		T288	1		T9	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	5	1			T51	1		T366	1		T344	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	11	1			T251	1		T141	1		T367	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T132	1		T368	1		T369	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	2	1			T295	1		T370	1		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T90	1		T7	1		T214	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	27	1			T332	1		T371	1		T52	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T372	1		T373	1		T374	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T6	1		T375	1		T376	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T7	1		T225	1		T377	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T213	1		T378	1		T379	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T15	1		T380	1		T368	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	13	1			T44	1		T25	1		T7	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T98	1		T346	1		T381	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	11	1			T64	1		T56	1		T379	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	11	1			T5	1		T69	1		T7	1
auto[6]	auto[StDisabled]	auto[OpGenId]	22	1			T89	2		T75	1		T54	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	35	1			T90	1		T75	1		T272	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	68	1			T14	2		T67	1		T199	1
auto[6]	auto[StDisabled]	auto[OpDisable]	5	1			T52	1		T194	1		T154	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	5	1			T382	1		T383	1		T360	1
auto[6]	auto[StInvalid]	auto[OpGenId]	8	1			T95	1		T357	1		T335	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T111	1		T384	1		T319	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T385	1		T260	1		T335	1
auto[7]	auto[StReset]	auto[OpGenId]	15	1			T51	1		T141	1		T386	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	18	1			T1	1		T50	1		T250	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	25	1			T300	1		T341	1		T26	1
auto[7]	auto[StInit]	auto[OpAdvance]	2	1			T330	1		T215	1		-	-
auto[7]	auto[StInit]	auto[OpGenId]	4	1			T358	1		T387	1		T388	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	5	1			T66	1		T359	1		T308	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	8	1			T45	1		T114	1		T155	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T27	1		T201	1		T389	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T117	1		T21	1		T133	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T390	1		T340	1		T391	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T67	1		T379	1		T286	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T392	1		-	-		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T117	1		T88	1		T199	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T141	1		T393	1		T194	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	15	1			T210	1		T394	1		T6	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T395	1		T396	1		T321	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	13	1			T239	1		T221	1		T309	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T270	1		T6	1		T225	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T45	1		T186	1		T397	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	14	1			T6	1		T398	1		T297	1
auto[7]	auto[StDisabled]	auto[OpGenId]	26	1			T247	1		T205	1		T69	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T70	1		T259	2		T312	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	77	1			T1	1		T113	1		T290	1
auto[7]	auto[StDisabled]	auto[OpDisable]	5	1			T399	1		T227	1		T400	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	1	1			T401	1		-	-		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	6	1			T96	1		T385	1		T402	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T16	1		T111	1		T279	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T111	1		T140	1		T255	1