Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

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Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1464

1

T1

2

T3

5

T14

5

clear_one[1]

auto[0]

auto[0]

auto[0]

452

1

T3

1

T16

2

T35

2

clear_one[1]

auto[0]

auto[0]

auto[1]

129

1

T19

2

T64

3

T114

2

clear_one[1]

auto[0]

auto[1]

auto[0]

150

1

T14

2

T67

1

T86

1

clear_one[1]

auto[0]

auto[1]

auto[1]

43

1

T47

2

T50

1

T403

1

clear_one[2]

auto[0]

auto[0]

auto[0]

456

1

T1

1

T35

1

T67

2

clear_one[2]

auto[0]

auto[0]

auto[1]

132

1

T19

1

T30

1

T64

1

clear_one[2]

auto[1]

auto[0]

auto[0]

155

1

T44

2

T45

2

T113

2

clear_one[2]

auto[1]

auto[0]

auto[1]

30

1

T47

1

T345

1

T281

1

clear_one[3]

auto[0]

auto[0]

auto[0]

468

1

T1

1

T19

2

T35

1

clear_one[3]

auto[0]

auto[1]

auto[0]

133

1

T1

1

T67

1

T300

2

clear_one[3]

auto[1]

auto[0]

auto[0]

130

1

T113

3

T155

2

T87

1

clear_one[3]

auto[1]

auto[1]

auto[0]

48

1

T87

2

T47

1

T49

2

clear_none

auto[0]

auto[0]

auto[0]

1430

1

T1

1

T3

3

T14

1

clear_none

auto[0]

auto[0]

auto[1]

113

1

T3

1

T64

1

T114

2

clear_none

auto[0]

auto[1]

auto[0]

136

1

T14

1

T27

1

T247

1

clear_none

auto[0]

auto[1]

auto[1]

32

1

T144

1

T50

3

T403

1

clear_none

auto[1]

auto[0]

auto[0]

141

1

T44

1

T45

1

T60

1

clear_none

auto[1]

auto[0]

auto[1]

43

1

T142

1

T49

4

T331

1

clear_none

auto[1]

auto[1]

auto[0]

28

1

T137

1

T343

1

T250

1

clear_none

auto[1]

auto[1]

auto[1]

23

1

T187

1

T72

1

T141

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1382	1			T1	2		T3	2		T14	5
clear_all	auto[1]	82	1			T3	3		T89	2		T69	2
clear_one[1]	auto[0]	733	1			T3	1		T14	2		T16	2
clear_one[1]	auto[1]	41	1			T89	6		T270	2		T273	1
clear_one[2]	auto[0]	714	1			T1	1		T19	1		T30	1
clear_one[2]	auto[1]	59	1			T86	2		T75	4		T318	1
clear_one[3]	auto[0]	738	1			T1	2		T19	2		T35	1
clear_one[3]	auto[1]	41	1			T87	2		T89	2		T72	1
clear_none	auto[0]	1864	1			T1	1		T3	2		T14	2
clear_none	auto[1]	82	1			T3	2		T86	1		T87	1