Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11908

1

T1

12

T2

3

T3

8

auto[Attestation]

8141

1

T1

4

T2

5

T3

8

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2891	1			T2	2		T3	4		T4	1
auto[Aes]	3677	1			T1	2		T3	3		T4	1
auto[Kmac]	3596	1			T1	4		T2	1		T3	1
auto[Otbn]	3525	1			T1	5		T2	3		T3	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8013	1			T1	8		T2	8		T3	8
auto[OpGenId]	6360	1			T1	5		T2	2		T3	6
auto[OpGenSwOut]	6396	1			T1	7		T2	6		T3	5
auto[OpGenHwOut]	7293	1			T1	4		T3	5		T4	1
auto[OpDisable]	156	1			T4	1		T117	1		T27	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

11169

1

T1

8

T2

8

T3

7

auto[OpDoneFail]

17049

1

T1

16

T2

8

T3

17

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	7214	1			T1	9		T2	1		T3	1
auto[StInit]	3809	1			T1	2		T2	2		T3	2
auto[StCreatorRootKey]	3344	1			T1	2		T2	2		T3	1
auto[StOwnerIntKey]	2970	1			T1	2		T2	2		T3	3
auto[StOwnerKey]	2573	1			T1	2		T2	2		T3	1
auto[StDisabled]	8308	1			T1	7		T2	7		T3	16

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	382	1			T16	1		T19	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	102	1			T30	1		T20	3		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	85	1			T8	2		T118	1		T128	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	82	1			T2	1		T3	1		T66	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	62	1			T117	1		T60	1		T198	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	222	1			T3	1		T30	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	416	1			T1	1		T16	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	83	1			T199	1		T200	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	104	1			T115	1		T47	2		T69	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	86	1			T37	1		T60	1		T87	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	68	1			T201	2		T202	1		T203	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	264	1			T19	1		T44	1		T66	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	388	1			T1	1		T16	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	91	1			T59	1		T201	1		T204	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	91	1			T18	1		T59	1		T61	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	65	1			T1	1		T49	2		T204	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	71	1			T18	1		T27	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	211	1			T2	1		T19	1		T115	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	387	1			T1	3		T19	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	98	1			T15	1		T18	1		T115	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	75	1			T17	1		T30	1		T87	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	65	1			T18	2		T118	1		T90	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	58	1			T19	1		T156	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	223	1			T2	1		T44	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	91	1			T57	1		T49	2		T135	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	109	1			T17	1		T44	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	85	1			T15	1		T205	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	83	1			T44	1		T57	1		T206	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	63	1			T2	1		T19	1		T115	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	236	1			T86	1		T117	1		T57	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	111	1			T48	1		T135	1		T52	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	91	1			T3	1		T44	1		T20	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	79	1			T4	1		T66	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	72	1			T57	1		T8	1		T49	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	65	1			T115	1		T27	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	240	1			T1	1		T3	2		T19	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	76	1			T57	1		T47	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	107	1			T86	1		T115	1		T20	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	84	1			T19	1		T86	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	75	1			T57	1		T199	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	70	1			T57	1		T199	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	235	1			T27	1		T56	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	102	1			T57	1		T49	4		T135	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	90	1			T2	1		T17	1		T30	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	79	1			T27	1		T5	1		T207	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	84	1			T59	1		T88	1		T208	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	62	1			T87	2		T209	1		T72	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	228	1			T2	1		T19	1		T156	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	299	1			T16	1		T17	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	93	1			T20	1		T59	1		T8	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	80	1			T115	1		T37	1		T8	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	69	1			T15	1		T86	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	43	1			T199	1		T207	1		T89	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	175	1			T4	1		T19	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	509	1			T16	3		T35	1		T45	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	132	1			T19	1		T45	1		T113	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	127	1			T15	1		T17	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	95	1			T15	1		T21	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	94	1			T45	1		T56	1		T155	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	299	1			T66	1		T45	2		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	501	1			T14	4		T17	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	129	1			T17	1		T44	1		T116	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	106	1			T1	1		T14	1		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	100	1			T14	1		T67	1		T59	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	96	1			T67	1		T27	1		T142	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	269	1			T1	1		T3	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	520	1			T1	2		T16	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	114	1			T64	1		T56	1		T142	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	110	1			T19	1		T64	1		T114	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	104	1			T114	1		T210	1		T208	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	97	1			T114	1		T5	1		T142	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	253	1			T3	1		T64	2		T114	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	56	1			T47	1		T51	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	83	1			T20	1		T57	1		T118	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	82	1			T27	1		T57	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	80	1			T3	1		T18	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	52	1			T69	1		T70	1		T211	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	177	1			T3	1		T44	2		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	56	1			T57	1		T50	1		T141	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	99	1			T88	1		T212	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	111	1			T60	1		T212	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	92	1			T45	1		T113	1		T117	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	82	1			T19	1		T113	1		T89	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	302	1			T44	1		T45	2		T113	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	80	1			T57	1		T52	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	114	1			T14	1		T19	1		T67	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	115	1			T67	1		T208	1		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	106	1			T59	2		T88	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	107	1			T14	1		T30	1		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	309	1			T14	3		T30	2		T67	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	70	1			T48	1		T50	1		T141	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	127	1			T114	1		T20	1		T210	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	100	1			T17	2		T19	1		T210	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	86	1			T30	1		T64	1		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	88	1			T64	1		T142	1		T210	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	305	1			T3	1		T64	2		T114	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	211	1			T2	1		T3	1		T66	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	724	1			T3	1		T16	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	233	1			T115	1		T37	1		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	788	1			T1	1		T16	1		T19	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	205	1			T1	1		T18	2		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	712	1			T1	1		T2	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	178	1			T17	1		T18	2		T30	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	728	1			T1	3		T2	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	215	1			T2	1		T15	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	452	1			T17	1		T44	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	196	1			T4	1		T66	1		T115	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	462	1			T1	1		T3	3		T19	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	206	1			T19	1		T86	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	441	1			T86	1		T115	1		T20	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	210	1			T27	1		T59	1		T87	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	435	1			T2	2		T17	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	166	1			T15	1		T86	1		T115	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	593	1			T4	1		T16	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	302	1			T15	2		T17	1		T45	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	954	1			T16	3		T19	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	281	1			T1	1		T14	2		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	920	1			T1	1		T3	1		T14	5
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	293	1			T19	1		T64	1		T114	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	905	1			T1	2		T3	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	194	1			T3	1		T18	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	336	1			T3	1		T44	2		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	269	1			T19	1		T45	1		T113	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	473	1			T44	1		T45	2		T113	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	311	1			T14	1		T30	1		T67	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	520	1			T14	4		T19	1		T30	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	258	1			T17	2		T30	1		T64	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	518	1			T3	1		T19	1		T64	2