Unified Coverage Report :: Group Instance : attest_sw_binding_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34472

1

T1

28

T2

20

T3

29

auto[1]

267

1

T3

4

T86

6

T87

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	34482	1			T1	28		T2	20		T3	29
auto[134217728:268435455]	13	1			T86	1		T72	1		T270	1
auto[268435456:402653183]	7	1			T75	1		T292	1		T436	1
auto[402653184:536870911]	8	1			T72	1		T353	1		T437	1
auto[536870912:671088639]	10	1			T89	1		T291	1		T292	2
auto[671088640:805306367]	5	1			T258	1		T438	1		T439	2
auto[805306368:939524095]	13	1			T87	1		T89	1		T302	1
auto[939524096:1073741823]	6	1			T86	1		T426	1		T419	1
auto[1073741824:1207959551]	7	1			T248	1		T273	1		T437	1
auto[1207959552:1342177279]	13	1			T89	1		T418	1		T258	1
auto[1342177280:1476395007]	8	1			T302	1		T248	1		T418	1
auto[1476395008:1610612735]	6	1			T3	1		T438	1		T419	1
auto[1610612736:1744830463]	14	1			T86	1		T87	1		T89	1
auto[1744830464:1879048191]	3	1			T3	1		T353	1		T436	1
auto[1879048192:2013265919]	8	1			T89	1		T69	1		T416	1
auto[2013265920:2147483647]	9	1			T353	1		T437	1		T292	1
auto[2147483648:2281701375]	4	1			T436	1		T440	1		T441	1
auto[2281701376:2415919103]	6	1			T3	1		T72	1		T273	1
auto[2415919104:2550136831]	11	1			T318	1		T258	1		T437	1
auto[2550136832:2684354559]	4	1			T89	1		T438	1		T441	1
auto[2684354560:2818572287]	8	1			T86	1		T75	1		T438	1
auto[2818572288:2952790015]	8	1			T87	1		T89	1		T248	1
auto[2952790016:3087007743]	11	1			T3	1		T438	1		T420	1
auto[3087007744:3221225471]	12	1			T87	1		T75	1		T437	1
auto[3221225472:3355443199]	10	1			T270	1		T416	1		T318	1
auto[3355443200:3489660927]	10	1			T416	1		T353	3		T302	1
auto[3489660928:3623878655]	5	1			T89	1		T442	2		T443	1
auto[3623878656:3758096383]	6	1			T86	1		T258	1		T437	2
auto[3758096384:3892314111]	9	1			T291	1		T444	1		T292	2
auto[3892314112:4026531839]	7	1			T87	1		T258	1		T292	1
auto[4026531840:4160749567]	6	1			T270	1		T291	1		T287	1
auto[4160749568:4294967295]	10	1			T89	1		T75	1		T291	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	34472	1			T1	28		T2	20		T3	29
auto[0:134217727]	auto[1]	10	1			T86	1		T416	1		T353	1
auto[134217728:268435455]	auto[1]	13	1			T86	1		T72	1		T270	1
auto[268435456:402653183]	auto[1]	7	1			T75	1		T292	1		T436	1
auto[402653184:536870911]	auto[1]	8	1			T72	1		T353	1		T437	1
auto[536870912:671088639]	auto[1]	10	1			T89	1		T291	1		T292	2
auto[671088640:805306367]	auto[1]	5	1			T258	1		T438	1		T439	2
auto[805306368:939524095]	auto[1]	13	1			T87	1		T89	1		T302	1
auto[939524096:1073741823]	auto[1]	6	1			T86	1		T426	1		T419	1
auto[1073741824:1207959551]	auto[1]	7	1			T248	1		T273	1		T437	1
auto[1207959552:1342177279]	auto[1]	13	1			T89	1		T418	1		T258	1
auto[1342177280:1476395007]	auto[1]	8	1			T302	1		T248	1		T418	1
auto[1476395008:1610612735]	auto[1]	6	1			T3	1		T438	1		T419	1
auto[1610612736:1744830463]	auto[1]	14	1			T86	1		T87	1		T89	1
auto[1744830464:1879048191]	auto[1]	3	1			T3	1		T353	1		T436	1
auto[1879048192:2013265919]	auto[1]	8	1			T89	1		T69	1		T416	1
auto[2013265920:2147483647]	auto[1]	9	1			T353	1		T437	1		T292	1
auto[2147483648:2281701375]	auto[1]	4	1			T436	1		T440	1		T441	1
auto[2281701376:2415919103]	auto[1]	6	1			T3	1		T72	1		T273	1
auto[2415919104:2550136831]	auto[1]	11	1			T318	1		T258	1		T437	1
auto[2550136832:2684354559]	auto[1]	4	1			T89	1		T438	1		T441	1
auto[2684354560:2818572287]	auto[1]	8	1			T86	1		T75	1		T438	1
auto[2818572288:2952790015]	auto[1]	8	1			T87	1		T89	1		T248	1
auto[2952790016:3087007743]	auto[1]	11	1			T3	1		T438	1		T420	1
auto[3087007744:3221225471]	auto[1]	12	1			T87	1		T75	1		T437	1
auto[3221225472:3355443199]	auto[1]	10	1			T270	1		T416	1		T318	1
auto[3355443200:3489660927]	auto[1]	10	1			T416	1		T353	3		T302	1
auto[3489660928:3623878655]	auto[1]	5	1			T89	1		T442	2		T443	1
auto[3623878656:3758096383]	auto[1]	6	1			T86	1		T258	1		T437	2
auto[3758096384:3892314111]	auto[1]	9	1			T291	1		T444	1		T292	2
auto[3892314112:4026531839]	auto[1]	7	1			T87	1		T258	1		T292	1
auto[4026531840:4160749567]	auto[1]	6	1			T270	1		T291	1		T287	1
auto[4160749568:4294967295]	auto[1]	10	1			T89	1		T75	1		T291	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3209

1

T3

3

T4

1

T15

1

auto[1]

261

1

T3

1

T86

4

T87

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	134	1			T44	1		T86	1		T36	1
auto[134217728:268435455]	99	1			T57	1		T142	1		T199	1
auto[268435456:402653183]	106	1			T35	1		T116	1		T27	1
auto[402653184:536870911]	106	1			T16	1		T117	1		T27	1
auto[536870912:671088639]	110	1			T44	1		T21	1		T87	2
auto[671088640:805306367]	120	1			T56	1		T142	1		T247	1
auto[805306368:939524095]	106	1			T35	1		T86	1		T97	1
auto[939524096:1073741823]	109	1			T19	1		T86	1		T117	1
auto[1073741824:1207959551]	111	1			T16	1		T35	1		T44	1
auto[1207959552:1342177279]	110	1			T17	1		T115	1		T20	1
auto[1342177280:1476395007]	111	1			T21	1		T5	1		T90	1
auto[1476395008:1610612735]	102	1			T117	1		T36	1		T199	1
auto[1610612736:1744830463]	110	1			T30	1		T36	1		T59	1
auto[1744830464:1879048191]	99	1			T15	1		T86	1		T115	1
auto[1879048192:2013265919]	97	1			T35	1		T86	1		T20	1
auto[2013265920:2147483647]	105	1			T17	1		T115	1		T87	1
auto[2147483648:2281701375]	103	1			T4	1		T56	2		T57	3
auto[2281701376:2415919103]	109	1			T35	1		T117	1		T87	1
auto[2415919104:2550136831]	114	1			T3	1		T19	2		T35	1
auto[2550136832:2684354559]	113	1			T3	1		T35	1		T44	1
auto[2684354560:2818572287]	101	1			T3	1		T16	1		T57	1
auto[2818572288:2952790015]	102	1			T30	1		T57	2		T21	1
auto[2952790016:3087007743]	112	1			T16	2		T115	1		T20	1
auto[3087007744:3221225471]	107	1			T44	1		T88	1		T91	1
auto[3221225472:3355443199]	107	1			T3	1		T35	1		T56	1
auto[3355443200:3489660927]	103	1			T17	1		T35	1		T115	1
auto[3489660928:3623878655]	111	1			T19	1		T117	2		T20	1
auto[3623878656:3758096383]	104	1			T16	1		T36	1		T57	1
auto[3758096384:3892314111]	123	1			T35	1		T57	1		T47	1
auto[3892314112:4026531839]	117	1			T35	1		T199	1		T198	1
auto[4026531840:4160749567]	101	1			T47	1		T244	1		T90	1
auto[4160749568:4294967295]	108	1			T57	2		T199	1		T111	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	1	63	98.44	1

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[3623878656:3758096383]]	[auto[1]]	0	1	1

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	114	1			T44	1		T86	1		T36	1
auto[0:134217727]	auto[1]	20	1			T89	2		T270	1		T248	1
auto[134217728:268435455]	auto[0]	97	1			T57	1		T142	1		T199	1
auto[134217728:268435455]	auto[1]	2	1			T270	1		T445	1		-	-
auto[268435456:402653183]	auto[0]	98	1			T35	1		T116	1		T27	1
auto[268435456:402653183]	auto[1]	8	1			T89	1		T270	1		T353	1
auto[402653184:536870911]	auto[0]	102	1			T16	1		T117	1		T27	1
auto[402653184:536870911]	auto[1]	4	1			T258	1		T309	1		T442	1
auto[536870912:671088639]	auto[0]	103	1			T44	1		T21	1		T87	1
auto[536870912:671088639]	auto[1]	7	1			T87	1		T69	1		T446	1
auto[671088640:805306367]	auto[0]	110	1			T56	1		T142	1		T247	1
auto[671088640:805306367]	auto[1]	10	1			T89	1		T75	2		T248	1
auto[805306368:939524095]	auto[0]	99	1			T35	1		T86	1		T97	1
auto[805306368:939524095]	auto[1]	7	1			T89	2		T75	1		T287	1
auto[939524096:1073741823]	auto[0]	102	1			T19	1		T117	1		T5	1
auto[939524096:1073741823]	auto[1]	7	1			T86	1		T89	1		T353	1
auto[1073741824:1207959551]	auto[0]	103	1			T16	1		T35	1		T44	1
auto[1073741824:1207959551]	auto[1]	8	1			T86	1		T75	1		T437	1
auto[1207959552:1342177279]	auto[0]	101	1			T17	1		T115	1		T20	1
auto[1207959552:1342177279]	auto[1]	9	1			T87	2		T292	1		T309	1
auto[1342177280:1476395007]	auto[0]	103	1			T21	1		T5	1		T90	1
auto[1342177280:1476395007]	auto[1]	8	1			T270	1		T353	1		T248	2
auto[1476395008:1610612735]	auto[0]	94	1			T117	1		T36	1		T199	1
auto[1476395008:1610612735]	auto[1]	8	1			T248	1		T291	1		T444	1
auto[1610612736:1744830463]	auto[0]	102	1			T30	1		T36	1		T59	1
auto[1610612736:1744830463]	auto[1]	8	1			T69	1		T75	1		T353	1
auto[1744830464:1879048191]	auto[0]	86	1			T15	1		T115	1		T27	1
auto[1744830464:1879048191]	auto[1]	13	1			T86	1		T87	1		T89	1
auto[1879048192:2013265919]	auto[0]	92	1			T35	1		T20	1		T57	1
auto[1879048192:2013265919]	auto[1]	5	1			T86	1		T70	1		T446	1
auto[2013265920:2147483647]	auto[0]	98	1			T17	1		T115	1		T142	1
auto[2013265920:2147483647]	auto[1]	7	1			T87	1		T270	1		T438	2
auto[2147483648:2281701375]	auto[0]	94	1			T4	1		T56	2		T57	3
auto[2147483648:2281701375]	auto[1]	9	1			T418	2		T437	1		T420	1
auto[2281701376:2415919103]	auto[0]	99	1			T35	1		T117	1		T87	1
auto[2281701376:2415919103]	auto[1]	10	1			T69	1		T75	1		T437	1
auto[2415919104:2550136831]	auto[0]	104	1			T3	1		T19	2		T35	1
auto[2415919104:2550136831]	auto[1]	10	1			T87	1		T444	1		T418	1
auto[2550136832:2684354559]	auto[0]	107	1			T35	1		T44	1		T142	1
auto[2550136832:2684354559]	auto[1]	6	1			T3	1		T444	1		T438	1
auto[2684354560:2818572287]	auto[0]	97	1			T3	1		T16	1		T57	1
auto[2684354560:2818572287]	auto[1]	4	1			T292	1		T352	1		T438	1
auto[2818572288:2952790015]	auto[0]	94	1			T30	1		T57	2		T21	1
auto[2818572288:2952790015]	auto[1]	8	1			T270	1		T418	1		T368	1
auto[2952790016:3087007743]	auto[0]	101	1			T16	2		T115	1		T20	1
auto[2952790016:3087007743]	auto[1]	11	1			T270	1		T353	1		T318	1
auto[3087007744:3221225471]	auto[0]	103	1			T44	1		T88	1		T91	1
auto[3087007744:3221225471]	auto[1]	4	1			T352	1		T438	1		T439	1
auto[3221225472:3355443199]	auto[0]	99	1			T3	1		T35	1		T56	1
auto[3221225472:3355443199]	auto[1]	8	1			T248	1		T444	1		T437	1
auto[3355443200:3489660927]	auto[0]	95	1			T17	1		T35	1		T115	1
auto[3355443200:3489660927]	auto[1]	8	1			T302	1		T437	1		T419	1
auto[3489660928:3623878655]	auto[0]	97	1			T19	1		T117	2		T20	1
auto[3489660928:3623878655]	auto[1]	14	1			T69	2		T70	1		T248	1
auto[3623878656:3758096383]	auto[0]	104	1			T16	1		T36	1		T57	1
auto[3758096384:3892314111]	auto[0]	111	1			T35	1		T57	1		T47	1
auto[3758096384:3892314111]	auto[1]	12	1			T75	1		T318	1		T248	1
auto[3892314112:4026531839]	auto[0]	106	1			T35	1		T199	1		T198	1
auto[3892314112:4026531839]	auto[1]	11	1			T89	1		T270	1		T353	1
auto[4026531840:4160749567]	auto[0]	92	1			T47	1		T244	1		T90	1
auto[4026531840:4160749567]	auto[1]	9	1			T416	1		T291	1		T418	1
auto[4160749568:4294967295]	auto[0]	102	1			T57	2		T199	1		T111	1
auto[4160749568:4294967295]	auto[1]	6	1			T302	1		T442	1		T440	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1675

1

T3

2

T4

1

T15

2

auto[1]

1952

1

T3

1

T15

3

T16

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	112	1			T44	1		T115	1		T57	1
auto[134217728:268435455]	97	1			T17	1		T115	1		T56	1
auto[268435456:402653183]	114	1			T3	1		T19	1		T35	1
auto[402653184:536870911]	137	1			T35	1		T20	1		T27	1
auto[536870912:671088639]	127	1			T19	1		T116	1		T20	1
auto[671088640:805306367]	111	1			T16	1		T57	1		T88	2
auto[805306368:939524095]	116	1			T36	1		T57	1		T5	2
auto[939524096:1073741823]	99	1			T117	1		T57	1		T5	1
auto[1073741824:1207959551]	118	1			T19	1		T35	2		T27	1
auto[1207959552:1342177279]	112	1			T35	1		T44	1		T116	1
auto[1342177280:1476395007]	122	1			T115	1		T206	1		T208	1
auto[1476395008:1610612735]	96	1			T36	1		T56	1		T57	1
auto[1610612736:1744830463]	110	1			T94	1		T447	1		T28	1
auto[1744830464:1879048191]	122	1			T15	1		T36	1		T88	1
auto[1879048192:2013265919]	103	1			T115	1		T59	1		T142	2
auto[2013265920:2147483647]	127	1			T15	1		T16	2		T35	1
auto[2147483648:2281701375]	124	1			T57	1		T87	1		T8	1
auto[2281701376:2415919103]	132	1			T3	1		T86	1		T117	1
auto[2415919104:2550136831]	117	1			T16	1		T21	1		T111	1
auto[2550136832:2684354559]	108	1			T15	1		T57	2		T97	1
auto[2684354560:2818572287]	100	1			T19	1		T115	1		T117	1
auto[2818572288:2952790015]	118	1			T16	1		T35	1		T21	1
auto[2952790016:3087007743]	133	1			T3	1		T35	1		T86	1
auto[3087007744:3221225471]	102	1			T30	1		T27	1		T57	1
auto[3221225472:3355443199]	102	1			T44	1		T27	1		T59	1
auto[3355443200:3489660927]	101	1			T27	1		T87	1		T5	2
auto[3489660928:3623878655]	112	1			T15	1		T16	1		T117	1
auto[3623878656:3758096383]	98	1			T30	1		T35	1		T21	1
auto[3758096384:3892314111]	111	1			T57	1		T282	2		T49	1
auto[3892314112:4026531839]	119	1			T44	1		T117	2		T20	2
auto[4026531840:4160749567]	103	1			T15	1		T17	2		T56	1
auto[4160749568:4294967295]	124	1			T4	1		T35	2		T36	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T44	1		T447	1		T278	1
auto[0:134217727]	auto[1]	63	1			T115	1		T57	1		T38	1
auto[134217728:268435455]	auto[0]	50	1			T17	1		T57	1		T199	1
auto[134217728:268435455]	auto[1]	47	1			T115	1		T56	1		T142	1
auto[268435456:402653183]	auto[0]	50	1			T3	1		T35	1		T128	1
auto[268435456:402653183]	auto[1]	64	1			T19	1		T201	1		T90	2
auto[402653184:536870911]	auto[0]	63	1			T35	1		T27	1		T88	1
auto[402653184:536870911]	auto[1]	74	1			T20	1		T5	2		T206	1
auto[536870912:671088639]	auto[0]	61	1			T19	1		T116	1		T111	1
auto[536870912:671088639]	auto[1]	66	1			T20	1		T90	1		T187	1
auto[671088640:805306367]	auto[0]	50	1			T16	1		T57	1		T142	1
auto[671088640:805306367]	auto[1]	61	1			T88	2		T89	1		T144	1
auto[805306368:939524095]	auto[0]	53	1			T36	1		T5	1		T97	1
auto[805306368:939524095]	auto[1]	63	1			T57	1		T5	1		T136	1
auto[939524096:1073741823]	auto[0]	44	1			T5	1		T247	1		T47	1
auto[939524096:1073741823]	auto[1]	55	1			T117	1		T57	1		T206	1
auto[1073741824:1207959551]	auto[0]	62	1			T35	2		T57	1		T142	1
auto[1073741824:1207959551]	auto[1]	56	1			T19	1		T27	1		T56	1
auto[1207959552:1342177279]	auto[0]	54	1			T35	1		T116	1		T247	1
auto[1207959552:1342177279]	auto[1]	58	1			T44	1		T47	1		T201	1
auto[1342177280:1476395007]	auto[0]	60	1			T115	1		T253	1		T6	1
auto[1342177280:1476395007]	auto[1]	62	1			T206	1		T208	1		T70	1
auto[1476395008:1610612735]	auto[0]	43	1			T57	1		T206	1		T198	1
auto[1476395008:1610612735]	auto[1]	53	1			T36	1		T56	1		T59	1
auto[1610612736:1744830463]	auto[0]	48	1			T94	1		T447	1		T25	1
auto[1610612736:1744830463]	auto[1]	62	1			T28	1		T259	1		T135	1
auto[1744830464:1879048191]	auto[0]	51	1			T69	1		T22	1		T95	1
auto[1744830464:1879048191]	auto[1]	71	1			T15	1		T36	1		T88	1
auto[1879048192:2013265919]	auto[0]	44	1			T282	1		T91	1		T50	1
auto[1879048192:2013265919]	auto[1]	59	1			T115	1		T59	1		T142	2
auto[2013265920:2147483647]	auto[0]	57	1			T15	1		T16	1		T44	1
auto[2013265920:2147483647]	auto[1]	70	1			T16	1		T35	1		T20	1
auto[2147483648:2281701375]	auto[0]	53	1			T69	1		T71	1		T50	1
auto[2147483648:2281701375]	auto[1]	71	1			T57	1		T87	1		T8	1
auto[2281701376:2415919103]	auto[0]	60	1			T86	1		T57	1		T282	1
auto[2281701376:2415919103]	auto[1]	72	1			T3	1		T117	1		T5	1
auto[2415919104:2550136831]	auto[0]	56	1			T16	1		T111	1		T69	1
auto[2415919104:2550136831]	auto[1]	61	1			T21	1		T247	1		T47	1
auto[2550136832:2684354559]	auto[0]	57	1			T57	2		T97	1		T95	1
auto[2550136832:2684354559]	auto[1]	51	1			T15	1		T48	1		T135	1
auto[2684354560:2818572287]	auto[0]	45	1			T198	1		T38	1		T138	1
auto[2684354560:2818572287]	auto[1]	55	1			T19	1		T115	1		T117	1
auto[2818572288:2952790015]	auto[0]	70	1			T35	1		T21	1		T5	1
auto[2818572288:2952790015]	auto[1]	48	1			T16	1		T88	1		T111	1
auto[2952790016:3087007743]	auto[0]	59	1			T3	1		T86	1		T20	1
auto[2952790016:3087007743]	auto[1]	74	1			T35	1		T57	1		T42	1
auto[3087007744:3221225471]	auto[0]	47	1			T97	1		T198	1		T95	1
auto[3087007744:3221225471]	auto[1]	55	1			T30	1		T27	1		T57	1
auto[3221225472:3355443199]	auto[0]	47	1			T27	1		T97	1		T325	1
auto[3221225472:3355443199]	auto[1]	55	1			T44	1		T59	1		T142	1
auto[3355443200:3489660927]	auto[0]	49	1			T5	2		T199	1		T201	1
auto[3355443200:3489660927]	auto[1]	52	1			T27	1		T87	1		T199	1
auto[3489660928:3623878655]	auto[0]	47	1			T15	1		T16	1		T117	1
auto[3489660928:3623878655]	auto[1]	65	1			T89	1		T71	1		T345	1
auto[3623878656:3758096383]	auto[0]	52	1			T30	1		T35	1		T21	1
auto[3623878656:3758096383]	auto[1]	46	1			T111	1		T90	1		T188	1
auto[3758096384:3892314111]	auto[0]	50	1			T282	1		T49	1		T188	1
auto[3758096384:3892314111]	auto[1]	61	1			T57	1		T282	1		T188	1
auto[3892314112:4026531839]	auto[0]	49	1			T117	1		T20	1		T247	1
auto[3892314112:4026531839]	auto[1]	70	1			T44	1		T117	1		T20	1
auto[4026531840:4160749567]	auto[0]	41	1			T17	1		T57	1		T111	1
auto[4026531840:4160749567]	auto[1]	62	1			T15	1		T17	1		T56	1
auto[4160749568:4294967295]	auto[0]	54	1			T4	1		T35	1		T201	1
auto[4160749568:4294967295]	auto[1]	70	1			T35	1		T36	1		T57	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1680

1

T3

1

T4

1

T15

2

auto[1]

1947

1

T3

2

T15

3

T16

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T57	1		T5	1		T142	1
auto[134217728:268435455]	106	1			T44	1		T117	1		T20	1
auto[268435456:402653183]	116	1			T44	1		T116	1		T27	1
auto[402653184:536870911]	115	1			T4	1		T15	3		T117	2
auto[536870912:671088639]	119	1			T30	1		T91	1		T201	1
auto[671088640:805306367]	131	1			T3	1		T35	1		T27	2
auto[805306368:939524095]	97	1			T56	1		T57	1		T142	1
auto[939524096:1073741823]	117	1			T36	1		T56	1		T57	1
auto[1073741824:1207959551]	128	1			T3	1		T15	1		T97	1
auto[1207959552:1342177279]	102	1			T16	2		T35	2		T87	1
auto[1342177280:1476395007]	104	1			T17	1		T86	1		T20	1
auto[1476395008:1610612735]	103	1			T35	1		T44	1		T36	1
auto[1610612736:1744830463]	113	1			T56	1		T87	1		T5	1
auto[1744830464:1879048191]	105	1			T16	1		T115	3		T20	1
auto[1879048192:2013265919]	124	1			T16	1		T35	2		T57	1
auto[2013265920:2147483647]	112	1			T17	1		T19	1		T35	1
auto[2147483648:2281701375]	122	1			T115	1		T87	1		T282	1
auto[2281701376:2415919103]	113	1			T20	1		T57	2		T88	1
auto[2415919104:2550136831]	131	1			T57	1		T199	1		T111	1
auto[2550136832:2684354559]	131	1			T19	1		T27	1		T56	1
auto[2684354560:2818572287]	117	1			T17	1		T117	1		T27	1
auto[2818572288:2952790015]	110	1			T19	1		T57	2		T111	1
auto[2952790016:3087007743]	124	1			T27	1		T36	1		T199	1
auto[3087007744:3221225471]	104	1			T16	1		T35	1		T57	1
auto[3221225472:3355443199]	114	1			T47	1		T69	1		T244	1
auto[3355443200:3489660927]	98	1			T35	1		T86	1		T88	1
auto[3489660928:3623878655]	104	1			T3	1		T30	1		T35	1
auto[3623878656:3758096383]	105	1			T16	1		T57	1		T59	1
auto[3758096384:3892314111]	114	1			T15	1		T35	1		T57	1
auto[3892314112:4026531839]	119	1			T44	1		T116	1		T21	1
auto[4026531840:4160749567]	119	1			T115	1		T57	1		T59	1
auto[4160749568:4294967295]	107	1			T19	1		T27	1		T57	1