Unified Coverage Report :: Group Instance : salt_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3212

1

T3

3

T4

1

T15

1

auto[1]

268

1

T3

6

T86

5

T87

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	117	1			T16	1		T27	1		T57	2
auto[134217728:268435455]	112	1			T3	1		T35	1		T20	1
auto[268435456:402653183]	100	1			T35	1		T116	1		T57	1
auto[402653184:536870911]	103	1			T117	1		T57	1		T87	1
auto[536870912:671088639]	118	1			T111	1		T247	1		T201	1
auto[671088640:805306367]	97	1			T3	2		T21	1		T5	1
auto[805306368:939524095]	107	1			T35	1		T115	1		T57	1
auto[939524096:1073741823]	108	1			T30	1		T115	1		T201	1
auto[1073741824:1207959551]	100	1			T4	1		T19	1		T44	1
auto[1207959552:1342177279]	100	1			T17	1		T86	2		T57	1
auto[1342177280:1476395007]	107	1			T27	1		T111	1		T198	2
auto[1476395008:1610612735]	138	1			T35	1		T86	1		T115	1
auto[1610612736:1744830463]	98	1			T20	1		T57	1		T142	3
auto[1744830464:1879048191]	108	1			T57	2		T247	1		T198	1
auto[1879048192:2013265919]	103	1			T16	1		T44	1		T86	1
auto[2013265920:2147483647]	110	1			T20	1		T88	1		T5	1
auto[2147483648:2281701375]	122	1			T3	1		T35	1		T57	1
auto[2281701376:2415919103]	118	1			T16	1		T35	2		T86	1
auto[2415919104:2550136831]	102	1			T15	1		T16	1		T19	1
auto[2550136832:2684354559]	115	1			T16	1		T35	2		T86	1
auto[2684354560:2818572287]	113	1			T3	1		T17	1		T115	1
auto[2818572288:2952790015]	114	1			T86	1		T57	1		T59	1
auto[2952790016:3087007743]	101	1			T16	1		T57	2		T21	1
auto[3087007744:3221225471]	122	1			T44	1		T87	1		T142	1
auto[3221225472:3355443199]	120	1			T20	1		T27	1		T36	2
auto[3355443200:3489660927]	101	1			T20	1		T56	1		T208	1
auto[3489660928:3623878655]	102	1			T3	1		T35	2		T117	1
auto[3623878656:3758096383]	110	1			T44	1		T56	1		T88	1
auto[3758096384:3892314111]	120	1			T117	1		T247	1		T47	1
auto[3892314112:4026531839]	101	1			T3	1		T19	1		T56	2
auto[4026531840:4160749567]	102	1			T3	1		T19	1		T30	1
auto[4160749568:4294967295]	91	1			T3	1		T17	1		T117	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	109	1			T16	1		T27	1		T57	2
auto[0:134217727]	auto[1]	8	1			T69	1		T353	1		T444	1
auto[134217728:268435455]	auto[0]	107	1			T35	1		T20	1		T57	1
auto[134217728:268435455]	auto[1]	5	1			T3	1		T437	2		T292	1
auto[268435456:402653183]	auto[0]	89	1			T35	1		T116	1		T57	1
auto[268435456:402653183]	auto[1]	11	1			T75	1		T353	1		T437	1
auto[402653184:536870911]	auto[0]	91	1			T117	1		T57	1		T47	2
auto[402653184:536870911]	auto[1]	12	1			T87	1		T416	1		T248	1
auto[536870912:671088639]	auto[0]	109	1			T111	1		T247	1		T201	1
auto[536870912:671088639]	auto[1]	9	1			T75	1		T270	2		T318	1
auto[671088640:805306367]	auto[0]	89	1			T3	2		T21	1		T5	1
auto[671088640:805306367]	auto[1]	8	1			T353	1		T426	1		T352	2
auto[805306368:939524095]	auto[0]	103	1			T35	1		T115	1		T57	1
auto[805306368:939524095]	auto[1]	4	1			T69	1		T302	1		T352	1
auto[939524096:1073741823]	auto[0]	95	1			T30	1		T115	1		T201	1
auto[939524096:1073741823]	auto[1]	13	1			T69	1		T75	1		T273	1
auto[1073741824:1207959551]	auto[0]	94	1			T4	1		T19	1		T44	1
auto[1073741824:1207959551]	auto[1]	6	1			T353	1		T368	1		T301	1
auto[1207959552:1342177279]	auto[0]	93	1			T17	1		T57	1		T206	1
auto[1207959552:1342177279]	auto[1]	7	1			T86	2		T69	1		T72	1
auto[1342177280:1476395007]	auto[0]	103	1			T27	1		T111	1		T198	2
auto[1342177280:1476395007]	auto[1]	4	1			T318	1		T443	1		T453	1
auto[1476395008:1610612735]	auto[0]	130	1			T35	1		T86	1		T115	1
auto[1476395008:1610612735]	auto[1]	8	1			T353	1		T302	1		T330	2
auto[1610612736:1744830463]	auto[0]	93	1			T20	1		T57	1		T142	3
auto[1610612736:1744830463]	auto[1]	5	1			T353	1		T437	1		T438	1
auto[1744830464:1879048191]	auto[0]	103	1			T57	2		T247	1		T198	1
auto[1744830464:1879048191]	auto[1]	5	1			T353	2		T302	1		T437	1
auto[1879048192:2013265919]	auto[0]	93	1			T16	1		T44	1		T5	1
auto[1879048192:2013265919]	auto[1]	10	1			T86	1		T270	1		T416	1
auto[2013265920:2147483647]	auto[0]	105	1			T20	1		T88	1		T5	1
auto[2013265920:2147483647]	auto[1]	5	1			T437	1		T436	1		T440	1
auto[2147483648:2281701375]	auto[0]	110	1			T3	1		T35	1		T57	1
auto[2147483648:2281701375]	auto[1]	12	1			T291	1		T418	1		T292	1
auto[2281701376:2415919103]	auto[0]	115	1			T16	1		T35	2		T115	1
auto[2281701376:2415919103]	auto[1]	3	1			T86	1		T444	1		T368	1
auto[2415919104:2550136831]	auto[0]	92	1			T15	1		T16	1		T19	1
auto[2415919104:2550136831]	auto[1]	10	1			T89	1		T353	1		T302	1
auto[2550136832:2684354559]	auto[0]	104	1			T16	1		T35	2		T86	1
auto[2550136832:2684354559]	auto[1]	11	1			T444	1		T426	1		T258	1
auto[2684354560:2818572287]	auto[0]	95	1			T17	1		T115	1		T20	1
auto[2684354560:2818572287]	auto[1]	18	1			T3	1		T87	2		T416	2
auto[2818572288:2952790015]	auto[0]	107	1			T57	1		T59	1		T5	1
auto[2818572288:2952790015]	auto[1]	7	1			T86	1		T444	1		T437	1
auto[2952790016:3087007743]	auto[0]	94	1			T16	1		T57	2		T21	1
auto[2952790016:3087007743]	auto[1]	7	1			T302	1		T368	1		T440	1
auto[3087007744:3221225471]	auto[0]	110	1			T44	1		T142	1		T206	1
auto[3087007744:3221225471]	auto[1]	12	1			T87	1		T273	1		T258	1
auto[3221225472:3355443199]	auto[0]	111	1			T20	1		T27	1		T36	2
auto[3221225472:3355443199]	auto[1]	9	1			T291	1		T444	1		T437	1
auto[3355443200:3489660927]	auto[0]	94	1			T20	1		T56	1		T208	1
auto[3355443200:3489660927]	auto[1]	7	1			T89	1		T438	1		T419	1
auto[3489660928:3623878655]	auto[0]	91	1			T35	2		T117	1		T56	1
auto[3489660928:3623878655]	auto[1]	11	1			T3	1		T87	1		T89	1
auto[3623878656:3758096383]	auto[0]	101	1			T44	1		T56	1		T88	1
auto[3623878656:3758096383]	auto[1]	9	1			T353	1		T302	1		T444	1
auto[3758096384:3892314111]	auto[0]	112	1			T117	1		T247	1		T47	1
auto[3758096384:3892314111]	auto[1]	8	1			T444	1		T426	1		T258	2
auto[3892314112:4026531839]	auto[0]	97	1			T19	1		T56	2		T142	1
auto[3892314112:4026531839]	auto[1]	4	1			T3	1		T270	1		T419	1
auto[4026531840:4160749567]	auto[0]	92	1			T19	1		T30	1		T117	2
auto[4026531840:4160749567]	auto[1]	10	1			T3	1		T87	1		T69	1
auto[4160749568:4294967295]	auto[0]	81	1			T17	1		T117	1		T36	1
auto[4160749568:4294967295]	auto[1]	10	1			T3	1		T87	1		T353	1