Unified Coverage Report :: Group Instance : sealing_sw_binding_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1700

1

T3

1

T4

1

T15

3

auto[1]

1927

1

T3

2

T15

2

T16

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	111	1			T35	1		T117	1		T36	1
auto[134217728:268435455]	118	1			T20	2		T27	1		T56	1
auto[268435456:402653183]	117	1			T15	1		T30	1		T35	2
auto[402653184:536870911]	101	1			T15	1		T35	1		T88	1
auto[536870912:671088639]	131	1			T3	1		T19	1		T30	1
auto[671088640:805306367]	103	1			T35	1		T199	1		T111	1
auto[805306368:939524095]	107	1			T35	1		T115	1		T5	1
auto[939524096:1073741823]	111	1			T57	1		T47	1		T198	1
auto[1073741824:1207959551]	128	1			T17	1		T57	1		T87	1
auto[1207959552:1342177279]	128	1			T20	1		T27	3		T47	1
auto[1342177280:1476395007]	104	1			T19	1		T115	1		T116	1
auto[1476395008:1610612735]	125	1			T19	1		T20	1		T57	1
auto[1610612736:1744830463]	112	1			T115	1		T36	1		T142	1
auto[1744830464:1879048191]	126	1			T35	1		T57	1		T59	1
auto[1879048192:2013265919]	112	1			T15	1		T117	1		T87	1
auto[2013265920:2147483647]	110	1			T16	1		T17	1		T35	1
auto[2147483648:2281701375]	105	1			T47	1		T69	1		T94	2
auto[2281701376:2415919103]	107	1			T115	1		T27	1		T57	3
auto[2415919104:2550136831]	114	1			T15	1		T117	1		T21	1
auto[2550136832:2684354559]	108	1			T35	1		T56	1		T57	1
auto[2684354560:2818572287]	95	1			T3	1		T16	1		T44	1
auto[2818572288:2952790015]	108	1			T16	1		T19	1		T57	3
auto[2952790016:3087007743]	102	1			T3	1		T44	1		T88	1
auto[3087007744:3221225471]	134	1			T142	1		T111	1		T247	1
auto[3221225472:3355443199]	109	1			T44	1		T86	1		T57	1
auto[3355443200:3489660927]	123	1			T4	1		T16	1		T115	1
auto[3489660928:3623878655]	104	1			T16	1		T17	1		T48	1
auto[3623878656:3758096383]	105	1			T15	1		T16	1		T86	1
auto[3758096384:3892314111]	114	1			T35	1		T20	1		T57	2
auto[3892314112:4026531839]	99	1			T36	1		T56	1		T88	1
auto[4026531840:4160749567]	127	1			T117	1		T56	1		T57	1
auto[4160749568:4294967295]	129	1			T44	1		T111	1		T47	3

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T35	1		T117	1		T5	1
auto[0:134217727]	auto[1]	55	1			T36	1		T91	1		T48	1
auto[134217728:268435455]	auto[0]	50	1			T198	1		T22	1		T253	1
auto[134217728:268435455]	auto[1]	68	1			T20	2		T27	1		T56	1
auto[268435456:402653183]	auto[0]	52	1			T57	1		T8	1		T47	1
auto[268435456:402653183]	auto[1]	65	1			T15	1		T30	1		T35	2
auto[402653184:536870911]	auto[0]	43	1			T35	1		T97	1		T247	1
auto[402653184:536870911]	auto[1]	58	1			T15	1		T88	1		T8	1
auto[536870912:671088639]	auto[0]	58	1			T19	1		T35	1		T27	1
auto[536870912:671088639]	auto[1]	73	1			T3	1		T30	1		T44	1
auto[671088640:805306367]	auto[0]	38	1			T35	1		T69	1		T140	1
auto[671088640:805306367]	auto[1]	65	1			T199	1		T111	1		T325	1
auto[805306368:939524095]	auto[0]	56	1			T35	1		T115	1		T91	1
auto[805306368:939524095]	auto[1]	51	1			T5	1		T198	1		T187	1
auto[939524096:1073741823]	auto[0]	66	1			T57	1		T47	1		T198	1
auto[939524096:1073741823]	auto[1]	45	1			T325	1		T201	1		T421	1
auto[1073741824:1207959551]	auto[0]	66	1			T17	1		T57	1		T87	1
auto[1073741824:1207959551]	auto[1]	62	1			T206	3		T89	1		T187	1
auto[1207959552:1342177279]	auto[0]	60	1			T27	1		T47	1		T188	1
auto[1207959552:1342177279]	auto[1]	68	1			T20	1		T27	2		T201	1
auto[1342177280:1476395007]	auto[0]	53	1			T20	1		T91	1		T22	1
auto[1342177280:1476395007]	auto[1]	51	1			T19	1		T115	1		T116	1
auto[1476395008:1610612735]	auto[0]	60	1			T142	1		T111	1		T90	1
auto[1476395008:1610612735]	auto[1]	65	1			T19	1		T20	1		T57	1
auto[1610612736:1744830463]	auto[0]	43	1			T91	1		T244	1		T189	1
auto[1610612736:1744830463]	auto[1]	69	1			T115	1		T36	1		T142	1
auto[1744830464:1879048191]	auto[0]	64	1			T35	1		T87	1		T198	1
auto[1744830464:1879048191]	auto[1]	62	1			T57	1		T59	1		T47	1
auto[1879048192:2013265919]	auto[0]	53	1			T15	1		T97	1		T47	1
auto[1879048192:2013265919]	auto[1]	59	1			T117	1		T87	1		T5	1
auto[2013265920:2147483647]	auto[0]	59	1			T16	1		T35	1		T201	1
auto[2013265920:2147483647]	auto[1]	51	1			T17	1		T27	1		T56	1
auto[2147483648:2281701375]	auto[0]	46	1			T69	1		T94	1		T137	1
auto[2147483648:2281701375]	auto[1]	59	1			T47	1		T94	1		T90	1
auto[2281701376:2415919103]	auto[0]	50	1			T27	1		T57	3		T48	1
auto[2281701376:2415919103]	auto[1]	57	1			T115	1		T198	1		T244	1
auto[2415919104:2550136831]	auto[0]	58	1			T15	1		T21	1		T88	1
auto[2415919104:2550136831]	auto[1]	56	1			T117	1		T59	1		T5	1
auto[2550136832:2684354559]	auto[0]	48	1			T35	1		T56	1		T282	1
auto[2550136832:2684354559]	auto[1]	60	1			T57	1		T90	2		T137	1
auto[2684354560:2818572287]	auto[0]	43	1			T16	1		T97	1		T189	1
auto[2684354560:2818572287]	auto[1]	52	1			T3	1		T44	1		T5	1
auto[2818572288:2952790015]	auto[0]	53	1			T19	1		T57	1		T142	1
auto[2818572288:2952790015]	auto[1]	55	1			T16	1		T57	2		T247	1
auto[2952790016:3087007743]	auto[0]	45	1			T3	1		T44	1		T74	1
auto[2952790016:3087007743]	auto[1]	57	1			T88	1		T257	1		T403	1
auto[3087007744:3221225471]	auto[0]	70	1			T142	1		T247	1		T47	1
auto[3087007744:3221225471]	auto[1]	64	1			T111	1		T208	1		T259	1
auto[3221225472:3355443199]	auto[0]	43	1			T57	1		T90	1		T421	1
auto[3221225472:3355443199]	auto[1]	66	1			T44	1		T86	1		T5	1
auto[3355443200:3489660927]	auto[0]	60	1			T4	1		T16	1		T116	1
auto[3355443200:3489660927]	auto[1]	63	1			T115	1		T117	1		T57	1
auto[3489660928:3623878655]	auto[0]	43	1			T17	1		T71	1		T140	1
auto[3489660928:3623878655]	auto[1]	61	1			T16	1		T48	1		T72	1
auto[3623878656:3758096383]	auto[0]	52	1			T15	1		T16	1		T86	1
auto[3623878656:3758096383]	auto[1]	53	1			T57	1		T21	1		T90	1
auto[3758096384:3892314111]	auto[0]	46	1			T20	1		T57	1		T97	1
auto[3758096384:3892314111]	auto[1]	68	1			T35	1		T57	1		T5	1
auto[3892314112:4026531839]	auto[0]	50	1			T36	1		T5	1		T94	1
auto[3892314112:4026531839]	auto[1]	49	1			T56	1		T88	1		T199	1
auto[4026531840:4160749567]	auto[0]	57	1			T117	1		T247	1		T198	2
auto[4026531840:4160749567]	auto[1]	70	1			T56	1		T57	1		T47	1
auto[4160749568:4294967295]	auto[0]	59	1			T111	1		T47	2		T282	1
auto[4160749568:4294967295]	auto[1]	70	1			T44	1		T47	1		T91	1