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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1673 1 T3 2 T4 1 T15 3
auto[1] 1954 1 T3 1 T15 2 T16 1


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 120 1 T15 1 T35 1 T86 1
auto[134217728:268435455] 112 1 T16 1 T35 1 T117 1
auto[268435456:402653183] 116 1 T116 1 T57 1 T142 1
auto[402653184:536870911] 104 1 T4 1 T30 1 T35 1
auto[536870912:671088639] 119 1 T115 1 T57 1 T87 1
auto[671088640:805306367] 118 1 T19 1 T115 2 T27 1
auto[805306368:939524095] 111 1 T86 1 T21 1 T8 1
auto[939524096:1073741823] 89 1 T15 1 T57 1 T206 1
auto[1073741824:1207959551] 125 1 T3 1 T44 1 T206 1
auto[1207959552:1342177279] 108 1 T20 1 T8 1 T94 1
auto[1342177280:1476395007] 111 1 T16 1 T57 2 T5 2
auto[1476395008:1610612735] 122 1 T17 1 T36 2 T57 1
auto[1610612736:1744830463] 122 1 T35 1 T117 1 T56 1
auto[1744830464:1879048191] 123 1 T35 1 T115 1 T59 1
auto[1879048192:2013265919] 124 1 T17 1 T27 1 T56 1
auto[2013265920:2147483647] 114 1 T16 1 T17 1 T47 1
auto[2147483648:2281701375] 104 1 T15 1 T16 2 T35 1
auto[2281701376:2415919103] 118 1 T20 1 T111 1 T89 1
auto[2415919104:2550136831] 88 1 T88 1 T5 1 T42 1
auto[2550136832:2684354559] 123 1 T57 2 T5 1 T142 1
auto[2684354560:2818572287] 111 1 T19 1 T21 1 T111 1
auto[2818572288:2952790015] 114 1 T15 1 T16 1 T30 1
auto[2952790016:3087007743] 108 1 T35 1 T44 1 T57 1
auto[3087007744:3221225471] 110 1 T35 2 T57 1 T87 1
auto[3221225472:3355443199] 124 1 T19 1 T44 1 T115 1
auto[3355443200:3489660927] 92 1 T27 2 T36 1 T56 1
auto[3489660928:3623878655] 101 1 T15 1 T44 1 T206 1
auto[3623878656:3758096383] 117 1 T3 1 T44 1 T20 1
auto[3758096384:3892314111] 117 1 T117 1 T88 1 T142 1
auto[3892314112:4026531839] 120 1 T19 1 T35 1 T117 1
auto[4026531840:4160749567] 118 1 T27 1 T57 2 T21 1
auto[4160749568:4294967295] 124 1 T3 1 T20 1 T57 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 53 1 T282 1 T259 1 T74 1
auto[0:134217727] auto[1] 67 1 T15 1 T35 1 T86 1
auto[134217728:268435455] auto[0] 51 1 T16 1 T117 1 T20 1
auto[134217728:268435455] auto[1] 61 1 T35 1 T57 1 T94 1
auto[268435456:402653183] auto[0] 53 1 T116 1 T142 1 T282 1
auto[268435456:402653183] auto[1] 63 1 T57 1 T206 1 T97 1
auto[402653184:536870911] auto[0] 48 1 T4 1 T30 1 T35 1
auto[402653184:536870911] auto[1] 56 1 T20 1 T36 1 T142 1
auto[536870912:671088639] auto[0] 56 1 T87 1 T199 1 T47 1
auto[536870912:671088639] auto[1] 63 1 T115 1 T57 1 T283 1
auto[671088640:805306367] auto[0] 61 1 T27 1 T57 1 T38 1
auto[671088640:805306367] auto[1] 57 1 T19 1 T115 2 T56 1
auto[805306368:939524095] auto[0] 50 1 T21 1 T198 1 T22 1
auto[805306368:939524095] auto[1] 61 1 T86 1 T8 1 T259 1
auto[939524096:1073741823] auto[0] 42 1 T15 1 T57 1 T111 1
auto[939524096:1073741823] auto[1] 47 1 T206 1 T47 1 T91 1
auto[1073741824:1207959551] auto[0] 63 1 T3 1 T206 1 T47 1
auto[1073741824:1207959551] auto[1] 62 1 T44 1 T447 1 T72 1
auto[1207959552:1342177279] auto[0] 49 1 T20 1 T94 1 T447 1
auto[1207959552:1342177279] auto[1] 59 1 T8 1 T90 1 T331 1
auto[1342177280:1476395007] auto[0] 40 1 T16 1 T5 1 T93 1
auto[1342177280:1476395007] auto[1] 71 1 T57 2 T5 1 T142 1
auto[1476395008:1610612735] auto[0] 54 1 T17 1 T36 1 T57 1
auto[1476395008:1610612735] auto[1] 68 1 T36 1 T47 2 T282 1
auto[1610612736:1744830463] auto[0] 54 1 T56 1 T57 1 T95 1
auto[1610612736:1744830463] auto[1] 68 1 T35 1 T117 1 T188 1
auto[1744830464:1879048191] auto[0] 51 1 T35 1 T5 1 T198 1
auto[1744830464:1879048191] auto[1] 72 1 T115 1 T59 1 T87 1
auto[1879048192:2013265919] auto[0] 53 1 T17 1 T57 1 T97 1
auto[1879048192:2013265919] auto[1] 71 1 T27 1 T56 1 T199 1
auto[2013265920:2147483647] auto[0] 64 1 T16 1 T282 1 T94 1
auto[2013265920:2147483647] auto[1] 50 1 T17 1 T47 1 T71 1
auto[2147483648:2281701375] auto[0] 48 1 T15 1 T16 2 T282 1
auto[2147483648:2281701375] auto[1] 56 1 T35 1 T117 2 T48 1
auto[2281701376:2415919103] auto[0] 62 1 T111 1 T89 1 T94 1
auto[2281701376:2415919103] auto[1] 56 1 T20 1 T188 1 T345 1
auto[2415919104:2550136831] auto[0] 37 1 T5 1 T42 1 T447 1
auto[2415919104:2550136831] auto[1] 51 1 T88 1 T90 2 T72 1
auto[2550136832:2684354559] auto[0] 58 1 T57 2 T47 1 T201 1
auto[2550136832:2684354559] auto[1] 65 1 T5 1 T142 1 T89 1
auto[2684354560:2818572287] auto[0] 48 1 T19 1 T91 1 T138 1
auto[2684354560:2818572287] auto[1] 63 1 T21 1 T111 1 T247 1
auto[2818572288:2952790015] auto[0] 63 1 T15 1 T35 1 T57 1
auto[2818572288:2952790015] auto[1] 51 1 T16 1 T30 1 T116 1
auto[2952790016:3087007743] auto[0] 52 1 T35 1 T44 1 T69 1
auto[2952790016:3087007743] auto[1] 56 1 T57 1 T47 1 T90 1
auto[3087007744:3221225471] auto[0] 40 1 T35 2 T247 1 T345 1
auto[3087007744:3221225471] auto[1] 70 1 T57 1 T87 1 T88 1
auto[3221225472:3355443199] auto[0] 60 1 T19 1 T88 1 T247 1
auto[3221225472:3355443199] auto[1] 64 1 T44 1 T115 1 T27 1
auto[3355443200:3489660927] auto[0] 47 1 T27 1 T97 1 T247 1
auto[3355443200:3489660927] auto[1] 45 1 T27 1 T36 1 T56 1
auto[3489660928:3623878655] auto[0] 44 1 T111 1 T187 1 T189 1
auto[3489660928:3623878655] auto[1] 57 1 T15 1 T44 1 T206 1
auto[3623878656:3758096383] auto[0] 59 1 T3 1 T44 1 T97 1
auto[3623878656:3758096383] auto[1] 58 1 T20 1 T56 1 T208 1
auto[3758096384:3892314111] auto[0] 53 1 T142 1 T97 1 T244 1
auto[3758096384:3892314111] auto[1] 64 1 T117 1 T88 1 T206 1
auto[3892314112:4026531839] auto[0] 45 1 T35 1 T117 1 T247 1
auto[3892314112:4026531839] auto[1] 75 1 T19 1 T27 1 T59 1
auto[4026531840:4160749567] auto[0] 55 1 T27 1 T57 2 T21 1
auto[4026531840:4160749567] auto[1] 63 1 T136 1 T42 1 T90 1
auto[4160749568:4294967295] auto[0] 60 1 T97 1 T91 1 T90 1
auto[4160749568:4294967295] auto[1] 64 1 T3 1 T20 1 T57 1

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