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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7608 1 T3 6 T4 2 T15 1
auto[1] 278 1 T3 8 T86 1 T87 5



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 3174 1 T3 3 T4 1 T16 11
auto[134217728:268435455] 191 1 T3 1 T16 1 T19 1
auto[268435456:402653183] 184 1 T3 1 T116 1 T20 1
auto[402653184:536870911] 180 1 T3 1 T16 1 T30 1
auto[536870912:671088639] 166 1 T16 2 T35 1 T115 1
auto[671088640:805306367] 168 1 T44 1 T20 2 T27 1
auto[805306368:939524095] 156 1 T3 1 T27 2 T56 1
auto[939524096:1073741823] 139 1 T3 1 T16 1 T35 1
auto[1073741824:1207959551] 143 1 T3 1 T17 1 T117 3
auto[1207959552:1342177279] 145 1 T35 3 T86 1 T56 1
auto[1342177280:1476395007] 132 1 T19 1 T35 1 T115 1
auto[1476395008:1610612735] 159 1 T16 1 T35 1 T27 1
auto[1610612736:1744830463] 140 1 T115 1 T36 1 T57 1
auto[1744830464:1879048191] 148 1 T19 1 T8 1 T47 1
auto[1879048192:2013265919] 142 1 T3 1 T16 1 T35 1
auto[2013265920:2147483647] 146 1 T19 1 T35 1 T21 1
auto[2147483648:2281701375] 153 1 T3 1 T16 1 T19 1
auto[2281701376:2415919103] 148 1 T3 1 T17 1 T36 1
auto[2415919104:2550136831] 167 1 T19 1 T44 1 T57 1
auto[2550136832:2684354559] 142 1 T36 1 T21 1 T47 1
auto[2684354560:2818572287] 133 1 T19 2 T57 1 T59 1
auto[2818572288:2952790015] 132 1 T3 1 T15 1 T44 1
auto[2952790016:3087007743] 133 1 T19 1 T27 1 T21 1
auto[3087007744:3221225471] 142 1 T86 1 T27 1 T56 1
auto[3221225472:3355443199] 141 1 T17 1 T30 1 T35 1
auto[3355443200:3489660927] 146 1 T5 1 T142 1 T206 1
auto[3489660928:3623878655] 134 1 T19 1 T35 2 T20 1
auto[3623878656:3758096383] 189 1 T56 1 T57 1 T87 1
auto[3758096384:3892314111] 142 1 T16 1 T20 1 T56 1
auto[3892314112:4026531839] 157 1 T4 1 T115 1 T88 1
auto[4026531840:4160749567] 165 1 T19 1 T44 1 T27 1
auto[4160749568:4294967295] 149 1 T3 1 T111 1 T201 1



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 3163 1 T3 3 T4 1 T16 11
auto[0:134217727] auto[1] 11 1 T291 1 T418 1 T438 2
auto[134217728:268435455] auto[0] 184 1 T16 1 T19 1 T35 1
auto[134217728:268435455] auto[1] 7 1 T3 1 T72 1 T330 1
auto[268435456:402653183] auto[0] 177 1 T116 1 T20 1 T59 1
auto[268435456:402653183] auto[1] 7 1 T3 1 T302 1 T291 1
auto[402653184:536870911] auto[0] 174 1 T16 1 T30 1 T35 1
auto[402653184:536870911] auto[1] 6 1 T3 1 T353 1 T248 1
auto[536870912:671088639] auto[0] 146 1 T16 2 T35 1 T115 1
auto[536870912:671088639] auto[1] 20 1 T87 1 T89 1 T72 1
auto[671088640:805306367] auto[0] 160 1 T44 1 T20 2 T27 1
auto[671088640:805306367] auto[1] 8 1 T75 1 T248 1 T292 1
auto[805306368:939524095] auto[0] 146 1 T3 1 T27 2 T56 1
auto[805306368:939524095] auto[1] 10 1 T87 1 T75 1 T352 1
auto[939524096:1073741823] auto[0] 129 1 T3 1 T16 1 T35 1
auto[939524096:1073741823] auto[1] 10 1 T75 1 T353 1 T437 1
auto[1073741824:1207959551] auto[0] 134 1 T3 1 T17 1 T117 3
auto[1073741824:1207959551] auto[1] 9 1 T302 1 T248 1 T292 1
auto[1207959552:1342177279] auto[0] 134 1 T35 3 T86 1 T56 1
auto[1207959552:1342177279] auto[1] 11 1 T75 1 T270 2 T248 1
auto[1342177280:1476395007] auto[0] 120 1 T19 1 T35 1 T115 1
auto[1342177280:1476395007] auto[1] 12 1 T69 1 T353 1 T318 1
auto[1476395008:1610612735] auto[0] 147 1 T16 1 T35 1 T27 1
auto[1476395008:1610612735] auto[1] 12 1 T87 1 T416 1 T248 1
auto[1610612736:1744830463] auto[0] 135 1 T115 1 T36 1 T57 1
auto[1610612736:1744830463] auto[1] 5 1 T416 1 T419 1 T396 1
auto[1744830464:1879048191] auto[0] 136 1 T19 1 T8 1 T47 1
auto[1744830464:1879048191] auto[1] 12 1 T89 1 T416 1 T444 1
auto[1879048192:2013265919] auto[0] 130 1 T16 1 T35 1 T44 1
auto[1879048192:2013265919] auto[1] 12 1 T3 1 T69 1 T270 2
auto[2013265920:2147483647] auto[0] 140 1 T19 1 T35 1 T21 1
auto[2013265920:2147483647] auto[1] 6 1 T248 1 T258 1 T292 1
auto[2147483648:2281701375] auto[0] 143 1 T16 1 T19 1 T117 1
auto[2147483648:2281701375] auto[1] 10 1 T3 1 T89 2 T75 1
auto[2281701376:2415919103] auto[0] 141 1 T17 1 T36 1 T88 1
auto[2281701376:2415919103] auto[1] 7 1 T3 1 T302 1 T291 1
auto[2415919104:2550136831] auto[0] 160 1 T19 1 T44 1 T57 1
auto[2415919104:2550136831] auto[1] 7 1 T248 1 T444 1 T438 1
auto[2550136832:2684354559] auto[0] 132 1 T36 1 T21 1 T47 1
auto[2550136832:2684354559] auto[1] 10 1 T353 1 T318 1 T437 1
auto[2684354560:2818572287] auto[0] 129 1 T19 2 T57 1 T59 1
auto[2684354560:2818572287] auto[1] 4 1 T442 1 T440 1 T284 1
auto[2818572288:2952790015] auto[0] 127 1 T15 1 T44 1 T27 1
auto[2818572288:2952790015] auto[1] 5 1 T3 1 T442 1 T420 1
auto[2952790016:3087007743] auto[0] 131 1 T19 1 T27 1 T21 1
auto[2952790016:3087007743] auto[1] 2 1 T439 1 T450 1 - -
auto[3087007744:3221225471] auto[0] 132 1 T27 1 T56 1 T57 4
auto[3087007744:3221225471] auto[1] 10 1 T86 1 T69 1 T416 1
auto[3221225472:3355443199] auto[0] 136 1 T17 1 T30 1 T35 1
auto[3221225472:3355443199] auto[1] 5 1 T270 1 T318 1 T258 1
auto[3355443200:3489660927] auto[0] 136 1 T5 1 T142 1 T206 1
auto[3355443200:3489660927] auto[1] 10 1 T302 1 T248 1 T418 1
auto[3489660928:3623878655] auto[0] 124 1 T19 1 T35 2 T20 1
auto[3489660928:3623878655] auto[1] 10 1 T87 1 T89 1 T75 1
auto[3623878656:3758096383] auto[0] 178 1 T56 1 T57 1 T5 1
auto[3623878656:3758096383] auto[1] 11 1 T87 1 T89 1 T69 1
auto[3758096384:3892314111] auto[0] 139 1 T16 1 T20 1 T56 1
auto[3758096384:3892314111] auto[1] 3 1 T270 1 T436 1 T373 1
auto[3892314112:4026531839] auto[0] 146 1 T4 1 T115 1 T88 1
auto[3892314112:4026531839] auto[1] 11 1 T69 1 T302 1 T258 1
auto[4026531840:4160749567] auto[0] 157 1 T19 1 T44 1 T27 1
auto[4026531840:4160749567] auto[1] 8 1 T89 1 T248 1 T426 1
auto[4160749568:4294967295] auto[0] 142 1 T111 1 T201 1 T140 1
auto[4160749568:4294967295] auto[1] 7 1 T3 1 T69 1 T437 1

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