| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.74 | 99.03 | 97.99 | 98.30 | 100.00 | 99.01 | 98.63 | 91.22 |
| T1006 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3763109711 | Oct 09 02:31:58 PM UTC 24 | Oct 09 02:32:01 PM UTC 24 | 59252077 ps | ||
| T1007 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.4277509238 | Oct 09 02:31:54 PM UTC 24 | Oct 09 02:32:02 PM UTC 24 | 700468224 ps | ||
| T1008 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_intr_test.974751237 | Oct 09 02:32:00 PM UTC 24 | Oct 09 02:32:03 PM UTC 24 | 14688852 ps | ||
| T1009 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_errors.360103454 | Oct 09 02:31:59 PM UTC 24 | Oct 09 02:32:03 PM UTC 24 | 147002276 ps | ||
| T1010 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1062920251 | Oct 09 02:31:55 PM UTC 24 | Oct 09 02:32:03 PM UTC 24 | 275616812 ps | ||
| T1011 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_intg_err.4238348818 | Oct 09 02:31:55 PM UTC 24 | Oct 09 02:32:04 PM UTC 24 | 281910322 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3439592398 | Oct 09 02:31:45 PM UTC 24 | Oct 09 02:32:04 PM UTC 24 | 2727620309 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.349878590 | Oct 09 02:31:58 PM UTC 24 | Oct 09 02:32:04 PM UTC 24 | 531866803 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_rw.1109082319 | Oct 09 02:32:02 PM UTC 24 | Oct 09 02:32:04 PM UTC 24 | 14543915 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4019435605 | Oct 09 02:32:03 PM UTC 24 | Oct 09 02:32:06 PM UTC 24 | 68384357 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2801053720 | Oct 09 02:31:59 PM UTC 24 | Oct 09 02:32:06 PM UTC 24 | 819939249 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.164614192 | Oct 09 02:32:03 PM UTC 24 | Oct 09 02:32:07 PM UTC 24 | 217905573 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.2027825873 | Oct 09 02:32:06 PM UTC 24 | Oct 09 02:32:08 PM UTC 24 | 19584902 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.4121382586 | Oct 09 02:32:04 PM UTC 24 | Oct 09 02:32:08 PM UTC 24 | 475698622 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.866020750 | Oct 09 02:32:04 PM UTC 24 | Oct 09 02:32:08 PM UTC 24 | 127218847 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.2294334815 | Oct 09 02:32:06 PM UTC 24 | Oct 09 02:32:09 PM UTC 24 | 167025771 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3817296335 | Oct 09 02:32:06 PM UTC 24 | Oct 09 02:32:11 PM UTC 24 | 86313179 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.1967978163 | Oct 09 02:32:04 PM UTC 24 | Oct 09 02:32:11 PM UTC 24 | 392180301 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1149064462 | Oct 09 02:32:07 PM UTC 24 | Oct 09 02:32:11 PM UTC 24 | 235981386 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3076305914 | Oct 09 02:32:17 PM UTC 24 | Oct 09 02:32:21 PM UTC 24 | 78533998 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1061704657 | Oct 09 02:32:07 PM UTC 24 | Oct 09 02:32:12 PM UTC 24 | 62258083 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.2694767606 | Oct 09 02:32:08 PM UTC 24 | Oct 09 02:32:12 PM UTC 24 | 38459450 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.15729650 | Oct 09 02:32:00 PM UTC 24 | Oct 09 02:32:12 PM UTC 24 | 258641220 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.4151279533 | Oct 09 02:32:10 PM UTC 24 | Oct 09 02:32:12 PM UTC 24 | 13281296 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.3363315800 | Oct 09 02:32:10 PM UTC 24 | Oct 09 02:32:13 PM UTC 24 | 205928154 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1550281691 | Oct 09 02:32:04 PM UTC 24 | Oct 09 02:32:13 PM UTC 24 | 293101702 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2540609894 | Oct 09 02:32:08 PM UTC 24 | Oct 09 02:32:14 PM UTC 24 | 123588337 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.1661954445 | Oct 09 02:32:10 PM UTC 24 | Oct 09 02:32:16 PM UTC 24 | 99505766 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3898559330 | Oct 09 02:32:11 PM UTC 24 | Oct 09 02:32:17 PM UTC 24 | 495252561 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.35933075 | Oct 09 02:32:13 PM UTC 24 | Oct 09 02:32:17 PM UTC 24 | 423042485 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.689347325 | Oct 09 02:32:13 PM UTC 24 | Oct 09 02:32:17 PM UTC 24 | 61154462 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.816653569 | Oct 09 02:32:14 PM UTC 24 | Oct 09 02:32:18 PM UTC 24 | 40176488 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.228005368 | Oct 09 02:32:13 PM UTC 24 | Oct 09 02:32:18 PM UTC 24 | 1591794001 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.2968803908 | Oct 09 02:32:14 PM UTC 24 | Oct 09 02:32:18 PM UTC 24 | 56460676 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.4153326510 | Oct 09 02:32:15 PM UTC 24 | Oct 09 02:32:18 PM UTC 24 | 118857353 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2898729115 | Oct 09 02:32:15 PM UTC 24 | Oct 09 02:32:19 PM UTC 24 | 258837996 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3670329945 | Oct 09 02:32:13 PM UTC 24 | Oct 09 02:32:20 PM UTC 24 | 117665544 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.3063686246 | Oct 09 02:32:14 PM UTC 24 | Oct 09 02:32:21 PM UTC 24 | 100268923 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.2696588628 | Oct 09 02:32:19 PM UTC 24 | Oct 09 02:32:21 PM UTC 24 | 100790751 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.2643610904 | Oct 09 02:32:19 PM UTC 24 | Oct 09 02:32:22 PM UTC 24 | 12490232 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.3741482524 | Oct 09 02:32:18 PM UTC 24 | Oct 09 02:32:23 PM UTC 24 | 184002664 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.1959784761 | Oct 09 02:32:19 PM UTC 24 | Oct 09 02:32:24 PM UTC 24 | 185500038 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2236791791 | Oct 09 02:32:20 PM UTC 24 | Oct 09 02:32:24 PM UTC 24 | 62982394 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.4079899948 | Oct 09 02:32:20 PM UTC 24 | Oct 09 02:32:24 PM UTC 24 | 108839105 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.3389826331 | Oct 09 02:32:22 PM UTC 24 | Oct 09 02:32:24 PM UTC 24 | 13579171 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.685289548 | Oct 09 02:32:20 PM UTC 24 | Oct 09 02:32:25 PM UTC 24 | 72281758 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.3005070168 | Oct 09 02:32:22 PM UTC 24 | Oct 09 02:32:25 PM UTC 24 | 22321790 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.3633955109 | Oct 09 02:32:22 PM UTC 24 | Oct 09 02:32:26 PM UTC 24 | 460284838 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3570191457 | Oct 09 02:32:23 PM UTC 24 | Oct 09 02:32:27 PM UTC 24 | 23202054 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.2067024954 | Oct 09 02:32:26 PM UTC 24 | Oct 09 02:32:28 PM UTC 24 | 27958514 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1056377609 | Oct 09 02:32:22 PM UTC 24 | Oct 09 02:32:28 PM UTC 24 | 291076803 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3893805359 | Oct 09 02:32:18 PM UTC 24 | Oct 09 02:32:28 PM UTC 24 | 305301982 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.3474801240 | Oct 09 02:32:22 PM UTC 24 | Oct 09 02:32:29 PM UTC 24 | 104151127 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3702548160 | Oct 09 02:32:25 PM UTC 24 | Oct 09 02:32:29 PM UTC 24 | 29912151 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.2153718641 | Oct 09 02:32:25 PM UTC 24 | Oct 09 02:32:29 PM UTC 24 | 57076893 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3563602247 | Oct 09 02:32:25 PM UTC 24 | Oct 09 02:32:29 PM UTC 24 | 183339724 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.2863101738 | Oct 09 02:32:27 PM UTC 24 | Oct 09 02:32:30 PM UTC 24 | 35050140 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.3304423386 | Oct 09 02:32:27 PM UTC 24 | Oct 09 02:32:30 PM UTC 24 | 61410538 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.1938021865 | Oct 09 02:32:25 PM UTC 24 | Oct 09 02:32:30 PM UTC 24 | 146236258 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1823709943 | Oct 09 02:32:27 PM UTC 24 | Oct 09 02:32:31 PM UTC 24 | 96951045 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.3022537114 | Oct 09 02:32:29 PM UTC 24 | Oct 09 02:32:31 PM UTC 24 | 39924550 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.551830844 | Oct 09 02:32:29 PM UTC 24 | Oct 09 02:32:31 PM UTC 24 | 10180080 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2007752554 | Oct 09 02:32:27 PM UTC 24 | Oct 09 02:32:32 PM UTC 24 | 345466374 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.997421692 | Oct 09 02:32:31 PM UTC 24 | Oct 09 02:32:33 PM UTC 24 | 14543480 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.2112613214 | Oct 09 02:32:31 PM UTC 24 | Oct 09 02:32:33 PM UTC 24 | 9297234 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.1660103771 | Oct 09 02:32:31 PM UTC 24 | Oct 09 02:32:33 PM UTC 24 | 9392817 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.2514931246 | Oct 09 02:32:31 PM UTC 24 | Oct 09 02:32:33 PM UTC 24 | 29583021 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.2538444735 | Oct 09 02:32:31 PM UTC 24 | Oct 09 02:32:33 PM UTC 24 | 16930110 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.593897353 | Oct 09 02:32:31 PM UTC 24 | Oct 09 02:32:33 PM UTC 24 | 8343620 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.3360624183 | Oct 09 02:32:33 PM UTC 24 | Oct 09 02:32:35 PM UTC 24 | 13114782 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.960844652 | Oct 09 02:32:33 PM UTC 24 | Oct 09 02:32:35 PM UTC 24 | 18599537 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.1729517118 | Oct 09 02:32:33 PM UTC 24 | Oct 09 02:32:35 PM UTC 24 | 14787981 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.4260645851 | Oct 09 02:32:33 PM UTC 24 | Oct 09 02:32:35 PM UTC 24 | 22087514 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.3481764380 | Oct 09 02:32:33 PM UTC 24 | Oct 09 02:32:35 PM UTC 24 | 45143299 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1063904661 | Oct 09 02:32:25 PM UTC 24 | Oct 09 02:32:36 PM UTC 24 | 645778831 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.2618457301 | Oct 09 02:32:35 PM UTC 24 | Oct 09 02:32:37 PM UTC 24 | 33917735 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.3519396631 | Oct 09 02:32:35 PM UTC 24 | Oct 09 02:32:37 PM UTC 24 | 54878751 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.2016733024 | Oct 09 02:32:35 PM UTC 24 | Oct 09 02:32:37 PM UTC 24 | 25881313 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.2638455094 | Oct 09 02:32:35 PM UTC 24 | Oct 09 02:32:37 PM UTC 24 | 42355215 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.3055699003 | Oct 09 02:32:35 PM UTC 24 | Oct 09 02:32:38 PM UTC 24 | 9488820 ps | ||
| T1081 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.1519996692 | Oct 09 02:32:35 PM UTC 24 | Oct 09 02:32:38 PM UTC 24 | 51922323 ps | ||
| T1082 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.1840590336 | Oct 09 02:32:35 PM UTC 24 | Oct 09 02:32:38 PM UTC 24 | 21702141 ps | ||
| T1083 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.3652498735 | Oct 09 02:32:37 PM UTC 24 | Oct 09 02:32:40 PM UTC 24 | 31635400 ps | ||
| T1084 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.816755570 | Oct 09 02:32:37 PM UTC 24 | Oct 09 02:32:40 PM UTC 24 | 67185609 ps | ||
| T1085 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.4232081850 | Oct 09 02:32:38 PM UTC 24 | Oct 09 02:32:40 PM UTC 24 | 11612924 ps | ||
| T1086 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.4150173273 | Oct 09 02:32:37 PM UTC 24 | Oct 09 02:32:40 PM UTC 24 | 55356976 ps | ||
| T1087 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.660653343 | Oct 09 02:32:37 PM UTC 24 | Oct 09 02:32:40 PM UTC 24 | 11661427 ps | ||
| T1088 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.16111881 | Oct 09 02:32:38 PM UTC 24 | Oct 09 02:32:40 PM UTC 24 | 24624492 ps | ||
| T1089 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.1635295958 | Oct 09 02:32:39 PM UTC 24 | Oct 09 02:32:42 PM UTC 24 | 31960899 ps | ||
| T1090 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.1644584115 | Oct 09 02:32:40 PM UTC 24 | Oct 09 02:32:42 PM UTC 24 | 13431453 ps | ||
| T1091 | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.4262205805 | Oct 09 02:32:40 PM UTC 24 | Oct 09 02:32:42 PM UTC 24 | 27233207 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/0.keymgr_sw_invalid_input.3927888532 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 166336854 ps |
| CPU time | 7.01 seconds |
| Started | Oct 09 10:11:08 AM UTC 24 |
| Finished | Oct 09 10:11:17 AM UTC 24 |
| Peak memory | 225588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927888532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3927888532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all_with_rand_reset.3693918669 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1751935093 ps |
| CPU time | 14.48 seconds |
| Started | Oct 09 10:11:15 AM UTC 24 |
| Finished | Oct 09 10:11:31 AM UTC 24 |
| Peak memory | 230040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3693918669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr _stress_all_with_rand_reset.3693918669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all.1401551975 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 33828480473 ps |
| CPU time | 62.5 seconds |
| Started | Oct 09 10:11:59 AM UTC 24 |
| Finished | Oct 09 10:13:03 AM UTC 24 |
| Peak memory | 231748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401551975 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1401551975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/0.keymgr_kmac_rsp_err.391106289 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 200946473 ps |
| CPU time | 7.01 seconds |
| Started | Oct 09 10:11:10 AM UTC 24 |
| Finished | Oct 09 10:11:18 AM UTC 24 |
| Peak memory | 223484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391106289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.391106289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/0.keymgr_sec_cm.1056135093 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 2448344223 ps |
| CPU time | 8.28 seconds |
| Started | Oct 09 10:11:16 AM UTC 24 |
| Finished | Oct 09 10:11:26 AM UTC 24 |
| Peak memory | 259536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056135093 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1056135093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all.2225691626 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 710421962 ps |
| CPU time | 16.73 seconds |
| Started | Oct 09 10:11:14 AM UTC 24 |
| Finished | Oct 09 10:11:32 AM UTC 24 |
| Peak memory | 231560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225691626 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2225691626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all_with_rand_reset.3946630797 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 539541958 ps |
| CPU time | 21.46 seconds |
| Started | Oct 09 10:11:41 AM UTC 24 |
| Finished | Oct 09 10:12:04 AM UTC 24 |
| Peak memory | 231868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3946630797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr _stress_all_with_rand_reset.3946630797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/3.keymgr_stress_all.2197751193 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 4548788386 ps |
| CPU time | 12.35 seconds |
| Started | Oct 09 10:11:50 AM UTC 24 |
| Finished | Oct 09 10:12:04 AM UTC 24 |
| Peak memory | 225736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197751193 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2197751193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all.1510586507 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 998595396 ps |
| CPU time | 14.08 seconds |
| Started | Oct 09 10:12:32 AM UTC 24 |
| Finished | Oct 09 10:12:48 AM UTC 24 |
| Peak memory | 227568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510586507 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1510586507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/2.keymgr_custom_cm.841116227 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 602250375 ps |
| CPU time | 6 seconds |
| Started | Oct 09 10:11:38 AM UTC 24 |
| Finished | Oct 09 10:11:45 AM UTC 24 |
| Peak memory | 217732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841116227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.841116227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/4.keymgr_lc_disable.1685334084 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1948968067 ps |
| CPU time | 12.25 seconds |
| Started | Oct 09 10:11:55 AM UTC 24 |
| Finished | Oct 09 10:12:09 AM UTC 24 |
| Peak memory | 217476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685334084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1685334084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/3.keymgr_cfg_regwen.2972910657 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 791362324 ps |
| CPU time | 11.34 seconds |
| Started | Oct 09 10:11:45 AM UTC 24 |
| Finished | Oct 09 10:11:58 AM UTC 24 |
| Peak memory | 223732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972910657 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2972910657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2827219107 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 77348242 ps |
| CPU time | 5.51 seconds |
| Started | Oct 09 02:30:19 PM UTC 24 |
| Finished | Oct 09 02:30:25 PM UTC 24 |
| Peak memory | 226116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827219107 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors_with_csr_rw.2827219107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all_with_rand_reset.2797579068 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 569764654 ps |
| CPU time | 18.07 seconds |
| Started | Oct 09 10:11:30 AM UTC 24 |
| Finished | Oct 09 10:11:50 AM UTC 24 |
| Peak memory | 230004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2797579068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr _stress_all_with_rand_reset.2797579068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/27.keymgr_cfg_regwen.2911948788 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 2839850099 ps |
| CPU time | 15.18 seconds |
| Started | Oct 09 10:15:07 AM UTC 24 |
| Finished | Oct 09 10:15:24 AM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911948788 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2911948788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/27.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/0.keymgr_cfg_regwen.242622590 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 82972082 ps |
| CPU time | 4.01 seconds |
| Started | Oct 09 10:11:04 AM UTC 24 |
| Finished | Oct 09 10:11:10 AM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242622590 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.242622590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all_with_rand_reset.3327348294 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 405367957 ps |
| CPU time | 14.9 seconds |
| Started | Oct 09 10:12:13 AM UTC 24 |
| Finished | Oct 09 10:12:29 AM UTC 24 |
| Peak memory | 231740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3327348294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr _stress_all_with_rand_reset.3327348294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/1.keymgr_hwsw_invalid_input.2025430760 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 142153893 ps |
| CPU time | 3.63 seconds |
| Started | Oct 09 10:11:25 AM UTC 24 |
| Finished | Oct 09 10:11:30 AM UTC 24 |
| Peak memory | 217608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025430760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2025430760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/20.keymgr_cfg_regwen.2764381846 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 976933121 ps |
| CPU time | 13.5 seconds |
| Started | Oct 09 10:14:18 AM UTC 24 |
| Finished | Oct 09 10:14:33 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764381846 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2764381846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/20.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/5.keymgr_kmac_rsp_err.4057362809 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 131676851 ps |
| CPU time | 7.67 seconds |
| Started | Oct 09 10:12:04 AM UTC 24 |
| Finished | Oct 09 10:12:13 AM UTC 24 |
| Peak memory | 231488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057362809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.4057362809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all.169962534 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1280074381 ps |
| CPU time | 55.52 seconds |
| Started | Oct 09 10:12:22 AM UTC 24 |
| Finished | Oct 09 10:13:19 AM UTC 24 |
| Peak memory | 230112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169962534 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.169962534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1556907600 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 232115401 ps |
| CPU time | 8.92 seconds |
| Started | Oct 09 02:30:18 PM UTC 24 |
| Finished | Oct 09 02:30:28 PM UTC 24 |
| Peak memory | 225804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556907600 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors.1556907600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/34.keymgr_cfg_regwen.1305839047 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 3569690297 ps |
| CPU time | 39.48 seconds |
| Started | Oct 09 10:16:01 AM UTC 24 |
| Finished | Oct 09 10:16:42 AM UTC 24 |
| Peak memory | 225532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305839047 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1305839047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/34.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/9.keymgr_custom_cm.2366061145 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 157482045 ps |
| CPU time | 3.92 seconds |
| Started | Oct 09 10:12:42 AM UTC 24 |
| Finished | Oct 09 10:12:47 AM UTC 24 |
| Peak memory | 217408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366061145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2366061145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/1.keymgr_cfg_regwen.1565151715 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 48890405 ps |
| CPU time | 3.99 seconds |
| Started | Oct 09 10:11:22 AM UTC 24 |
| Finished | Oct 09 10:11:27 AM UTC 24 |
| Peak memory | 223468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565151715 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1565151715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all.92905274 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 7403241023 ps |
| CPU time | 48.02 seconds |
| Started | Oct 09 10:12:56 AM UTC 24 |
| Finished | Oct 09 10:13:45 AM UTC 24 |
| Peak memory | 231764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92905274 -assert nopostproc +UVM_TESTNAME=ke ymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.92905274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/0.keymgr_sync_async_fault_cross.9293351 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 140107289 ps |
| CPU time | 3.64 seconds |
| Started | Oct 09 10:11:12 AM UTC 24 |
| Finished | Oct 09 10:11:17 AM UTC 24 |
| Peak memory | 219376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9293351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=k eymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.9293351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/2.keymgr_direct_to_disabled.2767196093 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 59238839 ps |
| CPU time | 3.62 seconds |
| Started | Oct 09 10:11:36 AM UTC 24 |
| Finished | Oct 09 10:11:40 AM UTC 24 |
| Peak memory | 217424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767196093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2767196093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/22.keymgr_custom_cm.3416128120 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 46498089 ps |
| CPU time | 3.76 seconds |
| Started | Oct 09 10:14:35 AM UTC 24 |
| Finished | Oct 09 10:14:40 AM UTC 24 |
| Peak memory | 231944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416128120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3416128120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/22.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/8.keymgr_custom_cm.277340921 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 97332003 ps |
| CPU time | 5.16 seconds |
| Started | Oct 09 10:12:30 AM UTC 24 |
| Finished | Oct 09 10:12:37 AM UTC 24 |
| Peak memory | 223628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277340921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.277340921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/40.keymgr_cfg_regwen.3997107065 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 295700024 ps |
| CPU time | 16.41 seconds |
| Started | Oct 09 10:16:48 AM UTC 24 |
| Finished | Oct 09 10:17:06 AM UTC 24 |
| Peak memory | 225380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997107065 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3997107065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/40.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/7.keymgr_cfg_regwen.1194487869 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 2163446591 ps |
| CPU time | 17.13 seconds |
| Started | Oct 09 10:12:18 AM UTC 24 |
| Finished | Oct 09 10:12:36 AM UTC 24 |
| Peak memory | 225716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194487869 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1194487869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/41.keymgr_custom_cm.4075965484 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 74663632 ps |
| CPU time | 4.86 seconds |
| Started | Oct 09 10:16:57 AM UTC 24 |
| Finished | Oct 09 10:17:03 AM UTC 24 |
| Peak memory | 231832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075965484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.4075965484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/41.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/38.keymgr_hwsw_invalid_input.1477054341 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 822252561 ps |
| CPU time | 5.98 seconds |
| Started | Oct 09 10:16:33 AM UTC 24 |
| Finished | Oct 09 10:16:40 AM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477054341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1477054341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/38.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/8.keymgr_hwsw_invalid_input.3933526395 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 252841328 ps |
| CPU time | 7.03 seconds |
| Started | Oct 09 10:12:29 AM UTC 24 |
| Finished | Oct 09 10:12:37 AM UTC 24 |
| Peak memory | 231508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933526395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3933526395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all_with_rand_reset.1890454796 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1066399802 ps |
| CPU time | 23.72 seconds |
| Started | Oct 09 10:12:32 AM UTC 24 |
| Finished | Oct 09 10:12:58 AM UTC 24 |
| Peak memory | 231736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1890454796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr _stress_all_with_rand_reset.1890454796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all.2186680541 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 500037072 ps |
| CPU time | 10.15 seconds |
| Started | Oct 09 10:11:29 AM UTC 24 |
| Finished | Oct 09 10:11:40 AM UTC 24 |
| Peak memory | 229760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186680541 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2186680541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/43.keymgr_cfg_regwen.162881918 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 49801898 ps |
| CPU time | 4.49 seconds |
| Started | Oct 09 10:17:09 AM UTC 24 |
| Finished | Oct 09 10:17:15 AM UTC 24 |
| Peak memory | 225776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162881918 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.162881918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/43.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/10.keymgr_kmac_rsp_err.1368882327 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 680870390 ps |
| CPU time | 6.05 seconds |
| Started | Oct 09 10:12:54 AM UTC 24 |
| Finished | Oct 09 10:13:02 AM UTC 24 |
| Peak memory | 223812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368882327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1368882327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/45.keymgr_cfg_regwen.226384304 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 462379205 ps |
| CPU time | 6.83 seconds |
| Started | Oct 09 10:17:24 AM UTC 24 |
| Finished | Oct 09 10:17:32 AM UTC 24 |
| Peak memory | 231604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226384304 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.226384304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/45.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all_with_rand_reset.3425866397 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 9338972282 ps |
| CPU time | 25.86 seconds |
| Started | Oct 09 10:12:22 AM UTC 24 |
| Finished | Oct 09 10:12:49 AM UTC 24 |
| Peak memory | 231448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3425866397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr _stress_all_with_rand_reset.3425866397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/1.keymgr_custom_cm.3668705722 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 125792891 ps |
| CPU time | 4.83 seconds |
| Started | Oct 09 10:11:27 AM UTC 24 |
| Finished | Oct 09 10:11:33 AM UTC 24 |
| Peak memory | 217664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668705722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3668705722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/0.keymgr_alert_test.3007093846 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 11447939 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 10:11:17 AM UTC 24 |
| Finished | Oct 09 10:11:20 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007093846 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3007093846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all.2789598609 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1892723190 ps |
| CPU time | 34.03 seconds |
| Started | Oct 09 10:14:22 AM UTC 24 |
| Finished | Oct 09 10:14:57 AM UTC 24 |
| Peak memory | 231544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789598609 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2789598609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/20.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_intg_err.1817725897 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 191157926 ps |
| CPU time | 7.61 seconds |
| Started | Oct 09 02:30:29 PM UTC 24 |
| Finished | Oct 09 02:30:38 PM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817725897 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.1817725897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/46.keymgr_cfg_regwen.4022531682 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 195480678 ps |
| CPU time | 4.55 seconds |
| Started | Oct 09 10:17:31 AM UTC 24 |
| Finished | Oct 09 10:17:37 AM UTC 24 |
| Peak memory | 231604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022531682 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.4022531682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/46.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/33.keymgr_hwsw_invalid_input.364834526 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 624080111 ps |
| CPU time | 4.44 seconds |
| Started | Oct 09 10:15:55 AM UTC 24 |
| Finished | Oct 09 10:16:01 AM UTC 24 |
| Peak memory | 225604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364834526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.364834526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/33.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_otbn.2299697279 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 177191162 ps |
| CPU time | 5.45 seconds |
| Started | Oct 09 10:11:21 AM UTC 24 |
| Finished | Oct 09 10:11:27 AM UTC 24 |
| Peak memory | 217320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299697279 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2299697279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/29.keymgr_cfg_regwen.613284900 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 801268307 ps |
| CPU time | 49.3 seconds |
| Started | Oct 09 10:15:21 AM UTC 24 |
| Finished | Oct 09 10:16:12 AM UTC 24 |
| Peak memory | 225864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613284900 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.613284900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/29.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/25.keymgr_custom_cm.1064273363 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 583589456 ps |
| CPU time | 3.76 seconds |
| Started | Oct 09 10:14:55 AM UTC 24 |
| Finished | Oct 09 10:15:00 AM UTC 24 |
| Peak memory | 231908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064273363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1064273363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/25.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/0.keymgr_random.656207083 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 4720884213 ps |
| CPU time | 40.24 seconds |
| Started | Oct 09 10:11:03 AM UTC 24 |
| Finished | Oct 09 10:11:46 AM UTC 24 |
| Peak memory | 223808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656207083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.656207083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/19.keymgr_stress_all.2083522132 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1667427458 ps |
| CPU time | 38.09 seconds |
| Started | Oct 09 10:14:14 AM UTC 24 |
| Finished | Oct 09 10:14:54 AM UTC 24 |
| Peak memory | 229612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083522132 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2083522132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/24.keymgr_cfg_regwen.2077536139 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 102430976 ps |
| CPU time | 5.2 seconds |
| Started | Oct 09 10:14:45 AM UTC 24 |
| Finished | Oct 09 10:14:52 AM UTC 24 |
| Peak memory | 225664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077536139 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2077536139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/24.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/7.keymgr_kmac_rsp_err.1131433248 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 63585711 ps |
| CPU time | 3.4 seconds |
| Started | Oct 09 10:12:19 AM UTC 24 |
| Finished | Oct 09 10:12:24 AM UTC 24 |
| Peak memory | 223484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131433248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1131433248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/12.keymgr_kmac_rsp_err.509427728 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 1193085246 ps |
| CPU time | 9.97 seconds |
| Started | Oct 09 10:13:11 AM UTC 24 |
| Finished | Oct 09 10:13:22 AM UTC 24 |
| Peak memory | 231560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509427728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.509427728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_otbn.1929646595 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 401341364 ps |
| CPU time | 13.57 seconds |
| Started | Oct 09 10:11:03 AM UTC 24 |
| Finished | Oct 09 10:11:18 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929646595 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1929646595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all_with_rand_reset.2298010508 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1088517155 ps |
| CPU time | 16.25 seconds |
| Started | Oct 09 10:13:13 AM UTC 24 |
| Finished | Oct 09 10:13:31 AM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2298010508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymg r_stress_all_with_rand_reset.2298010508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/39.keymgr_custom_cm.4045656631 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 321783896 ps |
| CPU time | 8.53 seconds |
| Started | Oct 09 10:16:44 AM UTC 24 |
| Finished | Oct 09 10:16:54 AM UTC 24 |
| Peak memory | 227772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045656631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.4045656631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/39.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/12.keymgr_sync_async_fault_cross.1617198297 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 144838162 ps |
| CPU time | 2.85 seconds |
| Started | Oct 09 10:13:12 AM UTC 24 |
| Finished | Oct 09 10:13:16 AM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617198297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1617198297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_intg_err.1049975804 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 455957083 ps |
| CPU time | 5.01 seconds |
| Started | Oct 09 02:31:47 PM UTC 24 |
| Finished | Oct 09 02:31:53 PM UTC 24 |
| Peak memory | 225488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049975804 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err.1049975804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.1967978163 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 392180301 ps |
| CPU time | 5.71 seconds |
| Started | Oct 09 02:32:04 PM UTC 24 |
| Finished | Oct 09 02:32:11 PM UTC 24 |
| Peak memory | 225432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967978163 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err.1967978163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.3063686246 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 100268923 ps |
| CPU time | 4.8 seconds |
| Started | Oct 09 02:32:14 PM UTC 24 |
| Finished | Oct 09 02:32:21 PM UTC 24 |
| Peak memory | 225560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063686246 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err.3063686246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/2.keymgr_sec_cm.2289279310 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 796841273 ps |
| CPU time | 16.28 seconds |
| Started | Oct 09 10:11:42 AM UTC 24 |
| Finished | Oct 09 10:11:59 AM UTC 24 |
| Peak memory | 261520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289279310 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2289279310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/26.keymgr_custom_cm.3293758298 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 412605704 ps |
| CPU time | 6.48 seconds |
| Started | Oct 09 10:15:02 AM UTC 24 |
| Finished | Oct 09 10:15:10 AM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293758298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3293758298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/26.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/27.keymgr_custom_cm.1511387767 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 127967516 ps |
| CPU time | 4.73 seconds |
| Started | Oct 09 10:15:10 AM UTC 24 |
| Finished | Oct 09 10:15:16 AM UTC 24 |
| Peak memory | 231748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511387767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1511387767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/27.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/15.keymgr_cfg_regwen.4203610127 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 296288589 ps |
| CPU time | 6.44 seconds |
| Started | Oct 09 10:13:37 AM UTC 24 |
| Finished | Oct 09 10:13:45 AM UTC 24 |
| Peak memory | 223608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203610127 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.4203610127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/19.keymgr_stress_all_with_rand_reset.3003020789 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 1561304174 ps |
| CPU time | 25.17 seconds |
| Started | Oct 09 10:14:14 AM UTC 24 |
| Finished | Oct 09 10:14:41 AM UTC 24 |
| Peak memory | 231736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3003020789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymg r_stress_all_with_rand_reset.3003020789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/20.keymgr_kmac_rsp_err.2580406525 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 913462530 ps |
| CPU time | 8.73 seconds |
| Started | Oct 09 10:14:21 AM UTC 24 |
| Finished | Oct 09 10:14:30 AM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580406525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2580406525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/20.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_aes.1553838891 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 84591613 ps |
| CPU time | 4.12 seconds |
| Started | Oct 09 10:11:44 AM UTC 24 |
| Finished | Oct 09 10:11:49 AM UTC 24 |
| Peak memory | 215616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553838891 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1553838891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/32.keymgr_stress_all.319676048 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 5258913914 ps |
| CPU time | 49.41 seconds |
| Started | Oct 09 10:15:50 AM UTC 24 |
| Finished | Oct 09 10:16:41 AM UTC 24 |
| Peak memory | 231632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319676048 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.319676048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/32.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all.2517682181 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 2245314877 ps |
| CPU time | 69 seconds |
| Started | Oct 09 10:16:36 AM UTC 24 |
| Finished | Oct 09 10:17:47 AM UTC 24 |
| Peak memory | 227628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517682181 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2517682181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/38.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_kmac.1152518742 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 187721388 ps |
| CPU time | 4.01 seconds |
| Started | Oct 09 10:12:24 AM UTC 24 |
| Finished | Oct 09 10:12:29 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152518742 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1152518742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/19.keymgr_sync_async_fault_cross.2604160703 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 742758271 ps |
| CPU time | 5.04 seconds |
| Started | Oct 09 10:14:14 AM UTC 24 |
| Finished | Oct 09 10:14:20 AM UTC 24 |
| Peak memory | 217656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604160703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2604160703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/1.keymgr_kmac_rsp_err.3971337217 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 108558095 ps |
| CPU time | 4.77 seconds |
| Started | Oct 09 10:11:25 AM UTC 24 |
| Finished | Oct 09 10:11:31 AM UTC 24 |
| Peak memory | 229756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971337217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3971337217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all_with_rand_reset.4278249283 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 193941496 ps |
| CPU time | 12.09 seconds |
| Started | Oct 09 10:12:56 AM UTC 24 |
| Finished | Oct 09 10:13:09 AM UTC 24 |
| Peak memory | 231644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4278249283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymg r_stress_all_with_rand_reset.4278249283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/13.keymgr_kmac_rsp_err.22337467 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 51294382 ps |
| CPU time | 3.03 seconds |
| Started | Oct 09 10:13:20 AM UTC 24 |
| Finished | Oct 09 10:13:25 AM UTC 24 |
| Peak memory | 229704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22337467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.22337467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/2.keymgr_sync_async_fault_cross.1916273117 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 209367782 ps |
| CPU time | 3.38 seconds |
| Started | Oct 09 10:11:41 AM UTC 24 |
| Finished | Oct 09 10:11:46 AM UTC 24 |
| Peak memory | 219452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916273117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1916273117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all_with_rand_reset.3968860472 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 244249057 ps |
| CPU time | 7.47 seconds |
| Started | Oct 09 10:14:23 AM UTC 24 |
| Finished | Oct 09 10:14:32 AM UTC 24 |
| Peak memory | 231904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3968860472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymg r_stress_all_with_rand_reset.3968860472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/20.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all.3186776620 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 9418913283 ps |
| CPU time | 74.37 seconds |
| Started | Oct 09 10:15:56 AM UTC 24 |
| Finished | Oct 09 10:17:13 AM UTC 24 |
| Peak memory | 227764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186776620 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3186776620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/33.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/36.keymgr_cfg_regwen.3940919882 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 2218807028 ps |
| CPU time | 116.96 seconds |
| Started | Oct 09 10:16:14 AM UTC 24 |
| Finished | Oct 09 10:18:14 AM UTC 24 |
| Peak memory | 227768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940919882 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3940919882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/36.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/41.keymgr_cfg_regwen.3909592811 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 416122194 ps |
| CPU time | 8.96 seconds |
| Started | Oct 09 10:16:55 AM UTC 24 |
| Finished | Oct 09 10:17:06 AM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909592811 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3909592811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/41.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_intg_err.1149495008 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 266876406 ps |
| CPU time | 8.51 seconds |
| Started | Oct 09 02:29:58 PM UTC 24 |
| Finished | Oct 09 02:30:08 PM UTC 24 |
| Peak memory | 225496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149495008 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.1149495008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_intg_err.3005316791 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 112086990 ps |
| CPU time | 4.68 seconds |
| Started | Oct 09 02:31:50 PM UTC 24 |
| Finished | Oct 09 02:31:56 PM UTC 24 |
| Peak memory | 225592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005316791 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err.3005316791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.1661954445 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 99505766 ps |
| CPU time | 5.24 seconds |
| Started | Oct 09 02:32:10 PM UTC 24 |
| Finished | Oct 09 02:32:16 PM UTC 24 |
| Peak memory | 225848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661954445 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err.1661954445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_intg_err.1059986277 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 989595068 ps |
| CPU time | 10.32 seconds |
| Started | Oct 09 02:30:55 PM UTC 24 |
| Finished | Oct 09 02:31:06 PM UTC 24 |
| Peak memory | 225496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059986277 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.1059986277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_intg_err.3367421757 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 450481400 ps |
| CPU time | 4.73 seconds |
| Started | Oct 09 02:31:27 PM UTC 24 |
| Finished | Oct 09 02:31:33 PM UTC 24 |
| Peak memory | 225496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367421757 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.3367421757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_intg_err.1661091583 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 266197452 ps |
| CPU time | 4.81 seconds |
| Started | Oct 09 02:31:42 PM UTC 24 |
| Finished | Oct 09 02:31:48 PM UTC 24 |
| Peak memory | 225752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661091583 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.1661091583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/18.keymgr_hwsw_invalid_input.2232089631 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 7313381308 ps |
| CPU time | 38.06 seconds |
| Started | Oct 09 10:14:04 AM UTC 24 |
| Finished | Oct 09 10:14:44 AM UTC 24 |
| Peak memory | 223860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232089631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2232089631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/47.keymgr_sync_async_fault_cross.3912788803 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 136340119 ps |
| CPU time | 3.74 seconds |
| Started | Oct 09 10:17:40 AM UTC 24 |
| Finished | Oct 09 10:17:44 AM UTC 24 |
| Peak memory | 217380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912788803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3912788803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/47.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/0.keymgr_hwsw_invalid_input.4225181809 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 31427602 ps |
| CPU time | 3.7 seconds |
| Started | Oct 09 10:11:09 AM UTC 24 |
| Finished | Oct 09 10:11:14 AM UTC 24 |
| Peak memory | 223688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225181809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.4225181809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_aes.3832370761 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 115315707 ps |
| CPU time | 2.58 seconds |
| Started | Oct 09 10:11:20 AM UTC 24 |
| Finished | Oct 09 10:11:23 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832370761 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3832370761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/11.keymgr_kmac_rsp_err.3017640205 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 96181991 ps |
| CPU time | 5.51 seconds |
| Started | Oct 09 10:13:03 AM UTC 24 |
| Finished | Oct 09 10:13:09 AM UTC 24 |
| Peak memory | 231588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017640205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3017640205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_kmac.913353101 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 1254747080 ps |
| CPU time | 12.09 seconds |
| Started | Oct 09 10:12:58 AM UTC 24 |
| Finished | Oct 09 10:13:11 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913353101 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.913353101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/12.keymgr_hwsw_invalid_input.2962085994 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 405662264 ps |
| CPU time | 3.31 seconds |
| Started | Oct 09 10:13:11 AM UTC 24 |
| Finished | Oct 09 10:13:15 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962085994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2962085994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/12.keymgr_lc_disable.1920535339 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 202110517 ps |
| CPU time | 3.41 seconds |
| Started | Oct 09 10:13:10 AM UTC 24 |
| Finished | Oct 09 10:13:15 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920535339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1920535339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/13.keymgr_hwsw_invalid_input.3670454821 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1335157118 ps |
| CPU time | 34.95 seconds |
| Started | Oct 09 10:13:19 AM UTC 24 |
| Finished | Oct 09 10:13:56 AM UTC 24 |
| Peak memory | 217528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670454821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3670454821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all.1700165559 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 5735450110 ps |
| CPU time | 57.55 seconds |
| Started | Oct 09 10:13:23 AM UTC 24 |
| Finished | Oct 09 10:14:22 AM UTC 24 |
| Peak memory | 225648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700165559 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1700165559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all.3750636700 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 4972945200 ps |
| CPU time | 45.61 seconds |
| Started | Oct 09 10:13:32 AM UTC 24 |
| Finished | Oct 09 10:14:19 AM UTC 24 |
| Peak memory | 225720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750636700 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3750636700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/15.keymgr_kmac_rsp_err.2260950921 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 144251423 ps |
| CPU time | 5.15 seconds |
| Started | Oct 09 10:13:39 AM UTC 24 |
| Finished | Oct 09 10:13:46 AM UTC 24 |
| Peak memory | 231548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260950921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2260950921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/16.keymgr_cfg_regwen.438156307 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 77538780 ps |
| CPU time | 3.27 seconds |
| Started | Oct 09 10:13:47 AM UTC 24 |
| Finished | Oct 09 10:13:51 AM UTC 24 |
| Peak memory | 225652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438156307 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.438156307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/16.keymgr_hwsw_invalid_input.317741209 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 75567825 ps |
| CPU time | 2.4 seconds |
| Started | Oct 09 10:13:48 AM UTC 24 |
| Finished | Oct 09 10:13:51 AM UTC 24 |
| Peak memory | 223612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317741209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.317741209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/17.keymgr_custom_cm.902497392 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 129157374 ps |
| CPU time | 3.19 seconds |
| Started | Oct 09 10:13:57 AM UTC 24 |
| Finished | Oct 09 10:14:01 AM UTC 24 |
| Peak memory | 232028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902497392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.902497392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/20.keymgr_custom_cm.520890248 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 512505552 ps |
| CPU time | 5.48 seconds |
| Started | Oct 09 10:14:21 AM UTC 24 |
| Finished | Oct 09 10:14:27 AM UTC 24 |
| Peak memory | 227920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520890248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.520890248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/20.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all_with_rand_reset.2887672239 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 4911512040 ps |
| CPU time | 25.84 seconds |
| Started | Oct 09 10:14:44 AM UTC 24 |
| Finished | Oct 09 10:15:11 AM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2887672239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymg r_stress_all_with_rand_reset.2887672239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/23.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all.3247043978 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 144488632709 ps |
| CPU time | 294.33 seconds |
| Started | Oct 09 10:14:57 AM UTC 24 |
| Finished | Oct 09 10:19:55 AM UTC 24 |
| Peak memory | 231640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247043978 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3247043978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/25.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/28.keymgr_hwsw_invalid_input.492694810 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 123241060 ps |
| CPU time | 5.41 seconds |
| Started | Oct 09 10:15:15 AM UTC 24 |
| Finished | Oct 09 10:15:22 AM UTC 24 |
| Peak memory | 223548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492694810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.492694810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/28.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_protect.1675489665 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1385827973 ps |
| CPU time | 25.72 seconds |
| Started | Oct 09 10:15:33 AM UTC 24 |
| Finished | Oct 09 10:16:00 AM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675489665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1675489665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/30.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/34.keymgr_lc_disable.3766470794 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 48540152 ps |
| CPU time | 4.44 seconds |
| Started | Oct 09 10:16:01 AM UTC 24 |
| Finished | Oct 09 10:16:07 AM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766470794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3766470794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/34.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/35.keymgr_cfg_regwen.2615662436 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 648909339 ps |
| CPU time | 10.54 seconds |
| Started | Oct 09 10:16:08 AM UTC 24 |
| Finished | Oct 09 10:16:19 AM UTC 24 |
| Peak memory | 225676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615662436 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2615662436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/35.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/36.keymgr_stress_all.1950015488 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 1278139340 ps |
| CPU time | 16.68 seconds |
| Started | Oct 09 10:16:17 AM UTC 24 |
| Finished | Oct 09 10:16:35 AM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950015488 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1950015488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/36.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/42.keymgr_cfg_regwen.1017321107 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 1660782300 ps |
| CPU time | 76.11 seconds |
| Started | Oct 09 10:17:02 AM UTC 24 |
| Finished | Oct 09 10:18:20 AM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017321107 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1017321107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/42.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all.110579942 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 1280998358 ps |
| CPU time | 32.02 seconds |
| Started | Oct 09 10:17:06 AM UTC 24 |
| Finished | Oct 09 10:17:39 AM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110579942 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.110579942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/42.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/49.keymgr_hwsw_invalid_input.2684987406 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 2500129250 ps |
| CPU time | 8.01 seconds |
| Started | Oct 09 10:17:52 AM UTC 24 |
| Finished | Oct 09 10:18:01 AM UTC 24 |
| Peak memory | 223528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684987406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2684987406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/49.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/35.keymgr_custom_cm.3190466791 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 62826717 ps |
| CPU time | 2.95 seconds |
| Started | Oct 09 10:16:09 AM UTC 24 |
| Finished | Oct 09 10:16:13 AM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190466791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3190466791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/35.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/5.keymgr_custom_cm.1582461264 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 84929867 ps |
| CPU time | 3.5 seconds |
| Started | Oct 09 10:12:04 AM UTC 24 |
| Finished | Oct 09 10:12:09 AM UTC 24 |
| Peak memory | 232020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582461264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1582461264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_aliasing.4120747024 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 257158214 ps |
| CPU time | 8.87 seconds |
| Started | Oct 09 02:30:08 PM UTC 24 |
| Finished | Oct 09 02:30:18 PM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120747024 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.4120747024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_bit_bash.402811641 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 254168022 ps |
| CPU time | 19.09 seconds |
| Started | Oct 09 02:30:08 PM UTC 24 |
| Finished | Oct 09 02:30:29 PM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402811641 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.402811641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_hw_reset.133358760 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 13985645 ps |
| CPU time | 1.54 seconds |
| Started | Oct 09 02:30:05 PM UTC 24 |
| Finished | Oct 09 02:30:08 PM UTC 24 |
| Peak memory | 212520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133358760 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.133358760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1233528665 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 116057481 ps |
| CPU time | 2.24 seconds |
| Started | Oct 09 02:30:14 PM UTC 24 |
| Finished | Oct 09 02:30:17 PM UTC 24 |
| Peak memory | 215608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1233528665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_mem_rw_w ith_rand_reset.1233528665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_rw.1011503798 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 32007192 ps |
| CPU time | 1.67 seconds |
| Started | Oct 09 02:30:05 PM UTC 24 |
| Finished | Oct 09 02:30:08 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011503798 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1011503798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_intr_test.812619332 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 16715864 ps |
| CPU time | 1.02 seconds |
| Started | Oct 09 02:30:02 PM UTC 24 |
| Finished | Oct 09 02:30:04 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812619332 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.812619332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3759942504 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 111286682 ps |
| CPU time | 3.15 seconds |
| Started | Oct 09 02:30:09 PM UTC 24 |
| Finished | Oct 09 02:30:13 PM UTC 24 |
| Peak memory | 215292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759942504 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_same_csr_outstanding.3759942504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.430920150 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 198557195 ps |
| CPU time | 2.3 seconds |
| Started | Oct 09 02:29:53 PM UTC 24 |
| Finished | Oct 09 02:29:57 PM UTC 24 |
| Peak memory | 225836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430920150 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors.430920150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3670403429 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 139491385 ps |
| CPU time | 6.66 seconds |
| Started | Oct 09 02:29:53 PM UTC 24 |
| Finished | Oct 09 02:30:01 PM UTC 24 |
| Peak memory | 225788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670403429 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors_with_csr_rw.3670403429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_errors.3714502232 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 85563876 ps |
| CPU time | 5.5 seconds |
| Started | Oct 09 02:29:58 PM UTC 24 |
| Finished | Oct 09 02:30:05 PM UTC 24 |
| Peak memory | 225552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714502232 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3714502232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_aliasing.1042677362 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 2101069581 ps |
| CPU time | 9.99 seconds |
| Started | Oct 09 02:30:34 PM UTC 24 |
| Finished | Oct 09 02:30:45 PM UTC 24 |
| Peak memory | 215244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042677362 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1042677362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2263234451 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 1047801951 ps |
| CPU time | 17.38 seconds |
| Started | Oct 09 02:30:34 PM UTC 24 |
| Finished | Oct 09 02:30:53 PM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263234451 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2263234451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2384550099 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 43240611 ps |
| CPU time | 2.22 seconds |
| Started | Oct 09 02:30:31 PM UTC 24 |
| Finished | Oct 09 02:30:36 PM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384550099 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2384550099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3421448323 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 25878966 ps |
| CPU time | 2.49 seconds |
| Started | Oct 09 02:30:37 PM UTC 24 |
| Finished | Oct 09 02:30:41 PM UTC 24 |
| Peak memory | 225496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3421448323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_mem_rw_w ith_rand_reset.3421448323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_rw.2382201716 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 68417428 ps |
| CPU time | 1.53 seconds |
| Started | Oct 09 02:30:33 PM UTC 24 |
| Finished | Oct 09 02:30:36 PM UTC 24 |
| Peak memory | 212860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382201716 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2382201716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_intr_test.4183570177 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 42775419 ps |
| CPU time | 1.32 seconds |
| Started | Oct 09 02:30:30 PM UTC 24 |
| Finished | Oct 09 02:30:33 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183570177 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.4183570177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3338821459 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 181116550 ps |
| CPU time | 2.17 seconds |
| Started | Oct 09 02:30:36 PM UTC 24 |
| Finished | Oct 09 02:30:39 PM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338821459 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_same_csr_outstanding.3338821459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_errors.4080961897 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 88605054 ps |
| CPU time | 2.36 seconds |
| Started | Oct 09 02:30:26 PM UTC 24 |
| Finished | Oct 09 02:30:30 PM UTC 24 |
| Peak memory | 225624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080961897 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.4080961897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.377887901 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 102709170 ps |
| CPU time | 2.29 seconds |
| Started | Oct 09 02:31:49 PM UTC 24 |
| Finished | Oct 09 02:31:52 PM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=377887901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_mem_rw_w ith_rand_reset.377887901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_rw.3937457360 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 23711265 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 02:31:47 PM UTC 24 |
| Finished | Oct 09 02:31:50 PM UTC 24 |
| Peak memory | 212856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937457360 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3937457360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_intr_test.3675804613 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 71078639 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 02:31:47 PM UTC 24 |
| Finished | Oct 09 02:31:49 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675804613 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3675804613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1815557031 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 320744514 ps |
| CPU time | 3.89 seconds |
| Started | Oct 09 02:31:47 PM UTC 24 |
| Finished | Oct 09 02:31:52 PM UTC 24 |
| Peak memory | 215384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815557031 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_same_csr_outstanding.1815557031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1527287183 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 85045967 ps |
| CPU time | 2.44 seconds |
| Started | Oct 09 02:31:45 PM UTC 24 |
| Finished | Oct 09 02:31:48 PM UTC 24 |
| Peak memory | 225772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527287183 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors.1527287183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3439592398 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 2727620309 ps |
| CPU time | 17.72 seconds |
| Started | Oct 09 02:31:45 PM UTC 24 |
| Finished | Oct 09 02:32:04 PM UTC 24 |
| Peak memory | 225920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439592398 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors_with_csr_rw.3439592398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_errors.2060184138 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 461523992 ps |
| CPU time | 2.82 seconds |
| Started | Oct 09 02:31:46 PM UTC 24 |
| Finished | Oct 09 02:31:50 PM UTC 24 |
| Peak memory | 225880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060184138 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2060184138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3501580979 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 97967513 ps |
| CPU time | 2.58 seconds |
| Started | Oct 09 02:31:53 PM UTC 24 |
| Finished | Oct 09 02:31:56 PM UTC 24 |
| Peak memory | 230068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3501580979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_mem_rw_ with_rand_reset.3501580979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_rw.3758456229 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 16892844 ps |
| CPU time | 1.79 seconds |
| Started | Oct 09 02:31:51 PM UTC 24 |
| Finished | Oct 09 02:31:54 PM UTC 24 |
| Peak memory | 212796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758456229 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3758456229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_intr_test.544220349 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 19518671 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 02:31:51 PM UTC 24 |
| Finished | Oct 09 02:31:53 PM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544220349 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.544220349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3934122826 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 176945335 ps |
| CPU time | 4.93 seconds |
| Started | Oct 09 02:31:53 PM UTC 24 |
| Finished | Oct 09 02:31:58 PM UTC 24 |
| Peak memory | 215640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934122826 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_same_csr_outstanding.3934122826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2261045100 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 878922974 ps |
| CPU time | 3.95 seconds |
| Started | Oct 09 02:31:49 PM UTC 24 |
| Finished | Oct 09 02:31:54 PM UTC 24 |
| Peak memory | 229988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261045100 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors.2261045100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.4070056034 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 757652178 ps |
| CPU time | 5.93 seconds |
| Started | Oct 09 02:31:50 PM UTC 24 |
| Finished | Oct 09 02:31:57 PM UTC 24 |
| Peak memory | 225792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070056034 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors_with_csr_rw.4070056034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_errors.230244289 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 131726872 ps |
| CPU time | 5.28 seconds |
| Started | Oct 09 02:31:50 PM UTC 24 |
| Finished | Oct 09 02:31:56 PM UTC 24 |
| Peak memory | 225492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230244289 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.230244289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.921860707 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 61045371 ps |
| CPU time | 1.77 seconds |
| Started | Oct 09 02:31:58 PM UTC 24 |
| Finished | Oct 09 02:32:01 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=921860707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_mem_rw_w ith_rand_reset.921860707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_rw.2344767163 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 107109573 ps |
| CPU time | 2.16 seconds |
| Started | Oct 09 02:31:56 PM UTC 24 |
| Finished | Oct 09 02:32:00 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344767163 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2344767163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_intr_test.602714513 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 43006705 ps |
| CPU time | 1.32 seconds |
| Started | Oct 09 02:31:55 PM UTC 24 |
| Finished | Oct 09 02:31:58 PM UTC 24 |
| Peak memory | 212852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602714513 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.602714513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3763109711 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 59252077 ps |
| CPU time | 2.68 seconds |
| Started | Oct 09 02:31:58 PM UTC 24 |
| Finished | Oct 09 02:32:01 PM UTC 24 |
| Peak memory | 215264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763109711 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_same_csr_outstanding.3763109711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.4277509238 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 700468224 ps |
| CPU time | 6.73 seconds |
| Started | Oct 09 02:31:54 PM UTC 24 |
| Finished | Oct 09 02:32:02 PM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277509238 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors.4277509238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1062920251 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 275616812 ps |
| CPU time | 6.98 seconds |
| Started | Oct 09 02:31:55 PM UTC 24 |
| Finished | Oct 09 02:32:03 PM UTC 24 |
| Peak memory | 232396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062920251 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors_with_csr_rw.1062920251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_errors.3271954011 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 127290122 ps |
| CPU time | 2.98 seconds |
| Started | Oct 09 02:31:55 PM UTC 24 |
| Finished | Oct 09 02:31:59 PM UTC 24 |
| Peak memory | 225548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271954011 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3271954011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_intg_err.4238348818 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 281910322 ps |
| CPU time | 7.19 seconds |
| Started | Oct 09 02:31:55 PM UTC 24 |
| Finished | Oct 09 02:32:04 PM UTC 24 |
| Peak memory | 225504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238348818 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err.4238348818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.164614192 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 217905573 ps |
| CPU time | 3.22 seconds |
| Started | Oct 09 02:32:03 PM UTC 24 |
| Finished | Oct 09 02:32:07 PM UTC 24 |
| Peak memory | 225912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=164614192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_mem_rw_w ith_rand_reset.164614192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_rw.1109082319 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 14543915 ps |
| CPU time | 1.62 seconds |
| Started | Oct 09 02:32:02 PM UTC 24 |
| Finished | Oct 09 02:32:04 PM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109082319 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1109082319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_intr_test.974751237 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 14688852 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 02:32:00 PM UTC 24 |
| Finished | Oct 09 02:32:03 PM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974751237 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.974751237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4019435605 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 68384357 ps |
| CPU time | 2.4 seconds |
| Started | Oct 09 02:32:03 PM UTC 24 |
| Finished | Oct 09 02:32:06 PM UTC 24 |
| Peak memory | 215608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019435605 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_same_csr_outstanding.4019435605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.349878590 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 531866803 ps |
| CPU time | 5 seconds |
| Started | Oct 09 02:31:58 PM UTC 24 |
| Finished | Oct 09 02:32:04 PM UTC 24 |
| Peak memory | 225776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349878590 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors.349878590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2801053720 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 819939249 ps |
| CPU time | 6.16 seconds |
| Started | Oct 09 02:31:59 PM UTC 24 |
| Finished | Oct 09 02:32:06 PM UTC 24 |
| Peak memory | 231912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801053720 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors_with_csr_rw.2801053720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_errors.360103454 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 147002276 ps |
| CPU time | 2.54 seconds |
| Started | Oct 09 02:31:59 PM UTC 24 |
| Finished | Oct 09 02:32:03 PM UTC 24 |
| Peak memory | 225612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360103454 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.360103454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.15729650 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 258641220 ps |
| CPU time | 10.76 seconds |
| Started | Oct 09 02:32:00 PM UTC 24 |
| Finished | Oct 09 02:32:12 PM UTC 24 |
| Peak memory | 225588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15729650 -assert nopostproc +UVM_TESTNAM E=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err.15729650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1061704657 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 62258083 ps |
| CPU time | 3.57 seconds |
| Started | Oct 09 02:32:07 PM UTC 24 |
| Finished | Oct 09 02:32:12 PM UTC 24 |
| Peak memory | 225588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1061704657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_mem_rw_ with_rand_reset.1061704657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.2294334815 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 167025771 ps |
| CPU time | 2.05 seconds |
| Started | Oct 09 02:32:06 PM UTC 24 |
| Finished | Oct 09 02:32:09 PM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294334815 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2294334815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.2027825873 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 19584902 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 02:32:06 PM UTC 24 |
| Finished | Oct 09 02:32:08 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027825873 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2027825873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3817296335 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 86313179 ps |
| CPU time | 3.93 seconds |
| Started | Oct 09 02:32:06 PM UTC 24 |
| Finished | Oct 09 02:32:11 PM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817296335 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_same_csr_outstanding.3817296335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.4121382586 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 475698622 ps |
| CPU time | 3.02 seconds |
| Started | Oct 09 02:32:04 PM UTC 24 |
| Finished | Oct 09 02:32:08 PM UTC 24 |
| Peak memory | 225892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121382586 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors.4121382586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1550281691 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 293101702 ps |
| CPU time | 7.69 seconds |
| Started | Oct 09 02:32:04 PM UTC 24 |
| Finished | Oct 09 02:32:13 PM UTC 24 |
| Peak memory | 232168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550281691 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors_with_csr_rw.1550281691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.866020750 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 127218847 ps |
| CPU time | 2.94 seconds |
| Started | Oct 09 02:32:04 PM UTC 24 |
| Finished | Oct 09 02:32:08 PM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866020750 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.866020750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.689347325 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 61154462 ps |
| CPU time | 3.07 seconds |
| Started | Oct 09 02:32:13 PM UTC 24 |
| Finished | Oct 09 02:32:17 PM UTC 24 |
| Peak memory | 227616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=689347325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_mem_rw_w ith_rand_reset.689347325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.3363315800 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 205928154 ps |
| CPU time | 1.79 seconds |
| Started | Oct 09 02:32:10 PM UTC 24 |
| Finished | Oct 09 02:32:13 PM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363315800 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3363315800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.4151279533 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 13281296 ps |
| CPU time | 1.41 seconds |
| Started | Oct 09 02:32:10 PM UTC 24 |
| Finished | Oct 09 02:32:12 PM UTC 24 |
| Peak memory | 212520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151279533 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.4151279533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3898559330 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 495252561 ps |
| CPU time | 4.34 seconds |
| Started | Oct 09 02:32:11 PM UTC 24 |
| Finished | Oct 09 02:32:17 PM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898559330 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_same_csr_outstanding.3898559330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1149064462 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 235981386 ps |
| CPU time | 3.29 seconds |
| Started | Oct 09 02:32:07 PM UTC 24 |
| Finished | Oct 09 02:32:11 PM UTC 24 |
| Peak memory | 225772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149064462 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors.1149064462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2540609894 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 123588337 ps |
| CPU time | 4.17 seconds |
| Started | Oct 09 02:32:08 PM UTC 24 |
| Finished | Oct 09 02:32:14 PM UTC 24 |
| Peak memory | 225888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540609894 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors_with_csr_rw.2540609894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.2694767606 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 38459450 ps |
| CPU time | 2.04 seconds |
| Started | Oct 09 02:32:08 PM UTC 24 |
| Finished | Oct 09 02:32:12 PM UTC 24 |
| Peak memory | 215260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694767606 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2694767606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.4153326510 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 118857353 ps |
| CPU time | 1.82 seconds |
| Started | Oct 09 02:32:15 PM UTC 24 |
| Finished | Oct 09 02:32:18 PM UTC 24 |
| Peak memory | 222976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4153326510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_mem_rw_ with_rand_reset.4153326510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.2968803908 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 56460676 ps |
| CPU time | 1.56 seconds |
| Started | Oct 09 02:32:14 PM UTC 24 |
| Finished | Oct 09 02:32:18 PM UTC 24 |
| Peak memory | 212796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968803908 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2968803908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.816653569 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 40176488 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 02:32:14 PM UTC 24 |
| Finished | Oct 09 02:32:18 PM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816653569 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.816653569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2898729115 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 258837996 ps |
| CPU time | 2.62 seconds |
| Started | Oct 09 02:32:15 PM UTC 24 |
| Finished | Oct 09 02:32:19 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898729115 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_same_csr_outstanding.2898729115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.228005368 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 1591794001 ps |
| CPU time | 3.72 seconds |
| Started | Oct 09 02:32:13 PM UTC 24 |
| Finished | Oct 09 02:32:18 PM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228005368 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors.228005368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3670329945 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 117665544 ps |
| CPU time | 5.83 seconds |
| Started | Oct 09 02:32:13 PM UTC 24 |
| Finished | Oct 09 02:32:20 PM UTC 24 |
| Peak memory | 225816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670329945 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors_with_csr_rw.3670329945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.35933075 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 423042485 ps |
| CPU time | 2.48 seconds |
| Started | Oct 09 02:32:13 PM UTC 24 |
| Finished | Oct 09 02:32:17 PM UTC 24 |
| Peak memory | 225456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35933075 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.35933075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.4079899948 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 108839105 ps |
| CPU time | 2.76 seconds |
| Started | Oct 09 02:32:20 PM UTC 24 |
| Finished | Oct 09 02:32:24 PM UTC 24 |
| Peak memory | 225588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4079899948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_mem_rw_ with_rand_reset.4079899948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.2643610904 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 12490232 ps |
| CPU time | 1.61 seconds |
| Started | Oct 09 02:32:19 PM UTC 24 |
| Finished | Oct 09 02:32:22 PM UTC 24 |
| Peak memory | 214284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643610904 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2643610904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.2696588628 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 100790751 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 02:32:19 PM UTC 24 |
| Finished | Oct 09 02:32:21 PM UTC 24 |
| Peak memory | 214144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696588628 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2696588628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2236791791 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 62982394 ps |
| CPU time | 2.62 seconds |
| Started | Oct 09 02:32:20 PM UTC 24 |
| Finished | Oct 09 02:32:24 PM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236791791 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_same_csr_outstanding.2236791791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3076305914 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 78533998 ps |
| CPU time | 2.75 seconds |
| Started | Oct 09 02:32:17 PM UTC 24 |
| Finished | Oct 09 02:32:21 PM UTC 24 |
| Peak memory | 225772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076305914 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors.3076305914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3893805359 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 305301982 ps |
| CPU time | 8.58 seconds |
| Started | Oct 09 02:32:18 PM UTC 24 |
| Finished | Oct 09 02:32:28 PM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893805359 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors_with_csr_rw.3893805359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.3741482524 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 184002664 ps |
| CPU time | 3.58 seconds |
| Started | Oct 09 02:32:18 PM UTC 24 |
| Finished | Oct 09 02:32:23 PM UTC 24 |
| Peak memory | 225616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741482524 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3741482524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.1959784761 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 185500038 ps |
| CPU time | 3.72 seconds |
| Started | Oct 09 02:32:19 PM UTC 24 |
| Finished | Oct 09 02:32:24 PM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959784761 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err.1959784761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3702548160 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 29912151 ps |
| CPU time | 2.31 seconds |
| Started | Oct 09 02:32:25 PM UTC 24 |
| Finished | Oct 09 02:32:29 PM UTC 24 |
| Peak memory | 215260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3702548160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_mem_rw_ with_rand_reset.3702548160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.3005070168 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 22321790 ps |
| CPU time | 1.95 seconds |
| Started | Oct 09 02:32:22 PM UTC 24 |
| Finished | Oct 09 02:32:25 PM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005070168 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3005070168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.3389826331 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 13579171 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 02:32:22 PM UTC 24 |
| Finished | Oct 09 02:32:24 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389826331 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3389826331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3570191457 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 23202054 ps |
| CPU time | 2.11 seconds |
| Started | Oct 09 02:32:23 PM UTC 24 |
| Finished | Oct 09 02:32:27 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570191457 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_same_csr_outstanding.3570191457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.685289548 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 72281758 ps |
| CPU time | 3.86 seconds |
| Started | Oct 09 02:32:20 PM UTC 24 |
| Finished | Oct 09 02:32:25 PM UTC 24 |
| Peak memory | 225704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685289548 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors.685289548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1056377609 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 291076803 ps |
| CPU time | 5.08 seconds |
| Started | Oct 09 02:32:22 PM UTC 24 |
| Finished | Oct 09 02:32:28 PM UTC 24 |
| Peak memory | 225768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056377609 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors_with_csr_rw.1056377609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.3633955109 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 460284838 ps |
| CPU time | 3.12 seconds |
| Started | Oct 09 02:32:22 PM UTC 24 |
| Finished | Oct 09 02:32:26 PM UTC 24 |
| Peak memory | 225428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633955109 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3633955109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.3474801240 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 104151127 ps |
| CPU time | 5.41 seconds |
| Started | Oct 09 02:32:22 PM UTC 24 |
| Finished | Oct 09 02:32:29 PM UTC 24 |
| Peak memory | 225432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474801240 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err.3474801240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1823709943 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 96951045 ps |
| CPU time | 2.42 seconds |
| Started | Oct 09 02:32:27 PM UTC 24 |
| Finished | Oct 09 02:32:31 PM UTC 24 |
| Peak memory | 225612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1823709943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_mem_rw_ with_rand_reset.1823709943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.3304423386 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 61410538 ps |
| CPU time | 2.3 seconds |
| Started | Oct 09 02:32:27 PM UTC 24 |
| Finished | Oct 09 02:32:30 PM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304423386 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3304423386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.2067024954 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 27958514 ps |
| CPU time | 1.06 seconds |
| Started | Oct 09 02:32:26 PM UTC 24 |
| Finished | Oct 09 02:32:28 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067024954 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2067024954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2007752554 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 345466374 ps |
| CPU time | 3.81 seconds |
| Started | Oct 09 02:32:27 PM UTC 24 |
| Finished | Oct 09 02:32:32 PM UTC 24 |
| Peak memory | 215196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007752554 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_same_csr_outstanding.2007752554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3563602247 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 183339724 ps |
| CPU time | 2.9 seconds |
| Started | Oct 09 02:32:25 PM UTC 24 |
| Finished | Oct 09 02:32:29 PM UTC 24 |
| Peak memory | 225736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563602247 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors.3563602247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1063904661 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 645778831 ps |
| CPU time | 9.27 seconds |
| Started | Oct 09 02:32:25 PM UTC 24 |
| Finished | Oct 09 02:32:36 PM UTC 24 |
| Peak memory | 225644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063904661 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors_with_csr_rw.1063904661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.2153718641 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 57076893 ps |
| CPU time | 2.33 seconds |
| Started | Oct 09 02:32:25 PM UTC 24 |
| Finished | Oct 09 02:32:29 PM UTC 24 |
| Peak memory | 225628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153718641 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2153718641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.1938021865 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 146236258 ps |
| CPU time | 3.72 seconds |
| Started | Oct 09 02:32:25 PM UTC 24 |
| Finished | Oct 09 02:32:30 PM UTC 24 |
| Peak memory | 225432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938021865 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err.1938021865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_aliasing.2197918249 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 84225430 ps |
| CPU time | 6.14 seconds |
| Started | Oct 09 02:30:48 PM UTC 24 |
| Finished | Oct 09 02:30:56 PM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197918249 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2197918249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1400835102 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 5117006675 ps |
| CPU time | 40.65 seconds |
| Started | Oct 09 02:30:47 PM UTC 24 |
| Finished | Oct 09 02:31:29 PM UTC 24 |
| Peak memory | 215324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400835102 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1400835102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_hw_reset.790213638 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 16558066 ps |
| CPU time | 1.56 seconds |
| Started | Oct 09 02:30:46 PM UTC 24 |
| Finished | Oct 09 02:30:49 PM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790213638 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.790213638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.529435215 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 36659259 ps |
| CPU time | 1.77 seconds |
| Started | Oct 09 02:30:50 PM UTC 24 |
| Finished | Oct 09 02:30:53 PM UTC 24 |
| Peak memory | 212740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=529435215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_mem_rw_wi th_rand_reset.529435215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_rw.718251806 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 18863751 ps |
| CPU time | 1.58 seconds |
| Started | Oct 09 02:30:47 PM UTC 24 |
| Finished | Oct 09 02:30:50 PM UTC 24 |
| Peak memory | 212796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718251806 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.718251806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_intr_test.3337973043 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 24851653 ps |
| CPU time | 1.26 seconds |
| Started | Oct 09 02:30:45 PM UTC 24 |
| Finished | Oct 09 02:30:47 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337973043 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3337973043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.864661019 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 69833611 ps |
| CPU time | 3.17 seconds |
| Started | Oct 09 02:30:49 PM UTC 24 |
| Finished | Oct 09 02:30:54 PM UTC 24 |
| Peak memory | 215196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864661019 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_same_csr_outstanding.864661019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2457143641 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 475520916 ps |
| CPU time | 3.46 seconds |
| Started | Oct 09 02:30:39 PM UTC 24 |
| Finished | Oct 09 02:30:44 PM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457143641 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors.2457143641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2561536859 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 231272175 ps |
| CPU time | 5.63 seconds |
| Started | Oct 09 02:30:39 PM UTC 24 |
| Finished | Oct 09 02:30:46 PM UTC 24 |
| Peak memory | 225828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561536859 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors_with_csr_rw.2561536859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_errors.858374077 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 84277173 ps |
| CPU time | 4.09 seconds |
| Started | Oct 09 02:30:40 PM UTC 24 |
| Finished | Oct 09 02:30:46 PM UTC 24 |
| Peak memory | 225760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858374077 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.858374077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_intg_err.1638428497 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 220650979 ps |
| CPU time | 5.82 seconds |
| Started | Oct 09 02:30:42 PM UTC 24 |
| Finished | Oct 09 02:30:49 PM UTC 24 |
| Peak memory | 225544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638428497 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.1638428497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.2863101738 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 35050140 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 02:32:27 PM UTC 24 |
| Finished | Oct 09 02:32:30 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863101738 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2863101738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/20.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.3022537114 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 39924550 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 02:32:29 PM UTC 24 |
| Finished | Oct 09 02:32:31 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022537114 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3022537114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/21.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.551830844 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 10180080 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 02:32:29 PM UTC 24 |
| Finished | Oct 09 02:32:31 PM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551830844 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.551830844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/22.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.2514931246 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 29583021 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 02:32:31 PM UTC 24 |
| Finished | Oct 09 02:32:33 PM UTC 24 |
| Peak memory | 212860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514931246 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2514931246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/23.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.1660103771 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 9392817 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 02:32:31 PM UTC 24 |
| Finished | Oct 09 02:32:33 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660103771 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1660103771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/24.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.997421692 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 14543480 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 02:32:31 PM UTC 24 |
| Finished | Oct 09 02:32:33 PM UTC 24 |
| Peak memory | 212656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997421692 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.997421692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/25.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.2112613214 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 9297234 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 02:32:31 PM UTC 24 |
| Finished | Oct 09 02:32:33 PM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112613214 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2112613214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/26.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.593897353 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 8343620 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 02:32:31 PM UTC 24 |
| Finished | Oct 09 02:32:33 PM UTC 24 |
| Peak memory | 212852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593897353 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.593897353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/27.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.2538444735 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 16930110 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 02:32:31 PM UTC 24 |
| Finished | Oct 09 02:32:33 PM UTC 24 |
| Peak memory | 212520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538444735 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2538444735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/28.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.3360624183 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 13114782 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 02:32:33 PM UTC 24 |
| Finished | Oct 09 02:32:35 PM UTC 24 |
| Peak memory | 212732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360624183 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3360624183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/29.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_aliasing.983865855 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 125096434 ps |
| CPU time | 10.49 seconds |
| Started | Oct 09 02:31:02 PM UTC 24 |
| Finished | Oct 09 02:31:14 PM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983865855 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.983865855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2048672760 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 265068458 ps |
| CPU time | 8.76 seconds |
| Started | Oct 09 02:31:00 PM UTC 24 |
| Finished | Oct 09 02:31:10 PM UTC 24 |
| Peak memory | 215196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048672760 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2048672760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1233276137 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 38217732 ps |
| CPU time | 1.52 seconds |
| Started | Oct 09 02:30:57 PM UTC 24 |
| Finished | Oct 09 02:30:59 PM UTC 24 |
| Peak memory | 212864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233276137 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1233276137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.4025665695 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 61220658 ps |
| CPU time | 2.34 seconds |
| Started | Oct 09 02:31:04 PM UTC 24 |
| Finished | Oct 09 02:31:08 PM UTC 24 |
| Peak memory | 215328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4025665695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_mem_rw_w ith_rand_reset.4025665695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_rw.3855080786 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 28658416 ps |
| CPU time | 1.84 seconds |
| Started | Oct 09 02:31:00 PM UTC 24 |
| Finished | Oct 09 02:31:03 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855080786 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3855080786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_intr_test.3397400933 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 9811711 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 02:30:57 PM UTC 24 |
| Finished | Oct 09 02:30:59 PM UTC 24 |
| Peak memory | 212520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397400933 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3397400933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.557084194 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 733825172 ps |
| CPU time | 2.82 seconds |
| Started | Oct 09 02:31:03 PM UTC 24 |
| Finished | Oct 09 02:31:06 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557084194 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_same_csr_outstanding.557084194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1759313650 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 253196431 ps |
| CPU time | 3.52 seconds |
| Started | Oct 09 02:30:51 PM UTC 24 |
| Finished | Oct 09 02:30:56 PM UTC 24 |
| Peak memory | 225732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759313650 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors.1759313650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1706465401 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 180003017 ps |
| CPU time | 9.69 seconds |
| Started | Oct 09 02:30:54 PM UTC 24 |
| Finished | Oct 09 02:31:04 PM UTC 24 |
| Peak memory | 225820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706465401 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors_with_csr_rw.1706465401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_errors.1056876281 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 168790377 ps |
| CPU time | 6.51 seconds |
| Started | Oct 09 02:30:54 PM UTC 24 |
| Finished | Oct 09 02:31:01 PM UTC 24 |
| Peak memory | 225496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056876281 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1056876281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.960844652 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 18599537 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 02:32:33 PM UTC 24 |
| Finished | Oct 09 02:32:35 PM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960844652 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.960844652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/30.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.1729517118 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 14787981 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 02:32:33 PM UTC 24 |
| Finished | Oct 09 02:32:35 PM UTC 24 |
| Peak memory | 212728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729517118 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1729517118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/31.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.3481764380 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 45143299 ps |
| CPU time | 1.38 seconds |
| Started | Oct 09 02:32:33 PM UTC 24 |
| Finished | Oct 09 02:32:35 PM UTC 24 |
| Peak memory | 212520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481764380 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3481764380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/32.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.4260645851 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 22087514 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 02:32:33 PM UTC 24 |
| Finished | Oct 09 02:32:35 PM UTC 24 |
| Peak memory | 212524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260645851 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.4260645851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/33.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.1519996692 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 51922323 ps |
| CPU time | 1.41 seconds |
| Started | Oct 09 02:32:35 PM UTC 24 |
| Finished | Oct 09 02:32:38 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519996692 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1519996692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/34.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.2618457301 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 33917735 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 02:32:35 PM UTC 24 |
| Finished | Oct 09 02:32:37 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618457301 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2618457301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/35.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.3519396631 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 54878751 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 02:32:35 PM UTC 24 |
| Finished | Oct 09 02:32:37 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519396631 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3519396631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/36.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.2638455094 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 42355215 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 02:32:35 PM UTC 24 |
| Finished | Oct 09 02:32:37 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638455094 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2638455094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/37.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.3055699003 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 9488820 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 02:32:35 PM UTC 24 |
| Finished | Oct 09 02:32:38 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055699003 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3055699003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/38.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.2016733024 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 25881313 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 02:32:35 PM UTC 24 |
| Finished | Oct 09 02:32:37 PM UTC 24 |
| Peak memory | 212520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016733024 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2016733024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/39.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_aliasing.376393825 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 3954085154 ps |
| CPU time | 22.37 seconds |
| Started | Oct 09 02:31:13 PM UTC 24 |
| Finished | Oct 09 02:31:37 PM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376393825 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.376393825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_bit_bash.4229795710 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 445330070 ps |
| CPU time | 12.04 seconds |
| Started | Oct 09 02:31:12 PM UTC 24 |
| Finished | Oct 09 02:31:25 PM UTC 24 |
| Peak memory | 215252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229795710 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.4229795710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_hw_reset.4185377457 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 102661524 ps |
| CPU time | 1.58 seconds |
| Started | Oct 09 02:31:10 PM UTC 24 |
| Finished | Oct 09 02:31:12 PM UTC 24 |
| Peak memory | 212864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185377457 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.4185377457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.4062880517 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 45751437 ps |
| CPU time | 2.83 seconds |
| Started | Oct 09 02:31:13 PM UTC 24 |
| Finished | Oct 09 02:31:17 PM UTC 24 |
| Peak memory | 225688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4062880517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_mem_rw_w ith_rand_reset.4062880517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_rw.3767134328 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 12561707 ps |
| CPU time | 1.41 seconds |
| Started | Oct 09 02:31:11 PM UTC 24 |
| Finished | Oct 09 02:31:13 PM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767134328 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3767134328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_intr_test.2998290142 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 44309879 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 02:31:09 PM UTC 24 |
| Finished | Oct 09 02:31:11 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998290142 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2998290142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3921864704 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 87610486 ps |
| CPU time | 2.44 seconds |
| Started | Oct 09 02:31:13 PM UTC 24 |
| Finished | Oct 09 02:31:17 PM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921864704 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_same_csr_outstanding.3921864704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3175470433 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 322236208 ps |
| CPU time | 3.9 seconds |
| Started | Oct 09 02:31:04 PM UTC 24 |
| Finished | Oct 09 02:31:09 PM UTC 24 |
| Peak memory | 225780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175470433 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors.3175470433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2238541664 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 1622835124 ps |
| CPU time | 13.41 seconds |
| Started | Oct 09 02:31:05 PM UTC 24 |
| Finished | Oct 09 02:31:20 PM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238541664 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors_with_csr_rw.2238541664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_errors.1051409946 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 35542498 ps |
| CPU time | 3.86 seconds |
| Started | Oct 09 02:31:08 PM UTC 24 |
| Finished | Oct 09 02:31:12 PM UTC 24 |
| Peak memory | 225784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051409946 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1051409946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_intg_err.1430897107 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 181828977 ps |
| CPU time | 4.05 seconds |
| Started | Oct 09 02:31:08 PM UTC 24 |
| Finished | Oct 09 02:31:13 PM UTC 24 |
| Peak memory | 215312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430897107 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.1430897107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.1840590336 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 21702141 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 02:32:35 PM UTC 24 |
| Finished | Oct 09 02:32:38 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840590336 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1840590336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/40.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.816755570 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 67185609 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 02:32:37 PM UTC 24 |
| Finished | Oct 09 02:32:40 PM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816755570 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.816755570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/41.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.660653343 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 11661427 ps |
| CPU time | 1.36 seconds |
| Started | Oct 09 02:32:37 PM UTC 24 |
| Finished | Oct 09 02:32:40 PM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660653343 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.660653343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/42.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.3652498735 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 31635400 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 02:32:37 PM UTC 24 |
| Finished | Oct 09 02:32:40 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652498735 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3652498735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/43.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.4150173273 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 55356976 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 02:32:37 PM UTC 24 |
| Finished | Oct 09 02:32:40 PM UTC 24 |
| Peak memory | 212520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150173273 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.4150173273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/44.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.4232081850 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 11612924 ps |
| CPU time | 1 seconds |
| Started | Oct 09 02:32:38 PM UTC 24 |
| Finished | Oct 09 02:32:40 PM UTC 24 |
| Peak memory | 212520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232081850 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.4232081850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/45.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.16111881 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 24624492 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 02:32:38 PM UTC 24 |
| Finished | Oct 09 02:32:40 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16111881 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.16111881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/46.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.1635295958 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 31960899 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 02:32:39 PM UTC 24 |
| Finished | Oct 09 02:32:42 PM UTC 24 |
| Peak memory | 212520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635295958 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1635295958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/47.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.4262205805 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 27233207 ps |
| CPU time | 1.35 seconds |
| Started | Oct 09 02:32:40 PM UTC 24 |
| Finished | Oct 09 02:32:42 PM UTC 24 |
| Peak memory | 212460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262205805 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.4262205805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/48.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.1644584115 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 13431453 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 02:32:40 PM UTC 24 |
| Finished | Oct 09 02:32:42 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644584115 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1644584115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/49.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.912821267 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 28424356 ps |
| CPU time | 2.14 seconds |
| Started | Oct 09 02:31:24 PM UTC 24 |
| Finished | Oct 09 02:31:28 PM UTC 24 |
| Peak memory | 215584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=912821267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_mem_rw_wi th_rand_reset.912821267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_rw.1871442572 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 13508917 ps |
| CPU time | 1.46 seconds |
| Started | Oct 09 02:31:21 PM UTC 24 |
| Finished | Oct 09 02:31:23 PM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871442572 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1871442572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_intr_test.3599755194 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 10464321 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 02:31:20 PM UTC 24 |
| Finished | Oct 09 02:31:22 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599755194 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3599755194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1519342172 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 49077057 ps |
| CPU time | 3.57 seconds |
| Started | Oct 09 02:31:23 PM UTC 24 |
| Finished | Oct 09 02:31:28 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519342172 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_same_csr_outstanding.1519342172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2722097235 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 132113441 ps |
| CPU time | 3.35 seconds |
| Started | Oct 09 02:31:14 PM UTC 24 |
| Finished | Oct 09 02:31:19 PM UTC 24 |
| Peak memory | 225804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722097235 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors.2722097235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1801313152 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 869691288 ps |
| CPU time | 12.68 seconds |
| Started | Oct 09 02:31:16 PM UTC 24 |
| Finished | Oct 09 02:31:29 PM UTC 24 |
| Peak memory | 225828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801313152 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors_with_csr_rw.1801313152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_errors.3757545096 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 114293909 ps |
| CPU time | 3.8 seconds |
| Started | Oct 09 02:31:18 PM UTC 24 |
| Finished | Oct 09 02:31:23 PM UTC 24 |
| Peak memory | 225432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757545096 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3757545096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_intg_err.1502495818 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 750418213 ps |
| CPU time | 7.92 seconds |
| Started | Oct 09 02:31:18 PM UTC 24 |
| Finished | Oct 09 02:31:27 PM UTC 24 |
| Peak memory | 225752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502495818 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.1502495818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1628326105 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 648990669 ps |
| CPU time | 2.28 seconds |
| Started | Oct 09 02:31:30 PM UTC 24 |
| Finished | Oct 09 02:31:34 PM UTC 24 |
| Peak memory | 225616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1628326105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_mem_rw_w ith_rand_reset.1628326105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_rw.199700527 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 28265263 ps |
| CPU time | 1.75 seconds |
| Started | Oct 09 02:31:28 PM UTC 24 |
| Finished | Oct 09 02:31:31 PM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199700527 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.199700527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_intr_test.2887726788 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 12788900 ps |
| CPU time | 1.32 seconds |
| Started | Oct 09 02:31:28 PM UTC 24 |
| Finished | Oct 09 02:31:30 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887726788 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2887726788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2032238133 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 103119763 ps |
| CPU time | 3.37 seconds |
| Started | Oct 09 02:31:29 PM UTC 24 |
| Finished | Oct 09 02:31:34 PM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032238133 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_same_csr_outstanding.2032238133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1477719785 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 304199531 ps |
| CPU time | 5.44 seconds |
| Started | Oct 09 02:31:24 PM UTC 24 |
| Finished | Oct 09 02:31:31 PM UTC 24 |
| Peak memory | 226036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477719785 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors.1477719785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.38801693 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 1205796859 ps |
| CPU time | 8.54 seconds |
| Started | Oct 09 02:31:27 PM UTC 24 |
| Finished | Oct 09 02:31:36 PM UTC 24 |
| Peak memory | 225816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38801693 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors_with_csr_rw.38801693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_errors.3798200131 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 444114914 ps |
| CPU time | 4.99 seconds |
| Started | Oct 09 02:31:27 PM UTC 24 |
| Finished | Oct 09 02:31:33 PM UTC 24 |
| Peak memory | 225504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798200131 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3798200131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.24407717 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 38955546 ps |
| CPU time | 1.76 seconds |
| Started | Oct 09 02:31:34 PM UTC 24 |
| Finished | Oct 09 02:31:37 PM UTC 24 |
| Peak memory | 225888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=24407717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_mem_rw_wit h_rand_reset.24407717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_rw.3400765249 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 25055504 ps |
| CPU time | 1.77 seconds |
| Started | Oct 09 02:31:33 PM UTC 24 |
| Finished | Oct 09 02:31:36 PM UTC 24 |
| Peak memory | 212860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400765249 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3400765249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_intr_test.379035105 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 12959230 ps |
| CPU time | 1.35 seconds |
| Started | Oct 09 02:31:32 PM UTC 24 |
| Finished | Oct 09 02:31:35 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379035105 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.379035105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1176660449 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 158127608 ps |
| CPU time | 3.15 seconds |
| Started | Oct 09 02:31:34 PM UTC 24 |
| Finished | Oct 09 02:31:39 PM UTC 24 |
| Peak memory | 215224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176660449 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_same_csr_outstanding.1176660449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3765524065 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 95338380 ps |
| CPU time | 3.93 seconds |
| Started | Oct 09 02:31:30 PM UTC 24 |
| Finished | Oct 09 02:31:35 PM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765524065 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors.3765524065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1853125587 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 369950642 ps |
| CPU time | 10.01 seconds |
| Started | Oct 09 02:31:32 PM UTC 24 |
| Finished | Oct 09 02:31:43 PM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853125587 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors_with_csr_rw.1853125587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_errors.214513176 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 295653886 ps |
| CPU time | 5 seconds |
| Started | Oct 09 02:31:32 PM UTC 24 |
| Finished | Oct 09 02:31:38 PM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214513176 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.214513176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_intg_err.1304011801 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 940430364 ps |
| CPU time | 7.17 seconds |
| Started | Oct 09 02:31:32 PM UTC 24 |
| Finished | Oct 09 02:31:40 PM UTC 24 |
| Peak memory | 225496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304011801 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.1304011801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.266029696 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 183936229 ps |
| CPU time | 2.26 seconds |
| Started | Oct 09 02:31:39 PM UTC 24 |
| Finished | Oct 09 02:31:43 PM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=266029696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_mem_rw_wi th_rand_reset.266029696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_rw.1311271581 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 40196578 ps |
| CPU time | 2.28 seconds |
| Started | Oct 09 02:31:38 PM UTC 24 |
| Finished | Oct 09 02:31:42 PM UTC 24 |
| Peak memory | 215416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311271581 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1311271581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_intr_test.783637330 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 44450388 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 02:31:38 PM UTC 24 |
| Finished | Oct 09 02:31:40 PM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783637330 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.783637330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.689076208 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 94081773 ps |
| CPU time | 4.97 seconds |
| Started | Oct 09 02:31:38 PM UTC 24 |
| Finished | Oct 09 02:31:44 PM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689076208 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_same_csr_outstanding.689076208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.112781498 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 169986566 ps |
| CPU time | 6.14 seconds |
| Started | Oct 09 02:31:35 PM UTC 24 |
| Finished | Oct 09 02:31:42 PM UTC 24 |
| Peak memory | 229868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112781498 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors.112781498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1080554136 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 1300213589 ps |
| CPU time | 14.36 seconds |
| Started | Oct 09 02:31:36 PM UTC 24 |
| Finished | Oct 09 02:31:51 PM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080554136 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors_with_csr_rw.1080554136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_errors.391002857 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 43488806 ps |
| CPU time | 3.13 seconds |
| Started | Oct 09 02:31:37 PM UTC 24 |
| Finished | Oct 09 02:31:41 PM UTC 24 |
| Peak memory | 225432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391002857 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.391002857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_intg_err.4225723769 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 71443511 ps |
| CPU time | 4.45 seconds |
| Started | Oct 09 02:31:37 PM UTC 24 |
| Finished | Oct 09 02:31:42 PM UTC 24 |
| Peak memory | 225496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225723769 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.4225723769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.103637739 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 35072468 ps |
| CPU time | 1.85 seconds |
| Started | Oct 09 02:31:43 PM UTC 24 |
| Finished | Oct 09 02:31:46 PM UTC 24 |
| Peak memory | 222980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=103637739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_mem_rw_wi th_rand_reset.103637739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_rw.317426489 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 42097742 ps |
| CPU time | 1.58 seconds |
| Started | Oct 09 02:31:43 PM UTC 24 |
| Finished | Oct 09 02:31:46 PM UTC 24 |
| Peak memory | 212796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317426489 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.317426489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_intr_test.440542942 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 90374836 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 02:31:43 PM UTC 24 |
| Finished | Oct 09 02:31:45 PM UTC 24 |
| Peak memory | 212460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440542942 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.440542942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2220728860 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 35942694 ps |
| CPU time | 2.3 seconds |
| Started | Oct 09 02:31:43 PM UTC 24 |
| Finished | Oct 09 02:31:47 PM UTC 24 |
| Peak memory | 215644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220728860 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_same_csr_outstanding.2220728860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2283020118 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 295971434 ps |
| CPU time | 4.98 seconds |
| Started | Oct 09 02:31:40 PM UTC 24 |
| Finished | Oct 09 02:31:45 PM UTC 24 |
| Peak memory | 225908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283020118 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors.2283020118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1055740863 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 201924664 ps |
| CPU time | 6.46 seconds |
| Started | Oct 09 02:31:42 PM UTC 24 |
| Finished | Oct 09 02:31:49 PM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055740863 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors_with_csr_rw.1055740863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_errors.3736498292 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 135255990 ps |
| CPU time | 5.32 seconds |
| Started | Oct 09 02:31:42 PM UTC 24 |
| Finished | Oct 09 02:31:48 PM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736498292 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3736498292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/0.keymgr_custom_cm.2910140664 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 209319028 ps |
| CPU time | 5.29 seconds |
| Started | Oct 09 10:11:11 AM UTC 24 |
| Finished | Oct 09 10:11:17 AM UTC 24 |
| Peak memory | 225532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910140664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2910140664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/0.keymgr_direct_to_disabled.1219871238 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 245607855 ps |
| CPU time | 2.42 seconds |
| Started | Oct 09 10:11:06 AM UTC 24 |
| Finished | Oct 09 10:11:10 AM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219871238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1219871238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/0.keymgr_lc_disable.3385970014 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 69296577 ps |
| CPU time | 4.25 seconds |
| Started | Oct 09 10:11:07 AM UTC 24 |
| Finished | Oct 09 10:11:13 AM UTC 24 |
| Peak memory | 227568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385970014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3385970014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/0.keymgr_sideload.2352982700 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 40739357 ps |
| CPU time | 3.46 seconds |
| Started | Oct 09 10:11:01 AM UTC 24 |
| Finished | Oct 09 10:11:05 AM UTC 24 |
| Peak memory | 217540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352982700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2352982700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_aes.2027247736 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 707644576 ps |
| CPU time | 19.84 seconds |
| Started | Oct 09 10:11:03 AM UTC 24 |
| Finished | Oct 09 10:11:25 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027247736 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2027247736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_kmac.1907142078 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 223868964 ps |
| CPU time | 7.07 seconds |
| Started | Oct 09 10:11:02 AM UTC 24 |
| Finished | Oct 09 10:11:10 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907142078 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1907142078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_protect.1554808854 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 51438774 ps |
| CPU time | 3.03 seconds |
| Started | Oct 09 10:11:11 AM UTC 24 |
| Finished | Oct 09 10:11:15 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554808854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1554808854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/0.keymgr_smoke.2773835915 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 263717697 ps |
| CPU time | 4.51 seconds |
| Started | Oct 09 10:11:01 AM UTC 24 |
| Finished | Oct 09 10:11:06 AM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773835915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2773835915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/0.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/1.keymgr_alert_test.3148034317 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 15313833 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 10:11:31 AM UTC 24 |
| Finished | Oct 09 10:11:34 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148034317 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3148034317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/1.keymgr_direct_to_disabled.3835557323 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 82890260 ps |
| CPU time | 4.77 seconds |
| Started | Oct 09 10:11:23 AM UTC 24 |
| Finished | Oct 09 10:11:29 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835557323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3835557323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/1.keymgr_lc_disable.2375461025 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 108064937 ps |
| CPU time | 3.12 seconds |
| Started | Oct 09 10:11:24 AM UTC 24 |
| Finished | Oct 09 10:11:28 AM UTC 24 |
| Peak memory | 227640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375461025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2375461025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/1.keymgr_random.1721486125 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 79579446 ps |
| CPU time | 5.5 seconds |
| Started | Oct 09 10:11:21 AM UTC 24 |
| Finished | Oct 09 10:11:27 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721486125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1721486125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/1.keymgr_sec_cm.3594264174 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 895640508 ps |
| CPU time | 17.06 seconds |
| Started | Oct 09 10:11:30 AM UTC 24 |
| Finished | Oct 09 10:11:48 AM UTC 24 |
| Peak memory | 254080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594264174 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3594264174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/1.keymgr_sideload.2440701580 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 205944690 ps |
| CPU time | 3.15 seconds |
| Started | Oct 09 10:11:18 AM UTC 24 |
| Finished | Oct 09 10:11:23 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440701580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2440701580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_kmac.116167324 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 179200055 ps |
| CPU time | 2.82 seconds |
| Started | Oct 09 10:11:20 AM UTC 24 |
| Finished | Oct 09 10:11:24 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116167324 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.116167324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_protect.2407662964 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 108747493 ps |
| CPU time | 5 seconds |
| Started | Oct 09 10:11:29 AM UTC 24 |
| Finished | Oct 09 10:11:35 AM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407662964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2407662964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/1.keymgr_smoke.3703396489 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 238290588 ps |
| CPU time | 4.8 seconds |
| Started | Oct 09 10:11:18 AM UTC 24 |
| Finished | Oct 09 10:11:24 AM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703396489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3703396489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/1.keymgr_sw_invalid_input.451582484 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 166680700 ps |
| CPU time | 6.42 seconds |
| Started | Oct 09 10:11:24 AM UTC 24 |
| Finished | Oct 09 10:11:32 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451582484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.451582484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/1.keymgr_sync_async_fault_cross.1867259626 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 274200678 ps |
| CPU time | 4.13 seconds |
| Started | Oct 09 10:11:29 AM UTC 24 |
| Finished | Oct 09 10:11:34 AM UTC 24 |
| Peak memory | 217404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867259626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1867259626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/1.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/10.keymgr_alert_test.1973255959 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 24144129 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 10:12:57 AM UTC 24 |
| Finished | Oct 09 10:12:59 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973255959 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1973255959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/10.keymgr_cfg_regwen.1168060103 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 119822577 ps |
| CPU time | 4.87 seconds |
| Started | Oct 09 10:12:49 AM UTC 24 |
| Finished | Oct 09 10:12:55 AM UTC 24 |
| Peak memory | 225588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168060103 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1168060103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/10.keymgr_custom_cm.671995604 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 215122550 ps |
| CPU time | 4.52 seconds |
| Started | Oct 09 10:12:54 AM UTC 24 |
| Finished | Oct 09 10:13:00 AM UTC 24 |
| Peak memory | 232176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671995604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.671995604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/10.keymgr_direct_to_disabled.2086144809 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 28326158 ps |
| CPU time | 2.6 seconds |
| Started | Oct 09 10:12:50 AM UTC 24 |
| Finished | Oct 09 10:12:54 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086144809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2086144809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/10.keymgr_hwsw_invalid_input.2340032995 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 83897818 ps |
| CPU time | 3.37 seconds |
| Started | Oct 09 10:12:53 AM UTC 24 |
| Finished | Oct 09 10:12:58 AM UTC 24 |
| Peak memory | 223548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340032995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2340032995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/10.keymgr_lc_disable.3012172201 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 211174793 ps |
| CPU time | 4.26 seconds |
| Started | Oct 09 10:12:51 AM UTC 24 |
| Finished | Oct 09 10:12:56 AM UTC 24 |
| Peak memory | 223544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012172201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3012172201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/10.keymgr_random.3906991189 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 258435413 ps |
| CPU time | 3.52 seconds |
| Started | Oct 09 10:12:49 AM UTC 24 |
| Finished | Oct 09 10:12:53 AM UTC 24 |
| Peak memory | 217596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906991189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3906991189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/10.keymgr_sideload.542799233 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 728915600 ps |
| CPU time | 7.1 seconds |
| Started | Oct 09 10:12:47 AM UTC 24 |
| Finished | Oct 09 10:12:56 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542799233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.542799233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_aes.3332033893 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 413257083 ps |
| CPU time | 13.84 seconds |
| Started | Oct 09 10:12:48 AM UTC 24 |
| Finished | Oct 09 10:13:04 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332033893 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3332033893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_kmac.3434430953 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 133279532 ps |
| CPU time | 2.79 seconds |
| Started | Oct 09 10:12:48 AM UTC 24 |
| Finished | Oct 09 10:12:52 AM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434430953 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3434430953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_otbn.4261937183 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 90365550 ps |
| CPU time | 4.97 seconds |
| Started | Oct 09 10:12:49 AM UTC 24 |
| Finished | Oct 09 10:12:55 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261937183 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.4261937183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_protect.4166606290 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 196819987 ps |
| CPU time | 5.73 seconds |
| Started | Oct 09 10:12:54 AM UTC 24 |
| Finished | Oct 09 10:13:01 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166606290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.4166606290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/10.keymgr_smoke.1416333822 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1414312919 ps |
| CPU time | 5.49 seconds |
| Started | Oct 09 10:12:46 AM UTC 24 |
| Finished | Oct 09 10:12:53 AM UTC 24 |
| Peak memory | 215620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416333822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1416333822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/10.keymgr_sw_invalid_input.811856903 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 507524349 ps |
| CPU time | 14.35 seconds |
| Started | Oct 09 10:12:53 AM UTC 24 |
| Finished | Oct 09 10:13:09 AM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811856903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.811856903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/10.keymgr_sync_async_fault_cross.3569473656 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 142271019 ps |
| CPU time | 3.75 seconds |
| Started | Oct 09 10:12:56 AM UTC 24 |
| Finished | Oct 09 10:13:00 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569473656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3569473656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/10.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/11.keymgr_alert_test.2762056727 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 38756343 ps |
| CPU time | 1.35 seconds |
| Started | Oct 09 10:13:07 AM UTC 24 |
| Finished | Oct 09 10:13:10 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762056727 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2762056727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/11.keymgr_cfg_regwen.827273559 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 3375577871 ps |
| CPU time | 10.24 seconds |
| Started | Oct 09 10:12:59 AM UTC 24 |
| Finished | Oct 09 10:13:11 AM UTC 24 |
| Peak memory | 223868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827273559 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.827273559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/11.keymgr_custom_cm.2891467509 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 120855962 ps |
| CPU time | 2.47 seconds |
| Started | Oct 09 10:13:03 AM UTC 24 |
| Finished | Oct 09 10:13:06 AM UTC 24 |
| Peak memory | 227976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891467509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2891467509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/11.keymgr_direct_to_disabled.3610264612 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 213926766 ps |
| CPU time | 7.3 seconds |
| Started | Oct 09 10:13:00 AM UTC 24 |
| Finished | Oct 09 10:13:08 AM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610264612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3610264612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/11.keymgr_hwsw_invalid_input.3572906009 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 129148880 ps |
| CPU time | 5.88 seconds |
| Started | Oct 09 10:13:02 AM UTC 24 |
| Finished | Oct 09 10:13:09 AM UTC 24 |
| Peak memory | 229828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572906009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3572906009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/11.keymgr_lc_disable.3380331341 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 56570714 ps |
| CPU time | 2.48 seconds |
| Started | Oct 09 10:13:02 AM UTC 24 |
| Finished | Oct 09 10:13:05 AM UTC 24 |
| Peak memory | 223408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380331341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3380331341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/11.keymgr_random.285359370 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 1307667610 ps |
| CPU time | 6.13 seconds |
| Started | Oct 09 10:12:59 AM UTC 24 |
| Finished | Oct 09 10:13:07 AM UTC 24 |
| Peak memory | 217656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285359370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.285359370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/11.keymgr_sideload.343768933 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 79573398 ps |
| CPU time | 2.52 seconds |
| Started | Oct 09 10:12:57 AM UTC 24 |
| Finished | Oct 09 10:13:01 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343768933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.343768933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_aes.3126888076 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 94908552 ps |
| CPU time | 3.57 seconds |
| Started | Oct 09 10:12:58 AM UTC 24 |
| Finished | Oct 09 10:13:03 AM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126888076 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3126888076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_otbn.4227187109 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 59463764 ps |
| CPU time | 3.93 seconds |
| Started | Oct 09 10:12:59 AM UTC 24 |
| Finished | Oct 09 10:13:04 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227187109 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.4227187109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_protect.3418201708 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 243663174 ps |
| CPU time | 5.21 seconds |
| Started | Oct 09 10:13:04 AM UTC 24 |
| Finished | Oct 09 10:13:11 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418201708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3418201708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/11.keymgr_smoke.1040928642 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 326651817 ps |
| CPU time | 7.44 seconds |
| Started | Oct 09 10:12:57 AM UTC 24 |
| Finished | Oct 09 10:13:05 AM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040928642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1040928642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all.4065422117 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 599303982 ps |
| CPU time | 6.48 seconds |
| Started | Oct 09 10:13:04 AM UTC 24 |
| Finished | Oct 09 10:13:12 AM UTC 24 |
| Peak memory | 229956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065422117 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.4065422117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/11.keymgr_sw_invalid_input.2448886732 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 293824022 ps |
| CPU time | 8.64 seconds |
| Started | Oct 09 10:13:02 AM UTC 24 |
| Finished | Oct 09 10:13:11 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448886732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2448886732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/11.keymgr_sync_async_fault_cross.2086067900 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 96386760 ps |
| CPU time | 2.36 seconds |
| Started | Oct 09 10:13:04 AM UTC 24 |
| Finished | Oct 09 10:13:08 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086067900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2086067900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/11.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/12.keymgr_alert_test.1388369138 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 15310006 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 10:13:13 AM UTC 24 |
| Finished | Oct 09 10:13:15 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388369138 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1388369138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/12.keymgr_cfg_regwen.4127561754 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 263160619 ps |
| CPU time | 14.12 seconds |
| Started | Oct 09 10:13:10 AM UTC 24 |
| Finished | Oct 09 10:13:26 AM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127561754 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.4127561754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/12.keymgr_custom_cm.1337986730 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 362267990 ps |
| CPU time | 6.98 seconds |
| Started | Oct 09 10:13:12 AM UTC 24 |
| Finished | Oct 09 10:13:20 AM UTC 24 |
| Peak memory | 217736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337986730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1337986730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/12.keymgr_direct_to_disabled.484599690 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 61182456 ps |
| CPU time | 4.25 seconds |
| Started | Oct 09 10:13:10 AM UTC 24 |
| Finished | Oct 09 10:13:16 AM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484599690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.484599690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/12.keymgr_random.4153296220 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 139780214 ps |
| CPU time | 5.41 seconds |
| Started | Oct 09 10:13:09 AM UTC 24 |
| Finished | Oct 09 10:13:16 AM UTC 24 |
| Peak memory | 229692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153296220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.4153296220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/12.keymgr_sideload.3323896468 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 802563208 ps |
| CPU time | 21.19 seconds |
| Started | Oct 09 10:13:07 AM UTC 24 |
| Finished | Oct 09 10:13:30 AM UTC 24 |
| Peak memory | 217476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323896468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3323896468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_aes.3036226230 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 64154227 ps |
| CPU time | 3.24 seconds |
| Started | Oct 09 10:13:08 AM UTC 24 |
| Finished | Oct 09 10:13:13 AM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036226230 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3036226230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_kmac.3116632858 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 587132466 ps |
| CPU time | 19.92 seconds |
| Started | Oct 09 10:13:08 AM UTC 24 |
| Finished | Oct 09 10:13:29 AM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116632858 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3116632858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_otbn.2553644221 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 6774049361 ps |
| CPU time | 62.48 seconds |
| Started | Oct 09 10:13:09 AM UTC 24 |
| Finished | Oct 09 10:14:14 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553644221 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2553644221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_protect.835953684 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 787141307 ps |
| CPU time | 4.87 seconds |
| Started | Oct 09 10:13:12 AM UTC 24 |
| Finished | Oct 09 10:13:18 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835953684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.835953684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/12.keymgr_smoke.2436557474 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 2931308121 ps |
| CPU time | 20.45 seconds |
| Started | Oct 09 10:13:07 AM UTC 24 |
| Finished | Oct 09 10:13:29 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436557474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2436557474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all.2109505723 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1458156794 ps |
| CPU time | 39.41 seconds |
| Started | Oct 09 10:13:13 AM UTC 24 |
| Finished | Oct 09 10:13:54 AM UTC 24 |
| Peak memory | 231672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109505723 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2109505723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/12.keymgr_sw_invalid_input.1828870952 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 480406246 ps |
| CPU time | 7.34 seconds |
| Started | Oct 09 10:13:10 AM UTC 24 |
| Finished | Oct 09 10:13:19 AM UTC 24 |
| Peak memory | 227720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828870952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1828870952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/12.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/13.keymgr_alert_test.302363139 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 17178078 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 10:13:24 AM UTC 24 |
| Finished | Oct 09 10:13:27 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302363139 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.302363139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/13.keymgr_cfg_regwen.2739079863 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 70354237 ps |
| CPU time | 3.69 seconds |
| Started | Oct 09 10:13:17 AM UTC 24 |
| Finished | Oct 09 10:13:22 AM UTC 24 |
| Peak memory | 223468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739079863 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2739079863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/13.keymgr_custom_cm.598466190 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1067966314 ps |
| CPU time | 5.1 seconds |
| Started | Oct 09 10:13:20 AM UTC 24 |
| Finished | Oct 09 10:13:27 AM UTC 24 |
| Peak memory | 229692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598466190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.598466190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/13.keymgr_direct_to_disabled.4209091577 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 361455335 ps |
| CPU time | 5.06 seconds |
| Started | Oct 09 10:13:17 AM UTC 24 |
| Finished | Oct 09 10:13:23 AM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209091577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.4209091577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/13.keymgr_lc_disable.792236814 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 531936597 ps |
| CPU time | 7.95 seconds |
| Started | Oct 09 10:13:18 AM UTC 24 |
| Finished | Oct 09 10:13:27 AM UTC 24 |
| Peak memory | 229936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792236814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.792236814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/13.keymgr_random.2921399602 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 84273694 ps |
| CPU time | 5.27 seconds |
| Started | Oct 09 10:13:17 AM UTC 24 |
| Finished | Oct 09 10:13:23 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921399602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2921399602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/13.keymgr_sideload.2012416400 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 38652545 ps |
| CPU time | 2.58 seconds |
| Started | Oct 09 10:13:14 AM UTC 24 |
| Finished | Oct 09 10:13:18 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012416400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2012416400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_aes.3124765109 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 655083561 ps |
| CPU time | 20.46 seconds |
| Started | Oct 09 10:13:17 AM UTC 24 |
| Finished | Oct 09 10:13:38 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124765109 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3124765109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_kmac.290257134 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 226562963 ps |
| CPU time | 3.91 seconds |
| Started | Oct 09 10:13:16 AM UTC 24 |
| Finished | Oct 09 10:13:22 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290257134 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.290257134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_otbn.546888534 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 812549329 ps |
| CPU time | 9.93 seconds |
| Started | Oct 09 10:13:17 AM UTC 24 |
| Finished | Oct 09 10:13:28 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546888534 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.546888534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_protect.230777278 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 188281828 ps |
| CPU time | 3.78 seconds |
| Started | Oct 09 10:13:21 AM UTC 24 |
| Finished | Oct 09 10:13:27 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230777278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.230777278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/13.keymgr_smoke.989235345 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 124638171 ps |
| CPU time | 2.98 seconds |
| Started | Oct 09 10:13:13 AM UTC 24 |
| Finished | Oct 09 10:13:17 AM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989235345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.989235345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all_with_rand_reset.2551945500 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 436606720 ps |
| CPU time | 13.09 seconds |
| Started | Oct 09 10:13:23 AM UTC 24 |
| Finished | Oct 09 10:13:37 AM UTC 24 |
| Peak memory | 231628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2551945500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymg r_stress_all_with_rand_reset.2551945500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/13.keymgr_sw_invalid_input.3452330571 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 289729172 ps |
| CPU time | 8.18 seconds |
| Started | Oct 09 10:13:19 AM UTC 24 |
| Finished | Oct 09 10:13:28 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452330571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3452330571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/13.keymgr_sync_async_fault_cross.1699096286 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 493697758 ps |
| CPU time | 3.58 seconds |
| Started | Oct 09 10:13:23 AM UTC 24 |
| Finished | Oct 09 10:13:28 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699096286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1699096286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/13.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/14.keymgr_alert_test.247061262 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 56917386 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 10:13:33 AM UTC 24 |
| Finished | Oct 09 10:13:36 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247061262 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.247061262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/14.keymgr_cfg_regwen.575043173 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 1370636174 ps |
| CPU time | 35.3 seconds |
| Started | Oct 09 10:13:28 AM UTC 24 |
| Finished | Oct 09 10:14:06 AM UTC 24 |
| Peak memory | 225776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575043173 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.575043173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/14.keymgr_custom_cm.3414596485 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 213593404 ps |
| CPU time | 2.73 seconds |
| Started | Oct 09 10:13:30 AM UTC 24 |
| Finished | Oct 09 10:13:34 AM UTC 24 |
| Peak memory | 225596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414596485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3414596485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/14.keymgr_direct_to_disabled.676707423 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 51240381 ps |
| CPU time | 2.95 seconds |
| Started | Oct 09 10:13:28 AM UTC 24 |
| Finished | Oct 09 10:13:33 AM UTC 24 |
| Peak memory | 223536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676707423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.676707423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/14.keymgr_hwsw_invalid_input.522368676 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 44470648 ps |
| CPU time | 3.79 seconds |
| Started | Oct 09 10:13:30 AM UTC 24 |
| Finished | Oct 09 10:13:35 AM UTC 24 |
| Peak memory | 223868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522368676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.522368676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/14.keymgr_kmac_rsp_err.1870850840 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 1223139738 ps |
| CPU time | 5.42 seconds |
| Started | Oct 09 10:13:30 AM UTC 24 |
| Finished | Oct 09 10:13:37 AM UTC 24 |
| Peak memory | 231188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870850840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1870850840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/14.keymgr_lc_disable.2415118888 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 70813773 ps |
| CPU time | 2.46 seconds |
| Started | Oct 09 10:13:29 AM UTC 24 |
| Finished | Oct 09 10:13:33 AM UTC 24 |
| Peak memory | 229616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415118888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2415118888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/14.keymgr_random.922064044 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 2055341465 ps |
| CPU time | 11.43 seconds |
| Started | Oct 09 10:13:28 AM UTC 24 |
| Finished | Oct 09 10:13:41 AM UTC 24 |
| Peak memory | 227728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922064044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.922064044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/14.keymgr_sideload.1130876976 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 118418897 ps |
| CPU time | 3.56 seconds |
| Started | Oct 09 10:13:26 AM UTC 24 |
| Finished | Oct 09 10:13:31 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130876976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1130876976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_aes.3874405754 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 50726737 ps |
| CPU time | 2.42 seconds |
| Started | Oct 09 10:13:27 AM UTC 24 |
| Finished | Oct 09 10:13:31 AM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874405754 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3874405754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_kmac.4193363138 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 366880724 ps |
| CPU time | 13.17 seconds |
| Started | Oct 09 10:13:27 AM UTC 24 |
| Finished | Oct 09 10:13:42 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193363138 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.4193363138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_otbn.1492090192 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 136848948 ps |
| CPU time | 3.17 seconds |
| Started | Oct 09 10:13:28 AM UTC 24 |
| Finished | Oct 09 10:13:33 AM UTC 24 |
| Peak memory | 217664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492090192 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1492090192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_protect.4104190686 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 42094016 ps |
| CPU time | 3.46 seconds |
| Started | Oct 09 10:13:31 AM UTC 24 |
| Finished | Oct 09 10:13:36 AM UTC 24 |
| Peak memory | 229688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104190686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.4104190686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/14.keymgr_smoke.219324588 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 526178618 ps |
| CPU time | 10.56 seconds |
| Started | Oct 09 10:13:24 AM UTC 24 |
| Finished | Oct 09 10:13:36 AM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219324588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.219324588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all_with_rand_reset.2418757462 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 516770768 ps |
| CPU time | 18.14 seconds |
| Started | Oct 09 10:13:32 AM UTC 24 |
| Finished | Oct 09 10:13:52 AM UTC 24 |
| Peak memory | 231744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2418757462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymg r_stress_all_with_rand_reset.2418757462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/14.keymgr_sw_invalid_input.2930535935 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 416535191 ps |
| CPU time | 6.29 seconds |
| Started | Oct 09 10:13:29 AM UTC 24 |
| Finished | Oct 09 10:13:37 AM UTC 24 |
| Peak memory | 217664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930535935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2930535935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/14.keymgr_sync_async_fault_cross.2592321152 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 78273800 ps |
| CPU time | 2.69 seconds |
| Started | Oct 09 10:13:31 AM UTC 24 |
| Finished | Oct 09 10:13:35 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592321152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2592321152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/14.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/15.keymgr_alert_test.882484580 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 10954546 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 10:13:43 AM UTC 24 |
| Finished | Oct 09 10:13:45 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882484580 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.882484580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/15.keymgr_custom_cm.1514943081 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 148247253 ps |
| CPU time | 6.62 seconds |
| Started | Oct 09 10:13:40 AM UTC 24 |
| Finished | Oct 09 10:13:47 AM UTC 24 |
| Peak memory | 224016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514943081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1514943081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/15.keymgr_direct_to_disabled.2360798087 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 23233933 ps |
| CPU time | 2.43 seconds |
| Started | Oct 09 10:13:37 AM UTC 24 |
| Finished | Oct 09 10:13:41 AM UTC 24 |
| Peak memory | 217420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360798087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2360798087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/15.keymgr_hwsw_invalid_input.762081624 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 818483374 ps |
| CPU time | 6.81 seconds |
| Started | Oct 09 10:13:38 AM UTC 24 |
| Finished | Oct 09 10:13:46 AM UTC 24 |
| Peak memory | 217460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762081624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.762081624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/15.keymgr_lc_disable.814493498 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 122111098 ps |
| CPU time | 3.21 seconds |
| Started | Oct 09 10:13:37 AM UTC 24 |
| Finished | Oct 09 10:13:41 AM UTC 24 |
| Peak memory | 229884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814493498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.814493498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/15.keymgr_random.3411521957 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 166425763 ps |
| CPU time | 4.43 seconds |
| Started | Oct 09 10:13:37 AM UTC 24 |
| Finished | Oct 09 10:13:42 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411521957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3411521957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/15.keymgr_sideload.4293865040 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 250400037 ps |
| CPU time | 4.33 seconds |
| Started | Oct 09 10:13:34 AM UTC 24 |
| Finished | Oct 09 10:13:39 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293865040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.4293865040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_aes.2500891653 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 148857095 ps |
| CPU time | 4.51 seconds |
| Started | Oct 09 10:13:36 AM UTC 24 |
| Finished | Oct 09 10:13:41 AM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500891653 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2500891653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_kmac.2423511290 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 5485011323 ps |
| CPU time | 62.93 seconds |
| Started | Oct 09 10:13:35 AM UTC 24 |
| Finished | Oct 09 10:14:39 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423511290 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2423511290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_otbn.2613788328 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 317155402 ps |
| CPU time | 5.39 seconds |
| Started | Oct 09 10:13:36 AM UTC 24 |
| Finished | Oct 09 10:13:42 AM UTC 24 |
| Peak memory | 217320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613788328 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2613788328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_protect.2906444228 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 690814091 ps |
| CPU time | 23.72 seconds |
| Started | Oct 09 10:13:42 AM UTC 24 |
| Finished | Oct 09 10:14:07 AM UTC 24 |
| Peak memory | 223800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906444228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2906444228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/15.keymgr_smoke.3718734317 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1243330583 ps |
| CPU time | 7.04 seconds |
| Started | Oct 09 10:13:33 AM UTC 24 |
| Finished | Oct 09 10:13:42 AM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718734317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3718734317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all.3029020052 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 412873724 ps |
| CPU time | 4.92 seconds |
| Started | Oct 09 10:13:43 AM UTC 24 |
| Finished | Oct 09 10:13:49 AM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029020052 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3029020052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/15.keymgr_sw_invalid_input.3472581785 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 87774536 ps |
| CPU time | 5.36 seconds |
| Started | Oct 09 10:13:37 AM UTC 24 |
| Finished | Oct 09 10:13:44 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472581785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3472581785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/15.keymgr_sync_async_fault_cross.3722044458 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 80050569 ps |
| CPU time | 3.07 seconds |
| Started | Oct 09 10:13:43 AM UTC 24 |
| Finished | Oct 09 10:13:47 AM UTC 24 |
| Peak memory | 217476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722044458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3722044458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/15.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/16.keymgr_alert_test.1596128338 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 37743458 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 10:13:52 AM UTC 24 |
| Finished | Oct 09 10:13:54 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596128338 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1596128338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/16.keymgr_custom_cm.1628129402 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 47798482 ps |
| CPU time | 3.89 seconds |
| Started | Oct 09 10:13:49 AM UTC 24 |
| Finished | Oct 09 10:13:54 AM UTC 24 |
| Peak memory | 227644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628129402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1628129402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/16.keymgr_direct_to_disabled.2349600739 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 36654618 ps |
| CPU time | 2.76 seconds |
| Started | Oct 09 10:13:47 AM UTC 24 |
| Finished | Oct 09 10:13:51 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349600739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2349600739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/16.keymgr_kmac_rsp_err.1447993495 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 116393243 ps |
| CPU time | 2.72 seconds |
| Started | Oct 09 10:13:48 AM UTC 24 |
| Finished | Oct 09 10:13:52 AM UTC 24 |
| Peak memory | 223428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447993495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1447993495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/16.keymgr_lc_disable.97943989 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 1639525382 ps |
| CPU time | 6.69 seconds |
| Started | Oct 09 10:13:48 AM UTC 24 |
| Finished | Oct 09 10:13:56 AM UTC 24 |
| Peak memory | 229776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97943989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.97943989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/16.keymgr_random.358830687 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 108061047 ps |
| CPU time | 4.77 seconds |
| Started | Oct 09 10:13:47 AM UTC 24 |
| Finished | Oct 09 10:13:52 AM UTC 24 |
| Peak memory | 227572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358830687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.358830687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/16.keymgr_sideload.3183693574 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 184025708 ps |
| CPU time | 3.14 seconds |
| Started | Oct 09 10:13:43 AM UTC 24 |
| Finished | Oct 09 10:13:47 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183693574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3183693574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_aes.2303970674 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 253038702 ps |
| CPU time | 4.24 seconds |
| Started | Oct 09 10:13:44 AM UTC 24 |
| Finished | Oct 09 10:13:50 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303970674 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2303970674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_kmac.3599440024 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 151800648 ps |
| CPU time | 4.06 seconds |
| Started | Oct 09 10:13:44 AM UTC 24 |
| Finished | Oct 09 10:13:49 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599440024 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3599440024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_otbn.985504760 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 42813142 ps |
| CPU time | 3.35 seconds |
| Started | Oct 09 10:13:45 AM UTC 24 |
| Finished | Oct 09 10:13:50 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985504760 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.985504760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_protect.2984399722 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 38942186 ps |
| CPU time | 2.71 seconds |
| Started | Oct 09 10:13:50 AM UTC 24 |
| Finished | Oct 09 10:13:54 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984399722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2984399722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/16.keymgr_smoke.3757270406 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1337730053 ps |
| CPU time | 6.6 seconds |
| Started | Oct 09 10:13:43 AM UTC 24 |
| Finished | Oct 09 10:13:51 AM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757270406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3757270406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all.3970540955 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 246059511 ps |
| CPU time | 12 seconds |
| Started | Oct 09 10:13:50 AM UTC 24 |
| Finished | Oct 09 10:14:04 AM UTC 24 |
| Peak memory | 227568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970540955 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3970540955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all_with_rand_reset.2423272480 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 510794850 ps |
| CPU time | 19.24 seconds |
| Started | Oct 09 10:13:50 AM UTC 24 |
| Finished | Oct 09 10:14:11 AM UTC 24 |
| Peak memory | 231740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2423272480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymg r_stress_all_with_rand_reset.2423272480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/16.keymgr_sw_invalid_input.2057814843 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1509370588 ps |
| CPU time | 9.69 seconds |
| Started | Oct 09 10:13:48 AM UTC 24 |
| Finished | Oct 09 10:13:59 AM UTC 24 |
| Peak memory | 217468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057814843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2057814843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/16.keymgr_sync_async_fault_cross.3084936097 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 226663801 ps |
| CPU time | 2.67 seconds |
| Started | Oct 09 10:13:50 AM UTC 24 |
| Finished | Oct 09 10:13:54 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084936097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3084936097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/16.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/17.keymgr_alert_test.1270672627 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 29975830 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 10:14:00 AM UTC 24 |
| Finished | Oct 09 10:14:02 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270672627 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1270672627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/17.keymgr_cfg_regwen.3292690731 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 66052616 ps |
| CPU time | 5.83 seconds |
| Started | Oct 09 10:13:54 AM UTC 24 |
| Finished | Oct 09 10:14:01 AM UTC 24 |
| Peak memory | 223468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292690731 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3292690731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/17.keymgr_direct_to_disabled.4275589117 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 66762440 ps |
| CPU time | 2.6 seconds |
| Started | Oct 09 10:13:55 AM UTC 24 |
| Finished | Oct 09 10:13:59 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275589117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.4275589117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/17.keymgr_hwsw_invalid_input.112943254 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 44434072 ps |
| CPU time | 2.5 seconds |
| Started | Oct 09 10:13:56 AM UTC 24 |
| Finished | Oct 09 10:13:59 AM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112943254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.112943254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/17.keymgr_kmac_rsp_err.1625263792 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 251066740 ps |
| CPU time | 3.49 seconds |
| Started | Oct 09 10:13:57 AM UTC 24 |
| Finished | Oct 09 10:14:01 AM UTC 24 |
| Peak memory | 223484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625263792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1625263792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/17.keymgr_lc_disable.3274505670 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 671906029 ps |
| CPU time | 4.59 seconds |
| Started | Oct 09 10:13:55 AM UTC 24 |
| Finished | Oct 09 10:14:01 AM UTC 24 |
| Peak memory | 223568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274505670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3274505670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/17.keymgr_random.1291620767 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 237329532 ps |
| CPU time | 5.43 seconds |
| Started | Oct 09 10:13:53 AM UTC 24 |
| Finished | Oct 09 10:14:00 AM UTC 24 |
| Peak memory | 217404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291620767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1291620767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/17.keymgr_sideload.2554675461 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 58649586 ps |
| CPU time | 4.11 seconds |
| Started | Oct 09 10:13:52 AM UTC 24 |
| Finished | Oct 09 10:13:57 AM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554675461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2554675461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_aes.3312187869 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 67619853 ps |
| CPU time | 4 seconds |
| Started | Oct 09 10:13:53 AM UTC 24 |
| Finished | Oct 09 10:13:58 AM UTC 24 |
| Peak memory | 217460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312187869 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3312187869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_kmac.3037593311 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 228876503 ps |
| CPU time | 8.79 seconds |
| Started | Oct 09 10:13:53 AM UTC 24 |
| Finished | Oct 09 10:14:03 AM UTC 24 |
| Peak memory | 217660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037593311 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3037593311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_otbn.868824106 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 650931334 ps |
| CPU time | 5.65 seconds |
| Started | Oct 09 10:13:53 AM UTC 24 |
| Finished | Oct 09 10:14:00 AM UTC 24 |
| Peak memory | 217320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868824106 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.868824106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_protect.1983934639 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 149633013 ps |
| CPU time | 5 seconds |
| Started | Oct 09 10:13:58 AM UTC 24 |
| Finished | Oct 09 10:14:04 AM UTC 24 |
| Peak memory | 223544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983934639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1983934639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/17.keymgr_smoke.3477408800 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 367158156 ps |
| CPU time | 4.79 seconds |
| Started | Oct 09 10:13:52 AM UTC 24 |
| Finished | Oct 09 10:13:57 AM UTC 24 |
| Peak memory | 217668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477408800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3477408800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all.3729853858 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1385457276 ps |
| CPU time | 25.54 seconds |
| Started | Oct 09 10:13:59 AM UTC 24 |
| Finished | Oct 09 10:14:26 AM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729853858 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3729853858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/17.keymgr_sw_invalid_input.3711066914 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 407348778 ps |
| CPU time | 6.63 seconds |
| Started | Oct 09 10:13:55 AM UTC 24 |
| Finished | Oct 09 10:14:03 AM UTC 24 |
| Peak memory | 217464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711066914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3711066914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/17.keymgr_sync_async_fault_cross.441083726 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 139922082 ps |
| CPU time | 1.95 seconds |
| Started | Oct 09 10:13:58 AM UTC 24 |
| Finished | Oct 09 10:14:01 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441083726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.441083726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/17.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/18.keymgr_alert_test.4196648421 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 71896249 ps |
| CPU time | 1.49 seconds |
| Started | Oct 09 10:14:07 AM UTC 24 |
| Finished | Oct 09 10:14:09 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196648421 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.4196648421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/18.keymgr_cfg_regwen.2810431643 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 43507010 ps |
| CPU time | 2.94 seconds |
| Started | Oct 09 10:14:02 AM UTC 24 |
| Finished | Oct 09 10:14:06 AM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810431643 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2810431643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/18.keymgr_custom_cm.3932312358 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 108080707 ps |
| CPU time | 6.11 seconds |
| Started | Oct 09 10:14:04 AM UTC 24 |
| Finished | Oct 09 10:14:12 AM UTC 24 |
| Peak memory | 217408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932312358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3932312358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/18.keymgr_direct_to_disabled.1468639334 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 2558352118 ps |
| CPU time | 32.12 seconds |
| Started | Oct 09 10:14:03 AM UTC 24 |
| Finished | Oct 09 10:14:36 AM UTC 24 |
| Peak memory | 223608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468639334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1468639334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/18.keymgr_kmac_rsp_err.1357643497 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 907019936 ps |
| CPU time | 4.73 seconds |
| Started | Oct 09 10:14:04 AM UTC 24 |
| Finished | Oct 09 10:14:10 AM UTC 24 |
| Peak memory | 223480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357643497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1357643497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/18.keymgr_lc_disable.733396670 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 86877924 ps |
| CPU time | 4.08 seconds |
| Started | Oct 09 10:14:03 AM UTC 24 |
| Finished | Oct 09 10:14:08 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733396670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.733396670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/18.keymgr_random.210271619 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 427361171 ps |
| CPU time | 3.48 seconds |
| Started | Oct 09 10:14:02 AM UTC 24 |
| Finished | Oct 09 10:14:06 AM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210271619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.210271619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/18.keymgr_sideload.1476630691 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 62883415 ps |
| CPU time | 2.88 seconds |
| Started | Oct 09 10:14:00 AM UTC 24 |
| Finished | Oct 09 10:14:04 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476630691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1476630691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_aes.2215359616 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 891509688 ps |
| CPU time | 8.37 seconds |
| Started | Oct 09 10:14:01 AM UTC 24 |
| Finished | Oct 09 10:14:11 AM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215359616 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2215359616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_kmac.1304134748 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 88120594 ps |
| CPU time | 3.85 seconds |
| Started | Oct 09 10:14:01 AM UTC 24 |
| Finished | Oct 09 10:14:06 AM UTC 24 |
| Peak memory | 217612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304134748 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1304134748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_otbn.2521250167 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 19434795920 ps |
| CPU time | 49.59 seconds |
| Started | Oct 09 10:14:02 AM UTC 24 |
| Finished | Oct 09 10:14:53 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521250167 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2521250167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_protect.2109258347 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 689514492 ps |
| CPU time | 7.32 seconds |
| Started | Oct 09 10:14:05 AM UTC 24 |
| Finished | Oct 09 10:14:14 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109258347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2109258347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/18.keymgr_smoke.904694713 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 128693368 ps |
| CPU time | 3.53 seconds |
| Started | Oct 09 10:14:00 AM UTC 24 |
| Finished | Oct 09 10:14:05 AM UTC 24 |
| Peak memory | 217548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904694713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.904694713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all.2515562038 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1313310196 ps |
| CPU time | 14.98 seconds |
| Started | Oct 09 10:14:06 AM UTC 24 |
| Finished | Oct 09 10:14:22 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515562038 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2515562038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all_with_rand_reset.2405216543 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 398664760 ps |
| CPU time | 10.17 seconds |
| Started | Oct 09 10:14:07 AM UTC 24 |
| Finished | Oct 09 10:14:18 AM UTC 24 |
| Peak memory | 229952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2405216543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymg r_stress_all_with_rand_reset.2405216543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/18.keymgr_sw_invalid_input.2886517477 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 619099603 ps |
| CPU time | 9.5 seconds |
| Started | Oct 09 10:14:03 AM UTC 24 |
| Finished | Oct 09 10:14:14 AM UTC 24 |
| Peak memory | 217648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886517477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2886517477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/18.keymgr_sync_async_fault_cross.376712526 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 487328250 ps |
| CPU time | 2.95 seconds |
| Started | Oct 09 10:14:05 AM UTC 24 |
| Finished | Oct 09 10:14:09 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376712526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.376712526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/18.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/19.keymgr_alert_test.2942041627 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 61861000 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 10:14:14 AM UTC 24 |
| Finished | Oct 09 10:14:17 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942041627 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2942041627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/19.keymgr_cfg_regwen.1217708655 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 57661602 ps |
| CPU time | 5.77 seconds |
| Started | Oct 09 10:14:10 AM UTC 24 |
| Finished | Oct 09 10:14:17 AM UTC 24 |
| Peak memory | 225544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217708655 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1217708655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/19.keymgr_custom_cm.1724831893 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 327065985 ps |
| CPU time | 5.82 seconds |
| Started | Oct 09 10:14:13 AM UTC 24 |
| Finished | Oct 09 10:14:20 AM UTC 24 |
| Peak memory | 230284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724831893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1724831893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/19.keymgr_direct_to_disabled.2681539425 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 308447473 ps |
| CPU time | 3.62 seconds |
| Started | Oct 09 10:14:11 AM UTC 24 |
| Finished | Oct 09 10:14:15 AM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681539425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2681539425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/19.keymgr_hwsw_invalid_input.788286193 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 103316055 ps |
| CPU time | 5.73 seconds |
| Started | Oct 09 10:14:12 AM UTC 24 |
| Finished | Oct 09 10:14:19 AM UTC 24 |
| Peak memory | 223740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788286193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.788286193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/19.keymgr_kmac_rsp_err.3832867362 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 42352859 ps |
| CPU time | 3.29 seconds |
| Started | Oct 09 10:14:13 AM UTC 24 |
| Finished | Oct 09 10:14:17 AM UTC 24 |
| Peak memory | 231452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832867362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3832867362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/19.keymgr_lc_disable.4156361200 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 84467641 ps |
| CPU time | 2.62 seconds |
| Started | Oct 09 10:14:11 AM UTC 24 |
| Finished | Oct 09 10:14:14 AM UTC 24 |
| Peak memory | 231540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156361200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.4156361200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/19.keymgr_random.1714569671 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 186995322 ps |
| CPU time | 9.13 seconds |
| Started | Oct 09 10:14:09 AM UTC 24 |
| Finished | Oct 09 10:14:20 AM UTC 24 |
| Peak memory | 223828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714569671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1714569671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/19.keymgr_sideload.1822826291 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 3229186754 ps |
| CPU time | 19.81 seconds |
| Started | Oct 09 10:14:07 AM UTC 24 |
| Finished | Oct 09 10:14:28 AM UTC 24 |
| Peak memory | 215608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822826291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1822826291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_aes.4285743558 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 177135190 ps |
| CPU time | 2.65 seconds |
| Started | Oct 09 10:14:08 AM UTC 24 |
| Finished | Oct 09 10:14:12 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285743558 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.4285743558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_kmac.973671800 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 185028786 ps |
| CPU time | 6.38 seconds |
| Started | Oct 09 10:14:08 AM UTC 24 |
| Finished | Oct 09 10:14:15 AM UTC 24 |
| Peak memory | 217664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973671800 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.973671800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_otbn.2846473201 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 237307830 ps |
| CPU time | 2.52 seconds |
| Started | Oct 09 10:14:09 AM UTC 24 |
| Finished | Oct 09 10:14:13 AM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846473201 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2846473201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_protect.826171799 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2531066671 ps |
| CPU time | 41.05 seconds |
| Started | Oct 09 10:14:13 AM UTC 24 |
| Finished | Oct 09 10:14:56 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826171799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.826171799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/19.keymgr_smoke.1701741837 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 244889480 ps |
| CPU time | 3.64 seconds |
| Started | Oct 09 10:14:07 AM UTC 24 |
| Finished | Oct 09 10:14:11 AM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701741837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1701741837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/19.keymgr_sw_invalid_input.763049746 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 186558408 ps |
| CPU time | 9.6 seconds |
| Started | Oct 09 10:14:12 AM UTC 24 |
| Finished | Oct 09 10:14:22 AM UTC 24 |
| Peak memory | 223544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763049746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.763049746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/19.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/2.keymgr_alert_test.2718022930 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 11626485 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 10:11:43 AM UTC 24 |
| Finished | Oct 09 10:11:45 AM UTC 24 |
| Peak memory | 212848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718022930 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2718022930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/2.keymgr_cfg_regwen.1549120934 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 203192866 ps |
| CPU time | 4.35 seconds |
| Started | Oct 09 10:11:35 AM UTC 24 |
| Finished | Oct 09 10:11:40 AM UTC 24 |
| Peak memory | 225780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549120934 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1549120934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/2.keymgr_hwsw_invalid_input.221819337 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 417418306 ps |
| CPU time | 4.37 seconds |
| Started | Oct 09 10:11:37 AM UTC 24 |
| Finished | Oct 09 10:11:42 AM UTC 24 |
| Peak memory | 223616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221819337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.221819337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/2.keymgr_kmac_rsp_err.2892812171 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 183622735 ps |
| CPU time | 4.43 seconds |
| Started | Oct 09 10:11:37 AM UTC 24 |
| Finished | Oct 09 10:11:43 AM UTC 24 |
| Peak memory | 223564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892812171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2892812171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/2.keymgr_lc_disable.1723511857 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 233508301 ps |
| CPU time | 3.31 seconds |
| Started | Oct 09 10:11:36 AM UTC 24 |
| Finished | Oct 09 10:11:40 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723511857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1723511857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/2.keymgr_random.3473205762 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 191984994 ps |
| CPU time | 6.26 seconds |
| Started | Oct 09 10:11:35 AM UTC 24 |
| Finished | Oct 09 10:11:42 AM UTC 24 |
| Peak memory | 217600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473205762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3473205762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/2.keymgr_sideload.166420399 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 53575070 ps |
| CPU time | 2.83 seconds |
| Started | Oct 09 10:11:32 AM UTC 24 |
| Finished | Oct 09 10:11:36 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166420399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.166420399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_aes.2533600476 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 259813791 ps |
| CPU time | 4.52 seconds |
| Started | Oct 09 10:11:33 AM UTC 24 |
| Finished | Oct 09 10:11:39 AM UTC 24 |
| Peak memory | 217664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533600476 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2533600476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_kmac.651026787 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2143051146 ps |
| CPU time | 36.12 seconds |
| Started | Oct 09 10:11:32 AM UTC 24 |
| Finished | Oct 09 10:12:10 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651026787 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.651026787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_otbn.694990047 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 199856761 ps |
| CPU time | 7.77 seconds |
| Started | Oct 09 10:11:33 AM UTC 24 |
| Finished | Oct 09 10:11:42 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694990047 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.694990047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_protect.4009963166 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 164578825 ps |
| CPU time | 5.79 seconds |
| Started | Oct 09 10:11:40 AM UTC 24 |
| Finished | Oct 09 10:11:47 AM UTC 24 |
| Peak memory | 217540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009963166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.4009963166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/2.keymgr_smoke.616658126 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 67851612 ps |
| CPU time | 3.18 seconds |
| Started | Oct 09 10:11:32 AM UTC 24 |
| Finished | Oct 09 10:11:37 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616658126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.616658126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all.2054672213 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 29165227932 ps |
| CPU time | 344.45 seconds |
| Started | Oct 09 10:11:41 AM UTC 24 |
| Finished | Oct 09 10:17:31 AM UTC 24 |
| Peak memory | 227956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054672213 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2054672213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/2.keymgr_sw_invalid_input.4043541051 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 44206140 ps |
| CPU time | 4.38 seconds |
| Started | Oct 09 10:11:37 AM UTC 24 |
| Finished | Oct 09 10:11:42 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043541051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.4043541051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/2.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/20.keymgr_alert_test.497219745 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 13078606 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 10:14:23 AM UTC 24 |
| Finished | Oct 09 10:14:25 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497219745 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.497219745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/20.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/20.keymgr_direct_to_disabled.3498316309 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 503085296 ps |
| CPU time | 10.7 seconds |
| Started | Oct 09 10:14:19 AM UTC 24 |
| Finished | Oct 09 10:14:31 AM UTC 24 |
| Peak memory | 223544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498316309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3498316309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/20.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/20.keymgr_hwsw_invalid_input.3745991781 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 108319293 ps |
| CPU time | 4.16 seconds |
| Started | Oct 09 10:14:20 AM UTC 24 |
| Finished | Oct 09 10:14:26 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745991781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3745991781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/20.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/20.keymgr_lc_disable.4184721442 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 749776480 ps |
| CPU time | 6.03 seconds |
| Started | Oct 09 10:14:19 AM UTC 24 |
| Finished | Oct 09 10:14:26 AM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184721442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.4184721442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/20.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/20.keymgr_random.845095149 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 448359145 ps |
| CPU time | 17.14 seconds |
| Started | Oct 09 10:14:18 AM UTC 24 |
| Finished | Oct 09 10:14:36 AM UTC 24 |
| Peak memory | 217656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845095149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.845095149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/20.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/20.keymgr_sideload.1640446492 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 116434341 ps |
| CPU time | 2.8 seconds |
| Started | Oct 09 10:14:16 AM UTC 24 |
| Finished | Oct 09 10:14:19 AM UTC 24 |
| Peak memory | 215620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640446492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1640446492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/20.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_aes.116867790 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 66655923 ps |
| CPU time | 4.24 seconds |
| Started | Oct 09 10:14:17 AM UTC 24 |
| Finished | Oct 09 10:14:22 AM UTC 24 |
| Peak memory | 217320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116867790 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.116867790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/20.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_kmac.103421526 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 156222036 ps |
| CPU time | 6.48 seconds |
| Started | Oct 09 10:14:17 AM UTC 24 |
| Finished | Oct 09 10:14:24 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103421526 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.103421526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/20.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_otbn.4137412016 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 534161103 ps |
| CPU time | 13.03 seconds |
| Started | Oct 09 10:14:18 AM UTC 24 |
| Finished | Oct 09 10:14:32 AM UTC 24 |
| Peak memory | 217320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137412016 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.4137412016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/20.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_protect.1948257992 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 248683336 ps |
| CPU time | 2.4 seconds |
| Started | Oct 09 10:14:21 AM UTC 24 |
| Finished | Oct 09 10:14:24 AM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948257992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1948257992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/20.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/20.keymgr_smoke.4072983681 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 214004241 ps |
| CPU time | 3.57 seconds |
| Started | Oct 09 10:14:14 AM UTC 24 |
| Finished | Oct 09 10:14:19 AM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072983681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.4072983681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/20.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/20.keymgr_sw_invalid_input.2309045092 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 161424835 ps |
| CPU time | 6.03 seconds |
| Started | Oct 09 10:14:20 AM UTC 24 |
| Finished | Oct 09 10:14:28 AM UTC 24 |
| Peak memory | 217464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309045092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2309045092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/20.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/20.keymgr_sync_async_fault_cross.1303898988 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 82404332 ps |
| CPU time | 3.04 seconds |
| Started | Oct 09 10:14:22 AM UTC 24 |
| Finished | Oct 09 10:14:26 AM UTC 24 |
| Peak memory | 219376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303898988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1303898988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/20.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/21.keymgr_alert_test.352074992 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 13442151 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 10:14:32 AM UTC 24 |
| Finished | Oct 09 10:14:34 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352074992 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.352074992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/21.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/21.keymgr_cfg_regwen.1827909401 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 221471156 ps |
| CPU time | 12.1 seconds |
| Started | Oct 09 10:14:27 AM UTC 24 |
| Finished | Oct 09 10:14:40 AM UTC 24 |
| Peak memory | 223732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827909401 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1827909401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/21.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/21.keymgr_custom_cm.2653403438 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 183225056 ps |
| CPU time | 3.19 seconds |
| Started | Oct 09 10:14:29 AM UTC 24 |
| Finished | Oct 09 10:14:33 AM UTC 24 |
| Peak memory | 223548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653403438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2653403438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/21.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/21.keymgr_direct_to_disabled.4048194870 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 33741126 ps |
| CPU time | 2.29 seconds |
| Started | Oct 09 10:14:27 AM UTC 24 |
| Finished | Oct 09 10:14:30 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048194870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.4048194870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/21.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/21.keymgr_hwsw_invalid_input.2538936264 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 126199650 ps |
| CPU time | 4.52 seconds |
| Started | Oct 09 10:14:28 AM UTC 24 |
| Finished | Oct 09 10:14:34 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538936264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2538936264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/21.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/21.keymgr_kmac_rsp_err.2203473950 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 108581596 ps |
| CPU time | 3.14 seconds |
| Started | Oct 09 10:14:28 AM UTC 24 |
| Finished | Oct 09 10:14:32 AM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203473950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2203473950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/21.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/21.keymgr_lc_disable.3974630816 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 358155520 ps |
| CPU time | 7.63 seconds |
| Started | Oct 09 10:14:28 AM UTC 24 |
| Finished | Oct 09 10:14:37 AM UTC 24 |
| Peak memory | 217424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974630816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3974630816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/21.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/21.keymgr_random.1154050804 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 140643102 ps |
| CPU time | 5.45 seconds |
| Started | Oct 09 10:14:27 AM UTC 24 |
| Finished | Oct 09 10:14:33 AM UTC 24 |
| Peak memory | 217596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154050804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1154050804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/21.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/21.keymgr_sideload.432701424 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 391453387 ps |
| CPU time | 5.06 seconds |
| Started | Oct 09 10:14:23 AM UTC 24 |
| Finished | Oct 09 10:14:29 AM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432701424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.432701424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/21.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_aes.1132275321 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 31221816 ps |
| CPU time | 2.34 seconds |
| Started | Oct 09 10:14:25 AM UTC 24 |
| Finished | Oct 09 10:14:29 AM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132275321 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1132275321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/21.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_kmac.1885076062 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 52224426 ps |
| CPU time | 3.89 seconds |
| Started | Oct 09 10:14:25 AM UTC 24 |
| Finished | Oct 09 10:14:30 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885076062 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1885076062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/21.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_otbn.2341985081 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 33494489 ps |
| CPU time | 2.77 seconds |
| Started | Oct 09 10:14:27 AM UTC 24 |
| Finished | Oct 09 10:14:30 AM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341985081 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2341985081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/21.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_protect.1139013986 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 165738511 ps |
| CPU time | 2.02 seconds |
| Started | Oct 09 10:14:29 AM UTC 24 |
| Finished | Oct 09 10:14:32 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139013986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1139013986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/21.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/21.keymgr_smoke.2707379942 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 357419754 ps |
| CPU time | 6.23 seconds |
| Started | Oct 09 10:14:23 AM UTC 24 |
| Finished | Oct 09 10:14:31 AM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707379942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2707379942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/21.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/21.keymgr_stress_all.680412600 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 6010238250 ps |
| CPU time | 169.52 seconds |
| Started | Oct 09 10:14:31 AM UTC 24 |
| Finished | Oct 09 10:17:23 AM UTC 24 |
| Peak memory | 227692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680412600 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.680412600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/21.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/21.keymgr_sw_invalid_input.1904143711 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 336413331 ps |
| CPU time | 8.71 seconds |
| Started | Oct 09 10:14:28 AM UTC 24 |
| Finished | Oct 09 10:14:38 AM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904143711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1904143711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/21.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/21.keymgr_sync_async_fault_cross.1923124515 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 1580485113 ps |
| CPU time | 23.07 seconds |
| Started | Oct 09 10:14:30 AM UTC 24 |
| Finished | Oct 09 10:14:55 AM UTC 24 |
| Peak memory | 219448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923124515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1923124515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/21.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/22.keymgr_alert_test.2942334269 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 30820243 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 10:14:38 AM UTC 24 |
| Finished | Oct 09 10:14:40 AM UTC 24 |
| Peak memory | 212824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942334269 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.2942334269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/22.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/22.keymgr_cfg_regwen.3386089188 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 40897980 ps |
| CPU time | 3.62 seconds |
| Started | Oct 09 10:14:33 AM UTC 24 |
| Finished | Oct 09 10:14:38 AM UTC 24 |
| Peak memory | 225588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386089188 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3386089188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/22.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/22.keymgr_direct_to_disabled.1326120629 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 60983129 ps |
| CPU time | 4 seconds |
| Started | Oct 09 10:14:33 AM UTC 24 |
| Finished | Oct 09 10:14:39 AM UTC 24 |
| Peak memory | 223544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326120629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1326120629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/22.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/22.keymgr_hwsw_invalid_input.1459632369 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 95429736 ps |
| CPU time | 5.64 seconds |
| Started | Oct 09 10:14:35 AM UTC 24 |
| Finished | Oct 09 10:14:41 AM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459632369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1459632369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/22.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/22.keymgr_kmac_rsp_err.2984386152 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 34950084 ps |
| CPU time | 2.89 seconds |
| Started | Oct 09 10:14:35 AM UTC 24 |
| Finished | Oct 09 10:14:39 AM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984386152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2984386152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/22.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/22.keymgr_lc_disable.3887069711 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 146403514 ps |
| CPU time | 4.79 seconds |
| Started | Oct 09 10:14:33 AM UTC 24 |
| Finished | Oct 09 10:14:39 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887069711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3887069711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/22.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/22.keymgr_random.1783188137 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 217474177 ps |
| CPU time | 7.91 seconds |
| Started | Oct 09 10:14:33 AM UTC 24 |
| Finished | Oct 09 10:14:42 AM UTC 24 |
| Peak memory | 227900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783188137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1783188137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/22.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/22.keymgr_sideload.2952802481 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 96279866 ps |
| CPU time | 4.4 seconds |
| Started | Oct 09 10:14:32 AM UTC 24 |
| Finished | Oct 09 10:14:37 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952802481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2952802481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/22.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_aes.4109587783 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 145890391 ps |
| CPU time | 4.88 seconds |
| Started | Oct 09 10:14:32 AM UTC 24 |
| Finished | Oct 09 10:14:38 AM UTC 24 |
| Peak memory | 217536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109587783 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.4109587783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/22.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_kmac.4053193533 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 218679496 ps |
| CPU time | 3.51 seconds |
| Started | Oct 09 10:14:32 AM UTC 24 |
| Finished | Oct 09 10:14:37 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053193533 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.4053193533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/22.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_otbn.1783132647 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 557152567 ps |
| CPU time | 7.94 seconds |
| Started | Oct 09 10:14:33 AM UTC 24 |
| Finished | Oct 09 10:14:42 AM UTC 24 |
| Peak memory | 215228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783132647 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1783132647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/22.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_protect.570339089 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 2989709228 ps |
| CPU time | 27.43 seconds |
| Started | Oct 09 10:14:37 AM UTC 24 |
| Finished | Oct 09 10:15:06 AM UTC 24 |
| Peak memory | 223536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570339089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.570339089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/22.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/22.keymgr_smoke.2873668289 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 163824813 ps |
| CPU time | 3.07 seconds |
| Started | Oct 09 10:14:32 AM UTC 24 |
| Finished | Oct 09 10:14:36 AM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873668289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2873668289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/22.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/22.keymgr_stress_all.2012318119 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 941572162 ps |
| CPU time | 16.56 seconds |
| Started | Oct 09 10:14:37 AM UTC 24 |
| Finished | Oct 09 10:14:55 AM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012318119 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2012318119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/22.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/22.keymgr_sw_invalid_input.1166043554 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 188497617 ps |
| CPU time | 5.08 seconds |
| Started | Oct 09 10:14:35 AM UTC 24 |
| Finished | Oct 09 10:14:41 AM UTC 24 |
| Peak memory | 223556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166043554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1166043554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/22.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/22.keymgr_sync_async_fault_cross.2712420888 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 38344613 ps |
| CPU time | 1.9 seconds |
| Started | Oct 09 10:14:37 AM UTC 24 |
| Finished | Oct 09 10:14:40 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712420888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2712420888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/22.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/23.keymgr_alert_test.970181515 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 35068101 ps |
| CPU time | 0.96 seconds |
| Started | Oct 09 10:14:44 AM UTC 24 |
| Finished | Oct 09 10:14:46 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970181515 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.970181515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/23.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/23.keymgr_cfg_regwen.4008389659 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 216746645 ps |
| CPU time | 7.38 seconds |
| Started | Oct 09 10:14:40 AM UTC 24 |
| Finished | Oct 09 10:14:48 AM UTC 24 |
| Peak memory | 225804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008389659 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.4008389659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/23.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/23.keymgr_custom_cm.3895375259 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 66689141 ps |
| CPU time | 3.39 seconds |
| Started | Oct 09 10:14:41 AM UTC 24 |
| Finished | Oct 09 10:14:46 AM UTC 24 |
| Peak memory | 230832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895375259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3895375259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/23.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/23.keymgr_direct_to_disabled.1957125765 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 32913703 ps |
| CPU time | 2.55 seconds |
| Started | Oct 09 10:14:41 AM UTC 24 |
| Finished | Oct 09 10:14:45 AM UTC 24 |
| Peak memory | 227944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957125765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1957125765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/23.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/23.keymgr_hwsw_invalid_input.3093012271 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 315012264 ps |
| CPU time | 5.45 seconds |
| Started | Oct 09 10:14:41 AM UTC 24 |
| Finished | Oct 09 10:14:48 AM UTC 24 |
| Peak memory | 230080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093012271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3093012271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/23.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/23.keymgr_kmac_rsp_err.3519492649 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 317867164 ps |
| CPU time | 2.68 seconds |
| Started | Oct 09 10:14:41 AM UTC 24 |
| Finished | Oct 09 10:14:45 AM UTC 24 |
| Peak memory | 223408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519492649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3519492649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/23.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/23.keymgr_lc_disable.189803853 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 50289095 ps |
| CPU time | 2.63 seconds |
| Started | Oct 09 10:14:41 AM UTC 24 |
| Finished | Oct 09 10:14:45 AM UTC 24 |
| Peak memory | 213172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189803853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.189803853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/23.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/23.keymgr_random.2694518295 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 86489676 ps |
| CPU time | 4.4 seconds |
| Started | Oct 09 10:14:40 AM UTC 24 |
| Finished | Oct 09 10:14:45 AM UTC 24 |
| Peak memory | 215612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694518295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2694518295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/23.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/23.keymgr_sideload.205026013 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 3826164887 ps |
| CPU time | 24.45 seconds |
| Started | Oct 09 10:14:38 AM UTC 24 |
| Finished | Oct 09 10:15:04 AM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205026013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.205026013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/23.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_aes.2009129435 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 6275630385 ps |
| CPU time | 43.73 seconds |
| Started | Oct 09 10:14:40 AM UTC 24 |
| Finished | Oct 09 10:15:25 AM UTC 24 |
| Peak memory | 217452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009129435 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2009129435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/23.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_kmac.3296177923 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 141682804 ps |
| CPU time | 3.28 seconds |
| Started | Oct 09 10:14:39 AM UTC 24 |
| Finished | Oct 09 10:14:43 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296177923 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3296177923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/23.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_otbn.3246509007 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 44821455 ps |
| CPU time | 3.22 seconds |
| Started | Oct 09 10:14:40 AM UTC 24 |
| Finished | Oct 09 10:14:44 AM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246509007 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3246509007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/23.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_protect.332545344 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 86526291 ps |
| CPU time | 2.2 seconds |
| Started | Oct 09 10:14:43 AM UTC 24 |
| Finished | Oct 09 10:14:46 AM UTC 24 |
| Peak memory | 217416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332545344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.332545344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/23.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/23.keymgr_smoke.2546660231 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 288452666 ps |
| CPU time | 3.54 seconds |
| Started | Oct 09 10:14:38 AM UTC 24 |
| Finished | Oct 09 10:14:43 AM UTC 24 |
| Peak memory | 215196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546660231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2546660231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/23.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all.4231469177 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 38048406995 ps |
| CPU time | 218.83 seconds |
| Started | Oct 09 10:14:43 AM UTC 24 |
| Finished | Oct 09 10:18:25 AM UTC 24 |
| Peak memory | 227960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231469177 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.4231469177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/23.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/23.keymgr_sw_invalid_input.2443303697 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1815648034 ps |
| CPU time | 23.09 seconds |
| Started | Oct 09 10:14:41 AM UTC 24 |
| Finished | Oct 09 10:15:06 AM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443303697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2443303697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/23.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/23.keymgr_sync_async_fault_cross.3187210559 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 49625745 ps |
| CPU time | 2.41 seconds |
| Started | Oct 09 10:14:43 AM UTC 24 |
| Finished | Oct 09 10:14:46 AM UTC 24 |
| Peak memory | 217668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187210559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3187210559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/23.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/24.keymgr_alert_test.332215487 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 78670714 ps |
| CPU time | 1.3 seconds |
| Started | Oct 09 10:14:50 AM UTC 24 |
| Finished | Oct 09 10:14:53 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332215487 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.332215487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/24.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/24.keymgr_custom_cm.730614849 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 238656491 ps |
| CPU time | 3.16 seconds |
| Started | Oct 09 10:14:47 AM UTC 24 |
| Finished | Oct 09 10:14:51 AM UTC 24 |
| Peak memory | 227904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730614849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.730614849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/24.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/24.keymgr_direct_to_disabled.480547872 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 64997273 ps |
| CPU time | 2.24 seconds |
| Started | Oct 09 10:14:47 AM UTC 24 |
| Finished | Oct 09 10:14:50 AM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480547872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.480547872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/24.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/24.keymgr_hwsw_invalid_input.1492684075 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 167338715 ps |
| CPU time | 6.39 seconds |
| Started | Oct 09 10:14:47 AM UTC 24 |
| Finished | Oct 09 10:14:54 AM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492684075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1492684075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/24.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/24.keymgr_kmac_rsp_err.3850707288 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 179855492 ps |
| CPU time | 6.55 seconds |
| Started | Oct 09 10:14:47 AM UTC 24 |
| Finished | Oct 09 10:14:55 AM UTC 24 |
| Peak memory | 231480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850707288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3850707288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/24.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/24.keymgr_lc_disable.953035377 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 104254909 ps |
| CPU time | 5.78 seconds |
| Started | Oct 09 10:14:47 AM UTC 24 |
| Finished | Oct 09 10:14:54 AM UTC 24 |
| Peak memory | 217596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953035377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.953035377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/24.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/24.keymgr_random.1628192884 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 168130679 ps |
| CPU time | 5.51 seconds |
| Started | Oct 09 10:14:45 AM UTC 24 |
| Finished | Oct 09 10:14:52 AM UTC 24 |
| Peak memory | 219380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628192884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1628192884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/24.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/24.keymgr_sideload.1370737576 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 783581797 ps |
| CPU time | 11.11 seconds |
| Started | Oct 09 10:14:44 AM UTC 24 |
| Finished | Oct 09 10:14:56 AM UTC 24 |
| Peak memory | 217464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370737576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1370737576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/24.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_aes.1741487632 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 105024776 ps |
| CPU time | 4.23 seconds |
| Started | Oct 09 10:14:45 AM UTC 24 |
| Finished | Oct 09 10:14:51 AM UTC 24 |
| Peak memory | 217464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741487632 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1741487632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/24.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_kmac.99139088 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 40231912 ps |
| CPU time | 2.78 seconds |
| Started | Oct 09 10:14:44 AM UTC 24 |
| Finished | Oct 09 10:14:48 AM UTC 24 |
| Peak memory | 215536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99139088 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.99139088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/24.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_otbn.549408871 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 278853324 ps |
| CPU time | 3.13 seconds |
| Started | Oct 09 10:14:45 AM UTC 24 |
| Finished | Oct 09 10:14:49 AM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549408871 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.549408871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/24.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_protect.3170248475 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 274525110 ps |
| CPU time | 4.59 seconds |
| Started | Oct 09 10:14:49 AM UTC 24 |
| Finished | Oct 09 10:14:55 AM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170248475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3170248475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/24.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/24.keymgr_smoke.877879260 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 85837742 ps |
| CPU time | 3.28 seconds |
| Started | Oct 09 10:14:44 AM UTC 24 |
| Finished | Oct 09 10:14:48 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877879260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.877879260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/24.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all.105483144 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 107348421 ps |
| CPU time | 5.83 seconds |
| Started | Oct 09 10:14:49 AM UTC 24 |
| Finished | Oct 09 10:14:56 AM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105483144 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.105483144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/24.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/24.keymgr_sw_invalid_input.1750718715 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 80518575 ps |
| CPU time | 4.24 seconds |
| Started | Oct 09 10:14:47 AM UTC 24 |
| Finished | Oct 09 10:14:52 AM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750718715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1750718715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/24.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/24.keymgr_sync_async_fault_cross.949851060 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 287484465 ps |
| CPU time | 4.33 seconds |
| Started | Oct 09 10:14:49 AM UTC 24 |
| Finished | Oct 09 10:14:54 AM UTC 24 |
| Peak memory | 219376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949851060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.949851060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/24.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/25.keymgr_alert_test.792886468 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 17267666 ps |
| CPU time | 0.96 seconds |
| Started | Oct 09 10:14:57 AM UTC 24 |
| Finished | Oct 09 10:14:59 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792886468 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.792886468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/25.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/25.keymgr_cfg_regwen.914881265 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 396638194 ps |
| CPU time | 2.89 seconds |
| Started | Oct 09 10:14:54 AM UTC 24 |
| Finished | Oct 09 10:14:58 AM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914881265 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.914881265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/25.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/25.keymgr_direct_to_disabled.1827277010 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 135198027 ps |
| CPU time | 6.84 seconds |
| Started | Oct 09 10:14:54 AM UTC 24 |
| Finished | Oct 09 10:15:02 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827277010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1827277010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/25.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/25.keymgr_hwsw_invalid_input.4263947674 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 51882993 ps |
| CPU time | 4.89 seconds |
| Started | Oct 09 10:14:55 AM UTC 24 |
| Finished | Oct 09 10:15:01 AM UTC 24 |
| Peak memory | 217288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263947674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.4263947674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/25.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/25.keymgr_kmac_rsp_err.1547236558 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 205134861 ps |
| CPU time | 4.02 seconds |
| Started | Oct 09 10:14:55 AM UTC 24 |
| Finished | Oct 09 10:15:01 AM UTC 24 |
| Peak memory | 223748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547236558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1547236558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/25.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/25.keymgr_lc_disable.2389714337 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 75730187 ps |
| CPU time | 3.46 seconds |
| Started | Oct 09 10:14:55 AM UTC 24 |
| Finished | Oct 09 10:15:00 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389714337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2389714337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/25.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/25.keymgr_random.2445778738 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 216875120 ps |
| CPU time | 5.61 seconds |
| Started | Oct 09 10:14:53 AM UTC 24 |
| Finished | Oct 09 10:15:00 AM UTC 24 |
| Peak memory | 217480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445778738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2445778738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/25.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/25.keymgr_sideload.2645623062 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 413237553 ps |
| CPU time | 4.53 seconds |
| Started | Oct 09 10:14:51 AM UTC 24 |
| Finished | Oct 09 10:14:57 AM UTC 24 |
| Peak memory | 215684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645623062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2645623062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/25.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_aes.950067071 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 728737829 ps |
| CPU time | 5.89 seconds |
| Started | Oct 09 10:14:53 AM UTC 24 |
| Finished | Oct 09 10:15:00 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950067071 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.950067071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/25.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_kmac.3008464817 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 70799450 ps |
| CPU time | 3.73 seconds |
| Started | Oct 09 10:14:52 AM UTC 24 |
| Finished | Oct 09 10:14:56 AM UTC 24 |
| Peak memory | 217612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008464817 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3008464817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/25.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_otbn.606307812 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 5188431714 ps |
| CPU time | 49.82 seconds |
| Started | Oct 09 10:14:53 AM UTC 24 |
| Finished | Oct 09 10:15:45 AM UTC 24 |
| Peak memory | 217460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606307812 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.606307812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/25.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_protect.3517007790 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 148890980 ps |
| CPU time | 4.09 seconds |
| Started | Oct 09 10:14:55 AM UTC 24 |
| Finished | Oct 09 10:15:01 AM UTC 24 |
| Peak memory | 223496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517007790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3517007790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/25.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/25.keymgr_smoke.3158347279 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 38465917 ps |
| CPU time | 3.23 seconds |
| Started | Oct 09 10:14:50 AM UTC 24 |
| Finished | Oct 09 10:14:55 AM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158347279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3158347279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/25.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all_with_rand_reset.1171593828 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1801624958 ps |
| CPU time | 7.52 seconds |
| Started | Oct 09 10:14:57 AM UTC 24 |
| Finished | Oct 09 10:15:05 AM UTC 24 |
| Peak memory | 231848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1171593828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymg r_stress_all_with_rand_reset.1171593828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/25.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/25.keymgr_sw_invalid_input.2028583014 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 470000443 ps |
| CPU time | 8.09 seconds |
| Started | Oct 09 10:14:55 AM UTC 24 |
| Finished | Oct 09 10:15:05 AM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028583014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2028583014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/25.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/25.keymgr_sync_async_fault_cross.1062377189 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 122555240 ps |
| CPU time | 2.2 seconds |
| Started | Oct 09 10:14:56 AM UTC 24 |
| Finished | Oct 09 10:14:59 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062377189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1062377189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/25.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/26.keymgr_alert_test.772883542 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 62834275 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 10:15:03 AM UTC 24 |
| Finished | Oct 09 10:15:06 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772883542 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.772883542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/26.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/26.keymgr_cfg_regwen.3970165344 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 142710615 ps |
| CPU time | 7.96 seconds |
| Started | Oct 09 10:15:00 AM UTC 24 |
| Finished | Oct 09 10:15:09 AM UTC 24 |
| Peak memory | 223536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970165344 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3970165344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/26.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/26.keymgr_direct_to_disabled.2455041384 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 2117383397 ps |
| CPU time | 11.75 seconds |
| Started | Oct 09 10:15:00 AM UTC 24 |
| Finished | Oct 09 10:15:13 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455041384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2455041384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/26.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/26.keymgr_hwsw_invalid_input.928550772 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 274939978 ps |
| CPU time | 3.78 seconds |
| Started | Oct 09 10:15:01 AM UTC 24 |
| Finished | Oct 09 10:15:06 AM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928550772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.928550772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/26.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/26.keymgr_kmac_rsp_err.2342709367 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 450724143 ps |
| CPU time | 7.99 seconds |
| Started | Oct 09 10:15:01 AM UTC 24 |
| Finished | Oct 09 10:15:10 AM UTC 24 |
| Peak memory | 223432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342709367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2342709367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/26.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/26.keymgr_lc_disable.459601311 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 594400724 ps |
| CPU time | 6.19 seconds |
| Started | Oct 09 10:15:01 AM UTC 24 |
| Finished | Oct 09 10:15:08 AM UTC 24 |
| Peak memory | 229692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459601311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.459601311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/26.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/26.keymgr_random.3003282313 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 193602757 ps |
| CPU time | 8.79 seconds |
| Started | Oct 09 10:14:58 AM UTC 24 |
| Finished | Oct 09 10:15:09 AM UTC 24 |
| Peak memory | 217480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003282313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3003282313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/26.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/26.keymgr_sideload.3023882244 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 62284168 ps |
| CPU time | 3.07 seconds |
| Started | Oct 09 10:14:57 AM UTC 24 |
| Finished | Oct 09 10:15:01 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023882244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3023882244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/26.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_aes.3534281573 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 213227992 ps |
| CPU time | 3.4 seconds |
| Started | Oct 09 10:14:58 AM UTC 24 |
| Finished | Oct 09 10:15:03 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534281573 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3534281573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/26.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_kmac.513707373 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1350976071 ps |
| CPU time | 33.23 seconds |
| Started | Oct 09 10:14:57 AM UTC 24 |
| Finished | Oct 09 10:15:32 AM UTC 24 |
| Peak memory | 217536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513707373 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.513707373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/26.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_otbn.3376913120 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 391868470 ps |
| CPU time | 7.27 seconds |
| Started | Oct 09 10:14:58 AM UTC 24 |
| Finished | Oct 09 10:15:07 AM UTC 24 |
| Peak memory | 217664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376913120 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3376913120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/26.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_protect.2792365938 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 41019843 ps |
| CPU time | 3.16 seconds |
| Started | Oct 09 10:15:02 AM UTC 24 |
| Finished | Oct 09 10:15:07 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792365938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2792365938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/26.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/26.keymgr_smoke.1252201586 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 118640568 ps |
| CPU time | 3.45 seconds |
| Started | Oct 09 10:14:57 AM UTC 24 |
| Finished | Oct 09 10:15:01 AM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252201586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1252201586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/26.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/26.keymgr_stress_all.2606188468 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1116778632 ps |
| CPU time | 11.37 seconds |
| Started | Oct 09 10:15:02 AM UTC 24 |
| Finished | Oct 09 10:15:15 AM UTC 24 |
| Peak memory | 227896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606188468 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2606188468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/26.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/26.keymgr_sw_invalid_input.1722496744 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 237324645 ps |
| CPU time | 7.34 seconds |
| Started | Oct 09 10:15:01 AM UTC 24 |
| Finished | Oct 09 10:15:10 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722496744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1722496744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/26.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/26.keymgr_sync_async_fault_cross.3149043769 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1068859995 ps |
| CPU time | 8.13 seconds |
| Started | Oct 09 10:15:02 AM UTC 24 |
| Finished | Oct 09 10:15:12 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149043769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3149043769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/26.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/27.keymgr_alert_test.2988275025 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 13781221 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 10:15:11 AM UTC 24 |
| Finished | Oct 09 10:15:13 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988275025 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2988275025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/27.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/27.keymgr_direct_to_disabled.12501448 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 380641563 ps |
| CPU time | 4.1 seconds |
| Started | Oct 09 10:15:07 AM UTC 24 |
| Finished | Oct 09 10:15:12 AM UTC 24 |
| Peak memory | 223620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12501448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.12501448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/27.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/27.keymgr_hwsw_invalid_input.2043168298 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 145798703 ps |
| CPU time | 6.85 seconds |
| Started | Oct 09 10:15:08 AM UTC 24 |
| Finished | Oct 09 10:15:16 AM UTC 24 |
| Peak memory | 231672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043168298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2043168298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/27.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/27.keymgr_kmac_rsp_err.2695726919 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 92260405 ps |
| CPU time | 3.72 seconds |
| Started | Oct 09 10:15:08 AM UTC 24 |
| Finished | Oct 09 10:15:13 AM UTC 24 |
| Peak memory | 230888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695726919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2695726919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/27.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/27.keymgr_lc_disable.2363675196 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 450433547 ps |
| CPU time | 3.33 seconds |
| Started | Oct 09 10:15:08 AM UTC 24 |
| Finished | Oct 09 10:15:13 AM UTC 24 |
| Peak memory | 223876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363675196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2363675196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/27.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/27.keymgr_random.1697680622 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 3255475279 ps |
| CPU time | 43.13 seconds |
| Started | Oct 09 10:15:07 AM UTC 24 |
| Finished | Oct 09 10:15:52 AM UTC 24 |
| Peak memory | 217468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697680622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1697680622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/27.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/27.keymgr_sideload.2058106217 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 122966673 ps |
| CPU time | 3.72 seconds |
| Started | Oct 09 10:15:05 AM UTC 24 |
| Finished | Oct 09 10:15:09 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058106217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2058106217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/27.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_aes.2715498490 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 951347801 ps |
| CPU time | 6.53 seconds |
| Started | Oct 09 10:15:07 AM UTC 24 |
| Finished | Oct 09 10:15:15 AM UTC 24 |
| Peak memory | 215304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715498490 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2715498490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/27.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_kmac.1097327261 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 162905327 ps |
| CPU time | 3.89 seconds |
| Started | Oct 09 10:15:06 AM UTC 24 |
| Finished | Oct 09 10:15:11 AM UTC 24 |
| Peak memory | 217728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097327261 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1097327261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/27.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_otbn.535433783 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 146654759 ps |
| CPU time | 2.85 seconds |
| Started | Oct 09 10:15:07 AM UTC 24 |
| Finished | Oct 09 10:15:11 AM UTC 24 |
| Peak memory | 215184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535433783 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.535433783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/27.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_protect.2495358002 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 36317544 ps |
| CPU time | 3.03 seconds |
| Started | Oct 09 10:15:10 AM UTC 24 |
| Finished | Oct 09 10:15:14 AM UTC 24 |
| Peak memory | 217320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495358002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2495358002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/27.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/27.keymgr_smoke.4024380667 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 39959468 ps |
| CPU time | 2.81 seconds |
| Started | Oct 09 10:15:03 AM UTC 24 |
| Finished | Oct 09 10:15:07 AM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024380667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.4024380667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/27.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/27.keymgr_stress_all.1503983541 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 473914803 ps |
| CPU time | 22.29 seconds |
| Started | Oct 09 10:15:10 AM UTC 24 |
| Finished | Oct 09 10:15:34 AM UTC 24 |
| Peak memory | 229920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503983541 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1503983541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/27.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/27.keymgr_stress_all_with_rand_reset.2009574214 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 1346244803 ps |
| CPU time | 18.92 seconds |
| Started | Oct 09 10:15:11 AM UTC 24 |
| Finished | Oct 09 10:15:31 AM UTC 24 |
| Peak memory | 230568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2009574214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymg r_stress_all_with_rand_reset.2009574214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/27.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/27.keymgr_sw_invalid_input.988596720 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 136346204 ps |
| CPU time | 6.65 seconds |
| Started | Oct 09 10:15:08 AM UTC 24 |
| Finished | Oct 09 10:15:16 AM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988596720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.988596720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/27.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/27.keymgr_sync_async_fault_cross.97003535 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 700440601 ps |
| CPU time | 4.8 seconds |
| Started | Oct 09 10:15:10 AM UTC 24 |
| Finished | Oct 09 10:15:16 AM UTC 24 |
| Peak memory | 219412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97003535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.97003535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/27.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/28.keymgr_alert_test.3895117803 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 24071815 ps |
| CPU time | 1.3 seconds |
| Started | Oct 09 10:15:18 AM UTC 24 |
| Finished | Oct 09 10:15:20 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895117803 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3895117803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/28.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/28.keymgr_cfg_regwen.2436252100 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 81378917 ps |
| CPU time | 4.81 seconds |
| Started | Oct 09 10:15:14 AM UTC 24 |
| Finished | Oct 09 10:15:20 AM UTC 24 |
| Peak memory | 223536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436252100 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2436252100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/28.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/28.keymgr_custom_cm.1964631529 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 264726736 ps |
| CPU time | 3.59 seconds |
| Started | Oct 09 10:15:15 AM UTC 24 |
| Finished | Oct 09 10:15:20 AM UTC 24 |
| Peak memory | 230732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964631529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1964631529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/28.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/28.keymgr_direct_to_disabled.1798764097 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 628463484 ps |
| CPU time | 9.82 seconds |
| Started | Oct 09 10:15:14 AM UTC 24 |
| Finished | Oct 09 10:15:25 AM UTC 24 |
| Peak memory | 223936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798764097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1798764097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/28.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/28.keymgr_kmac_rsp_err.4174395947 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 468652076 ps |
| CPU time | 7.34 seconds |
| Started | Oct 09 10:15:15 AM UTC 24 |
| Finished | Oct 09 10:15:24 AM UTC 24 |
| Peak memory | 223484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174395947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.4174395947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/28.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/28.keymgr_lc_disable.575075454 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 161624760 ps |
| CPU time | 6.57 seconds |
| Started | Oct 09 10:15:14 AM UTC 24 |
| Finished | Oct 09 10:15:22 AM UTC 24 |
| Peak memory | 227572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575075454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.575075454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/28.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/28.keymgr_random.2197538539 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 118657883 ps |
| CPU time | 5.72 seconds |
| Started | Oct 09 10:15:13 AM UTC 24 |
| Finished | Oct 09 10:15:19 AM UTC 24 |
| Peak memory | 223624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197538539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2197538539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/28.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/28.keymgr_sideload.1459117249 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 741344546 ps |
| CPU time | 18.36 seconds |
| Started | Oct 09 10:15:11 AM UTC 24 |
| Finished | Oct 09 10:15:31 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459117249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1459117249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/28.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_aes.3235674782 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 1452926895 ps |
| CPU time | 20.78 seconds |
| Started | Oct 09 10:15:12 AM UTC 24 |
| Finished | Oct 09 10:15:35 AM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235674782 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3235674782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/28.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_kmac.3479251657 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 51390716 ps |
| CPU time | 3.83 seconds |
| Started | Oct 09 10:15:12 AM UTC 24 |
| Finished | Oct 09 10:15:17 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479251657 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3479251657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/28.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_otbn.820661888 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 259231277 ps |
| CPU time | 3.6 seconds |
| Started | Oct 09 10:15:13 AM UTC 24 |
| Finished | Oct 09 10:15:17 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820661888 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.820661888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/28.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_protect.2935223558 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 100215280 ps |
| CPU time | 4.03 seconds |
| Started | Oct 09 10:15:16 AM UTC 24 |
| Finished | Oct 09 10:15:21 AM UTC 24 |
| Peak memory | 223608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935223558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2935223558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/28.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/28.keymgr_smoke.2034044037 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 322237427 ps |
| CPU time | 3.82 seconds |
| Started | Oct 09 10:15:11 AM UTC 24 |
| Finished | Oct 09 10:15:16 AM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034044037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2034044037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/28.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all_with_rand_reset.2383217558 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 1257064571 ps |
| CPU time | 11.94 seconds |
| Started | Oct 09 10:15:18 AM UTC 24 |
| Finished | Oct 09 10:15:31 AM UTC 24 |
| Peak memory | 227688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2383217558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymg r_stress_all_with_rand_reset.2383217558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/28.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/28.keymgr_sw_invalid_input.2154769825 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 243204186 ps |
| CPU time | 4.72 seconds |
| Started | Oct 09 10:15:14 AM UTC 24 |
| Finished | Oct 09 10:15:20 AM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154769825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2154769825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/28.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/28.keymgr_sync_async_fault_cross.512956118 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 397186506 ps |
| CPU time | 5.52 seconds |
| Started | Oct 09 10:15:16 AM UTC 24 |
| Finished | Oct 09 10:15:23 AM UTC 24 |
| Peak memory | 217472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512956118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.512956118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/28.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/29.keymgr_alert_test.3006544837 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 10015027 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:15:26 AM UTC 24 |
| Finished | Oct 09 10:15:28 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006544837 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3006544837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/29.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/29.keymgr_custom_cm.1024158801 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 226713418 ps |
| CPU time | 3.45 seconds |
| Started | Oct 09 10:15:24 AM UTC 24 |
| Finished | Oct 09 10:15:29 AM UTC 24 |
| Peak memory | 230224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024158801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1024158801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/29.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/29.keymgr_direct_to_disabled.507674124 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 447656446 ps |
| CPU time | 13.06 seconds |
| Started | Oct 09 10:15:21 AM UTC 24 |
| Finished | Oct 09 10:15:36 AM UTC 24 |
| Peak memory | 217468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507674124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.507674124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/29.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/29.keymgr_hwsw_invalid_input.3443760390 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 184569848 ps |
| CPU time | 7.12 seconds |
| Started | Oct 09 10:15:23 AM UTC 24 |
| Finished | Oct 09 10:15:31 AM UTC 24 |
| Peak memory | 223732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443760390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3443760390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/29.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/29.keymgr_kmac_rsp_err.848160116 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 43089913 ps |
| CPU time | 3.4 seconds |
| Started | Oct 09 10:15:24 AM UTC 24 |
| Finished | Oct 09 10:15:29 AM UTC 24 |
| Peak memory | 223680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848160116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.848160116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/29.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/29.keymgr_lc_disable.2292455819 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 80286297 ps |
| CPU time | 3.29 seconds |
| Started | Oct 09 10:15:22 AM UTC 24 |
| Finished | Oct 09 10:15:27 AM UTC 24 |
| Peak memory | 231608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292455819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2292455819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/29.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/29.keymgr_random.3121168112 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 68975397 ps |
| CPU time | 4.23 seconds |
| Started | Oct 09 10:15:21 AM UTC 24 |
| Finished | Oct 09 10:15:27 AM UTC 24 |
| Peak memory | 217672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121168112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3121168112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/29.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/29.keymgr_sideload.1435290538 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 273348036 ps |
| CPU time | 4.17 seconds |
| Started | Oct 09 10:15:19 AM UTC 24 |
| Finished | Oct 09 10:15:24 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435290538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1435290538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/29.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_aes.399568410 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 106343129 ps |
| CPU time | 3.64 seconds |
| Started | Oct 09 10:15:20 AM UTC 24 |
| Finished | Oct 09 10:15:25 AM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399568410 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.399568410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/29.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_kmac.3075874679 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 70212873 ps |
| CPU time | 2.4 seconds |
| Started | Oct 09 10:15:19 AM UTC 24 |
| Finished | Oct 09 10:15:23 AM UTC 24 |
| Peak memory | 215616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075874679 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3075874679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/29.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_otbn.3004328985 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 235717778 ps |
| CPU time | 4.07 seconds |
| Started | Oct 09 10:15:21 AM UTC 24 |
| Finished | Oct 09 10:15:27 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004328985 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3004328985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/29.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_protect.3049065292 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 80005018 ps |
| CPU time | 4.52 seconds |
| Started | Oct 09 10:15:25 AM UTC 24 |
| Finished | Oct 09 10:15:31 AM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049065292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3049065292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/29.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/29.keymgr_smoke.3726812689 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 147749063 ps |
| CPU time | 5.55 seconds |
| Started | Oct 09 10:15:18 AM UTC 24 |
| Finished | Oct 09 10:15:25 AM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726812689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3726812689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/29.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all.698066971 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 3645065180 ps |
| CPU time | 41.42 seconds |
| Started | Oct 09 10:15:25 AM UTC 24 |
| Finished | Oct 09 10:16:08 AM UTC 24 |
| Peak memory | 225580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698066971 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.698066971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/29.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all_with_rand_reset.11486666 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 4923486166 ps |
| CPU time | 27.84 seconds |
| Started | Oct 09 10:15:25 AM UTC 24 |
| Finished | Oct 09 10:15:55 AM UTC 24 |
| Peak memory | 231756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=11486666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_ stress_all_with_rand_reset.11486666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/29.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/29.keymgr_sw_invalid_input.3035559820 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 30842386070 ps |
| CPU time | 77.69 seconds |
| Started | Oct 09 10:15:23 AM UTC 24 |
| Finished | Oct 09 10:16:42 AM UTC 24 |
| Peak memory | 223600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035559820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3035559820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/29.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/29.keymgr_sync_async_fault_cross.905290175 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 655708207 ps |
| CPU time | 15.45 seconds |
| Started | Oct 09 10:15:25 AM UTC 24 |
| Finished | Oct 09 10:15:42 AM UTC 24 |
| Peak memory | 217300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905290175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.905290175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/29.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/3.keymgr_alert_test.184882765 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 47096439 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 10:11:51 AM UTC 24 |
| Finished | Oct 09 10:11:54 AM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184882765 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.184882765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/3.keymgr_custom_cm.216071575 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 166504474 ps |
| CPU time | 4 seconds |
| Started | Oct 09 10:11:49 AM UTC 24 |
| Finished | Oct 09 10:11:54 AM UTC 24 |
| Peak memory | 229772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216071575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.216071575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/3.keymgr_direct_to_disabled.1264966752 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 170772853 ps |
| CPU time | 2.28 seconds |
| Started | Oct 09 10:11:46 AM UTC 24 |
| Finished | Oct 09 10:11:50 AM UTC 24 |
| Peak memory | 217540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264966752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1264966752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/3.keymgr_hwsw_invalid_input.2727150885 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 123422990 ps |
| CPU time | 3.24 seconds |
| Started | Oct 09 10:11:48 AM UTC 24 |
| Finished | Oct 09 10:11:52 AM UTC 24 |
| Peak memory | 231516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727150885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2727150885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/3.keymgr_kmac_rsp_err.1395284043 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 181940244 ps |
| CPU time | 6.09 seconds |
| Started | Oct 09 10:11:48 AM UTC 24 |
| Finished | Oct 09 10:11:55 AM UTC 24 |
| Peak memory | 230840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395284043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1395284043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/3.keymgr_lc_disable.127100419 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 40723136 ps |
| CPU time | 3.35 seconds |
| Started | Oct 09 10:11:46 AM UTC 24 |
| Finished | Oct 09 10:11:51 AM UTC 24 |
| Peak memory | 225664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127100419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.127100419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/3.keymgr_random.1155098601 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 160110052 ps |
| CPU time | 3.83 seconds |
| Started | Oct 09 10:11:45 AM UTC 24 |
| Finished | Oct 09 10:11:50 AM UTC 24 |
| Peak memory | 223732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155098601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1155098601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/3.keymgr_sec_cm.1797142634 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 656610764 ps |
| CPU time | 7.04 seconds |
| Started | Oct 09 10:11:51 AM UTC 24 |
| Finished | Oct 09 10:11:59 AM UTC 24 |
| Peak memory | 261592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797142634 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1797142634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/3.keymgr_sideload.394126750 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 757503186 ps |
| CPU time | 6.74 seconds |
| Started | Oct 09 10:11:44 AM UTC 24 |
| Finished | Oct 09 10:11:52 AM UTC 24 |
| Peak memory | 215268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394126750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.394126750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_kmac.4045757657 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 36748548 ps |
| CPU time | 2.28 seconds |
| Started | Oct 09 10:11:44 AM UTC 24 |
| Finished | Oct 09 10:11:47 AM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045757657 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.4045757657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_otbn.2204666288 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 328879235 ps |
| CPU time | 3.9 seconds |
| Started | Oct 09 10:11:45 AM UTC 24 |
| Finished | Oct 09 10:11:50 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204666288 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2204666288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_protect.3890081526 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 63355368 ps |
| CPU time | 2.14 seconds |
| Started | Oct 09 10:11:49 AM UTC 24 |
| Finished | Oct 09 10:11:52 AM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890081526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3890081526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/3.keymgr_smoke.2031431493 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 236171421 ps |
| CPU time | 4.26 seconds |
| Started | Oct 09 10:11:44 AM UTC 24 |
| Finished | Oct 09 10:11:49 AM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031431493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2031431493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/3.keymgr_stress_all_with_rand_reset.1185393891 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 94538902 ps |
| CPU time | 7.27 seconds |
| Started | Oct 09 10:11:50 AM UTC 24 |
| Finished | Oct 09 10:11:59 AM UTC 24 |
| Peak memory | 231736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1185393891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr _stress_all_with_rand_reset.1185393891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/3.keymgr_sw_invalid_input.369429524 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 179034217 ps |
| CPU time | 4.63 seconds |
| Started | Oct 09 10:11:46 AM UTC 24 |
| Finished | Oct 09 10:11:52 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369429524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.369429524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/3.keymgr_sync_async_fault_cross.4261529135 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 56120226 ps |
| CPU time | 3.66 seconds |
| Started | Oct 09 10:11:50 AM UTC 24 |
| Finished | Oct 09 10:11:55 AM UTC 24 |
| Peak memory | 217672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261529135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.4261529135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/3.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/30.keymgr_alert_test.2997706997 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 40475963 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:15:33 AM UTC 24 |
| Finished | Oct 09 10:15:35 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997706997 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2997706997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/30.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/30.keymgr_cfg_regwen.3865747139 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 874577823 ps |
| CPU time | 48.83 seconds |
| Started | Oct 09 10:15:30 AM UTC 24 |
| Finished | Oct 09 10:16:20 AM UTC 24 |
| Peak memory | 231608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865747139 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3865747139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/30.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/30.keymgr_custom_cm.3504190037 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 670088890 ps |
| CPU time | 5.93 seconds |
| Started | Oct 09 10:15:33 AM UTC 24 |
| Finished | Oct 09 10:15:40 AM UTC 24 |
| Peak memory | 230460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504190037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3504190037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/30.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/30.keymgr_direct_to_disabled.3983331090 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 27603554 ps |
| CPU time | 2.86 seconds |
| Started | Oct 09 10:15:30 AM UTC 24 |
| Finished | Oct 09 10:15:34 AM UTC 24 |
| Peak memory | 227636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983331090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3983331090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/30.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/30.keymgr_hwsw_invalid_input.1436189513 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 151436116 ps |
| CPU time | 2.44 seconds |
| Started | Oct 09 10:15:32 AM UTC 24 |
| Finished | Oct 09 10:15:36 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436189513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1436189513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/30.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/30.keymgr_kmac_rsp_err.1039531706 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 62994438 ps |
| CPU time | 4.45 seconds |
| Started | Oct 09 10:15:32 AM UTC 24 |
| Finished | Oct 09 10:15:38 AM UTC 24 |
| Peak memory | 231480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039531706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1039531706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/30.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/30.keymgr_lc_disable.376800345 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 338698569 ps |
| CPU time | 4.81 seconds |
| Started | Oct 09 10:15:31 AM UTC 24 |
| Finished | Oct 09 10:15:37 AM UTC 24 |
| Peak memory | 229764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376800345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.376800345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/30.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/30.keymgr_random.3823846010 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 165106272 ps |
| CPU time | 6.49 seconds |
| Started | Oct 09 10:15:30 AM UTC 24 |
| Finished | Oct 09 10:15:37 AM UTC 24 |
| Peak memory | 223548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823846010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3823846010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/30.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/30.keymgr_sideload.2194324462 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 171002960 ps |
| CPU time | 3.72 seconds |
| Started | Oct 09 10:15:26 AM UTC 24 |
| Finished | Oct 09 10:15:31 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194324462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2194324462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/30.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_aes.3243427481 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 95079356 ps |
| CPU time | 2.83 seconds |
| Started | Oct 09 10:15:28 AM UTC 24 |
| Finished | Oct 09 10:15:31 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243427481 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3243427481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/30.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_kmac.2609136965 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 1920714612 ps |
| CPU time | 26.82 seconds |
| Started | Oct 09 10:15:28 AM UTC 24 |
| Finished | Oct 09 10:15:56 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609136965 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2609136965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/30.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_otbn.1232460582 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 44914802 ps |
| CPU time | 2.82 seconds |
| Started | Oct 09 10:15:28 AM UTC 24 |
| Finished | Oct 09 10:15:32 AM UTC 24 |
| Peak memory | 215616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232460582 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1232460582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/30.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/30.keymgr_smoke.2259573974 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 572691100 ps |
| CPU time | 5.79 seconds |
| Started | Oct 09 10:15:26 AM UTC 24 |
| Finished | Oct 09 10:15:33 AM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259573974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2259573974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/30.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all.2730453345 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 4356018432 ps |
| CPU time | 30.71 seconds |
| Started | Oct 09 10:15:33 AM UTC 24 |
| Finished | Oct 09 10:16:05 AM UTC 24 |
| Peak memory | 231740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730453345 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2730453345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/30.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all_with_rand_reset.2663057626 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2471966062 ps |
| CPU time | 19.44 seconds |
| Started | Oct 09 10:15:33 AM UTC 24 |
| Finished | Oct 09 10:15:54 AM UTC 24 |
| Peak memory | 231988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2663057626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymg r_stress_all_with_rand_reset.2663057626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/30.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/30.keymgr_sw_invalid_input.4107155431 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 91380978 ps |
| CPU time | 4.56 seconds |
| Started | Oct 09 10:15:31 AM UTC 24 |
| Finished | Oct 09 10:15:37 AM UTC 24 |
| Peak memory | 215268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107155431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.4107155431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/30.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/30.keymgr_sync_async_fault_cross.3771646688 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 335082878 ps |
| CPU time | 4.2 seconds |
| Started | Oct 09 10:15:33 AM UTC 24 |
| Finished | Oct 09 10:15:38 AM UTC 24 |
| Peak memory | 219376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771646688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3771646688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/30.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/31.keymgr_alert_test.399956195 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 9949097 ps |
| CPU time | 1.34 seconds |
| Started | Oct 09 10:15:41 AM UTC 24 |
| Finished | Oct 09 10:15:44 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399956195 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.399956195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/31.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/31.keymgr_cfg_regwen.3349648957 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 48587731 ps |
| CPU time | 3.38 seconds |
| Started | Oct 09 10:15:37 AM UTC 24 |
| Finished | Oct 09 10:15:41 AM UTC 24 |
| Peak memory | 225540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349648957 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3349648957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/31.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/31.keymgr_custom_cm.4131048167 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 935025354 ps |
| CPU time | 12.07 seconds |
| Started | Oct 09 10:15:39 AM UTC 24 |
| Finished | Oct 09 10:15:52 AM UTC 24 |
| Peak memory | 229928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131048167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.4131048167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/31.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/31.keymgr_direct_to_disabled.3097859295 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 28395082 ps |
| CPU time | 2.38 seconds |
| Started | Oct 09 10:15:38 AM UTC 24 |
| Finished | Oct 09 10:15:41 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097859295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3097859295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/31.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/31.keymgr_hwsw_invalid_input.875775412 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 619968854 ps |
| CPU time | 6.92 seconds |
| Started | Oct 09 10:15:39 AM UTC 24 |
| Finished | Oct 09 10:15:47 AM UTC 24 |
| Peak memory | 227560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875775412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.875775412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/31.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/31.keymgr_kmac_rsp_err.2347813085 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 58411174 ps |
| CPU time | 4.29 seconds |
| Started | Oct 09 10:15:39 AM UTC 24 |
| Finished | Oct 09 10:15:44 AM UTC 24 |
| Peak memory | 231628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347813085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2347813085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/31.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/31.keymgr_lc_disable.669203018 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 88663092 ps |
| CPU time | 3.51 seconds |
| Started | Oct 09 10:15:38 AM UTC 24 |
| Finished | Oct 09 10:15:42 AM UTC 24 |
| Peak memory | 227836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669203018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.669203018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/31.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/31.keymgr_random.2106144590 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 855327345 ps |
| CPU time | 10.5 seconds |
| Started | Oct 09 10:15:36 AM UTC 24 |
| Finished | Oct 09 10:15:48 AM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106144590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2106144590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/31.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/31.keymgr_sideload.1920702673 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 89077947 ps |
| CPU time | 2.44 seconds |
| Started | Oct 09 10:15:34 AM UTC 24 |
| Finished | Oct 09 10:15:38 AM UTC 24 |
| Peak memory | 217732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920702673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1920702673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/31.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_aes.3750056792 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 186098602 ps |
| CPU time | 2.33 seconds |
| Started | Oct 09 10:15:35 AM UTC 24 |
| Finished | Oct 09 10:15:39 AM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750056792 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3750056792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/31.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_kmac.4100768957 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 555728951 ps |
| CPU time | 23.31 seconds |
| Started | Oct 09 10:15:35 AM UTC 24 |
| Finished | Oct 09 10:16:00 AM UTC 24 |
| Peak memory | 217320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100768957 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.4100768957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/31.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_otbn.1466324816 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 80076356 ps |
| CPU time | 2.92 seconds |
| Started | Oct 09 10:15:36 AM UTC 24 |
| Finished | Oct 09 10:15:40 AM UTC 24 |
| Peak memory | 217664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466324816 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1466324816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/31.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_protect.16603826 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 110198867 ps |
| CPU time | 2.63 seconds |
| Started | Oct 09 10:15:39 AM UTC 24 |
| Finished | Oct 09 10:15:43 AM UTC 24 |
| Peak memory | 229612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16603826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.16603826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/31.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/31.keymgr_smoke.2156672266 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 105856776 ps |
| CPU time | 2.12 seconds |
| Started | Oct 09 10:15:34 AM UTC 24 |
| Finished | Oct 09 10:15:37 AM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156672266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2156672266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/31.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/31.keymgr_stress_all.3270968297 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 3113703828 ps |
| CPU time | 33.32 seconds |
| Started | Oct 09 10:15:40 AM UTC 24 |
| Finished | Oct 09 10:16:15 AM UTC 24 |
| Peak memory | 231684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270968297 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3270968297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/31.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/31.keymgr_stress_all_with_rand_reset.2913481829 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 263622333 ps |
| CPU time | 18.46 seconds |
| Started | Oct 09 10:15:40 AM UTC 24 |
| Finished | Oct 09 10:16:00 AM UTC 24 |
| Peak memory | 231744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2913481829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymg r_stress_all_with_rand_reset.2913481829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/31.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/31.keymgr_sw_invalid_input.3772792791 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 320224434 ps |
| CPU time | 3.58 seconds |
| Started | Oct 09 10:15:39 AM UTC 24 |
| Finished | Oct 09 10:15:44 AM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772792791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3772792791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/31.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/31.keymgr_sync_async_fault_cross.2083416461 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 33600549 ps |
| CPU time | 1.63 seconds |
| Started | Oct 09 10:15:39 AM UTC 24 |
| Finished | Oct 09 10:15:42 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083416461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2083416461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/31.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/32.keymgr_alert_test.2458108084 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 47600334 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 10:15:51 AM UTC 24 |
| Finished | Oct 09 10:15:53 AM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458108084 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2458108084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/32.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/32.keymgr_cfg_regwen.1108018816 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 85247865 ps |
| CPU time | 3.53 seconds |
| Started | Oct 09 10:15:45 AM UTC 24 |
| Finished | Oct 09 10:15:50 AM UTC 24 |
| Peak memory | 223732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108018816 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1108018816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/32.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/32.keymgr_custom_cm.1054351893 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 43110744 ps |
| CPU time | 3.21 seconds |
| Started | Oct 09 10:15:49 AM UTC 24 |
| Finished | Oct 09 10:15:53 AM UTC 24 |
| Peak memory | 230020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054351893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1054351893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/32.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/32.keymgr_direct_to_disabled.1163201932 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 78645297 ps |
| CPU time | 3.18 seconds |
| Started | Oct 09 10:15:45 AM UTC 24 |
| Finished | Oct 09 10:15:49 AM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163201932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1163201932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/32.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/32.keymgr_hwsw_invalid_input.2461640498 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 355755211 ps |
| CPU time | 5.39 seconds |
| Started | Oct 09 10:15:46 AM UTC 24 |
| Finished | Oct 09 10:15:53 AM UTC 24 |
| Peak memory | 229684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461640498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2461640498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/32.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/32.keymgr_kmac_rsp_err.187428374 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 145319080 ps |
| CPU time | 4.16 seconds |
| Started | Oct 09 10:15:48 AM UTC 24 |
| Finished | Oct 09 10:15:54 AM UTC 24 |
| Peak memory | 225464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187428374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.187428374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/32.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/32.keymgr_lc_disable.3093296532 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 108376296 ps |
| CPU time | 4.71 seconds |
| Started | Oct 09 10:15:45 AM UTC 24 |
| Finished | Oct 09 10:15:51 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093296532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3093296532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/32.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/32.keymgr_random.1260974132 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 3403227926 ps |
| CPU time | 9.62 seconds |
| Started | Oct 09 10:15:44 AM UTC 24 |
| Finished | Oct 09 10:15:55 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260974132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1260974132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/32.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/32.keymgr_sideload.2194927178 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 136218605 ps |
| CPU time | 4.07 seconds |
| Started | Oct 09 10:15:43 AM UTC 24 |
| Finished | Oct 09 10:15:48 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194927178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2194927178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/32.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_aes.2775668237 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 148244541 ps |
| CPU time | 4.38 seconds |
| Started | Oct 09 10:15:43 AM UTC 24 |
| Finished | Oct 09 10:15:48 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775668237 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2775668237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/32.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_kmac.409959590 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 692295324 ps |
| CPU time | 7.4 seconds |
| Started | Oct 09 10:15:43 AM UTC 24 |
| Finished | Oct 09 10:15:51 AM UTC 24 |
| Peak memory | 217464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409959590 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.409959590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/32.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_otbn.1972816947 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 1013337472 ps |
| CPU time | 3.07 seconds |
| Started | Oct 09 10:15:44 AM UTC 24 |
| Finished | Oct 09 10:15:48 AM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972816947 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1972816947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/32.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_protect.2447495206 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 72459089 ps |
| CPU time | 4.27 seconds |
| Started | Oct 09 10:15:49 AM UTC 24 |
| Finished | Oct 09 10:15:54 AM UTC 24 |
| Peak memory | 227636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447495206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2447495206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/32.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/32.keymgr_smoke.630896408 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 55177979 ps |
| CPU time | 3.16 seconds |
| Started | Oct 09 10:15:42 AM UTC 24 |
| Finished | Oct 09 10:15:46 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630896408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.630896408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/32.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/32.keymgr_sw_invalid_input.1458356584 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 292730046 ps |
| CPU time | 8.06 seconds |
| Started | Oct 09 10:15:45 AM UTC 24 |
| Finished | Oct 09 10:15:54 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458356584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1458356584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/32.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/32.keymgr_sync_async_fault_cross.4066320766 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 48995855 ps |
| CPU time | 3.27 seconds |
| Started | Oct 09 10:15:50 AM UTC 24 |
| Finished | Oct 09 10:15:54 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066320766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.4066320766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/32.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/33.keymgr_alert_test.3055138292 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 166679886 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 10:15:59 AM UTC 24 |
| Finished | Oct 09 10:16:01 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055138292 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3055138292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/33.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/33.keymgr_cfg_regwen.3212065089 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 622057730 ps |
| CPU time | 7.51 seconds |
| Started | Oct 09 10:15:55 AM UTC 24 |
| Finished | Oct 09 10:16:04 AM UTC 24 |
| Peak memory | 231676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212065089 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3212065089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/33.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/33.keymgr_custom_cm.1776152877 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 144025309 ps |
| CPU time | 3.79 seconds |
| Started | Oct 09 10:15:56 AM UTC 24 |
| Finished | Oct 09 10:16:01 AM UTC 24 |
| Peak memory | 231924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776152877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1776152877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/33.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/33.keymgr_direct_to_disabled.378859827 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 260544091 ps |
| CPU time | 3.4 seconds |
| Started | Oct 09 10:15:55 AM UTC 24 |
| Finished | Oct 09 10:15:59 AM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378859827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.378859827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/33.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/33.keymgr_kmac_rsp_err.101671746 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 107623733 ps |
| CPU time | 4.05 seconds |
| Started | Oct 09 10:15:55 AM UTC 24 |
| Finished | Oct 09 10:16:00 AM UTC 24 |
| Peak memory | 223680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101671746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.101671746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/33.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/33.keymgr_lc_disable.1487985912 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 449313946 ps |
| CPU time | 4.57 seconds |
| Started | Oct 09 10:15:55 AM UTC 24 |
| Finished | Oct 09 10:16:01 AM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487985912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1487985912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/33.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/33.keymgr_random.3318681936 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 205381126 ps |
| CPU time | 6.63 seconds |
| Started | Oct 09 10:15:55 AM UTC 24 |
| Finished | Oct 09 10:16:03 AM UTC 24 |
| Peak memory | 227832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318681936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3318681936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/33.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/33.keymgr_sideload.3651973852 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 45009838 ps |
| CPU time | 3.61 seconds |
| Started | Oct 09 10:15:52 AM UTC 24 |
| Finished | Oct 09 10:15:57 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651973852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3651973852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/33.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_aes.2146491699 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 44832210 ps |
| CPU time | 3.42 seconds |
| Started | Oct 09 10:15:53 AM UTC 24 |
| Finished | Oct 09 10:15:58 AM UTC 24 |
| Peak memory | 215356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146491699 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2146491699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/33.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_kmac.2060903796 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 59145707 ps |
| CPU time | 2.95 seconds |
| Started | Oct 09 10:15:53 AM UTC 24 |
| Finished | Oct 09 10:15:57 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060903796 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2060903796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/33.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_otbn.560042693 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 63740372 ps |
| CPU time | 3.12 seconds |
| Started | Oct 09 10:15:53 AM UTC 24 |
| Finished | Oct 09 10:15:58 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560042693 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.560042693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/33.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_protect.284291193 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 101884668 ps |
| CPU time | 4.48 seconds |
| Started | Oct 09 10:15:56 AM UTC 24 |
| Finished | Oct 09 10:16:02 AM UTC 24 |
| Peak memory | 227568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284291193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.284291193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/33.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/33.keymgr_smoke.276155158 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 138774834 ps |
| CPU time | 4.06 seconds |
| Started | Oct 09 10:15:52 AM UTC 24 |
| Finished | Oct 09 10:15:57 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276155158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.276155158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/33.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all_with_rand_reset.2804854888 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 402943819 ps |
| CPU time | 13.47 seconds |
| Started | Oct 09 10:15:58 AM UTC 24 |
| Finished | Oct 09 10:16:12 AM UTC 24 |
| Peak memory | 231736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2804854888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymg r_stress_all_with_rand_reset.2804854888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/33.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/33.keymgr_sw_invalid_input.3957319470 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 1014269803 ps |
| CPU time | 24.73 seconds |
| Started | Oct 09 10:15:55 AM UTC 24 |
| Finished | Oct 09 10:16:21 AM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957319470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3957319470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/33.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/33.keymgr_sync_async_fault_cross.3296746221 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 351950994 ps |
| CPU time | 6.04 seconds |
| Started | Oct 09 10:15:56 AM UTC 24 |
| Finished | Oct 09 10:16:04 AM UTC 24 |
| Peak memory | 217732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296746221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3296746221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/33.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/34.keymgr_alert_test.2297459792 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 28055366 ps |
| CPU time | 0.95 seconds |
| Started | Oct 09 10:16:04 AM UTC 24 |
| Finished | Oct 09 10:16:06 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297459792 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2297459792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/34.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/34.keymgr_custom_cm.1206401682 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 58734384 ps |
| CPU time | 3.03 seconds |
| Started | Oct 09 10:16:03 AM UTC 24 |
| Finished | Oct 09 10:16:07 AM UTC 24 |
| Peak memory | 217404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206401682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1206401682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/34.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/34.keymgr_direct_to_disabled.859213718 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 153023870 ps |
| CPU time | 3.15 seconds |
| Started | Oct 09 10:16:01 AM UTC 24 |
| Finished | Oct 09 10:16:06 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859213718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.859213718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/34.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/34.keymgr_hwsw_invalid_input.412204511 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 93795116 ps |
| CPU time | 3.94 seconds |
| Started | Oct 09 10:16:03 AM UTC 24 |
| Finished | Oct 09 10:16:08 AM UTC 24 |
| Peak memory | 223744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412204511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.412204511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/34.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/34.keymgr_kmac_rsp_err.4292729575 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 182322552 ps |
| CPU time | 4.27 seconds |
| Started | Oct 09 10:16:03 AM UTC 24 |
| Finished | Oct 09 10:16:08 AM UTC 24 |
| Peak memory | 223676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292729575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.4292729575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/34.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/34.keymgr_random.2894780439 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 361292860 ps |
| CPU time | 6.01 seconds |
| Started | Oct 09 10:16:01 AM UTC 24 |
| Finished | Oct 09 10:16:08 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894780439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2894780439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/34.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/34.keymgr_sideload.2603236253 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 106927471 ps |
| CPU time | 3.71 seconds |
| Started | Oct 09 10:15:59 AM UTC 24 |
| Finished | Oct 09 10:16:04 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603236253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2603236253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/34.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_aes.258427977 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 9391612140 ps |
| CPU time | 40.95 seconds |
| Started | Oct 09 10:16:00 AM UTC 24 |
| Finished | Oct 09 10:16:42 AM UTC 24 |
| Peak memory | 217496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258427977 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.258427977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/34.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_kmac.4275363143 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 742155922 ps |
| CPU time | 4.17 seconds |
| Started | Oct 09 10:15:59 AM UTC 24 |
| Finished | Oct 09 10:16:04 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275363143 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.4275363143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/34.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_otbn.2840549460 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 50147290 ps |
| CPU time | 3.41 seconds |
| Started | Oct 09 10:16:01 AM UTC 24 |
| Finished | Oct 09 10:16:06 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840549460 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2840549460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/34.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_protect.1511908103 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 79586919 ps |
| CPU time | 2.34 seconds |
| Started | Oct 09 10:16:04 AM UTC 24 |
| Finished | Oct 09 10:16:07 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511908103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1511908103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/34.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/34.keymgr_smoke.3092765557 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 189657271 ps |
| CPU time | 3.17 seconds |
| Started | Oct 09 10:15:59 AM UTC 24 |
| Finished | Oct 09 10:16:03 AM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092765557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3092765557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/34.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all.3569362337 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 1683100732 ps |
| CPU time | 22.69 seconds |
| Started | Oct 09 10:16:04 AM UTC 24 |
| Finished | Oct 09 10:16:28 AM UTC 24 |
| Peak memory | 231756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569362337 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3569362337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/34.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all_with_rand_reset.1877282911 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 173704518 ps |
| CPU time | 7.13 seconds |
| Started | Oct 09 10:16:04 AM UTC 24 |
| Finished | Oct 09 10:16:12 AM UTC 24 |
| Peak memory | 231708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1877282911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymg r_stress_all_with_rand_reset.1877282911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/34.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/34.keymgr_sw_invalid_input.566787912 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 788751801 ps |
| CPU time | 5.23 seconds |
| Started | Oct 09 10:16:01 AM UTC 24 |
| Finished | Oct 09 10:16:08 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566787912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.566787912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/34.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/34.keymgr_sync_async_fault_cross.1625213218 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 67502809 ps |
| CPU time | 3.2 seconds |
| Started | Oct 09 10:16:04 AM UTC 24 |
| Finished | Oct 09 10:16:08 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625213218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1625213218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/34.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/35.keymgr_alert_test.482560768 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 11170140 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 10:16:12 AM UTC 24 |
| Finished | Oct 09 10:16:14 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482560768 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.482560768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/35.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/35.keymgr_direct_to_disabled.2647883165 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 35529956 ps |
| CPU time | 3.25 seconds |
| Started | Oct 09 10:16:08 AM UTC 24 |
| Finished | Oct 09 10:16:12 AM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647883165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2647883165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/35.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/35.keymgr_hwsw_invalid_input.3994609573 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 129022410 ps |
| CPU time | 3.47 seconds |
| Started | Oct 09 10:16:09 AM UTC 24 |
| Finished | Oct 09 10:16:14 AM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994609573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3994609573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/35.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/35.keymgr_kmac_rsp_err.1615580184 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 146163274 ps |
| CPU time | 3.12 seconds |
| Started | Oct 09 10:16:09 AM UTC 24 |
| Finished | Oct 09 10:16:13 AM UTC 24 |
| Peak memory | 223480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615580184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1615580184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/35.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/35.keymgr_lc_disable.3418310821 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 586555991 ps |
| CPU time | 4.06 seconds |
| Started | Oct 09 10:16:08 AM UTC 24 |
| Finished | Oct 09 10:16:13 AM UTC 24 |
| Peak memory | 227640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418310821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3418310821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/35.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/35.keymgr_random.1067440631 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 68128584 ps |
| CPU time | 4.35 seconds |
| Started | Oct 09 10:16:08 AM UTC 24 |
| Finished | Oct 09 10:16:13 AM UTC 24 |
| Peak memory | 227580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067440631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1067440631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/35.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/35.keymgr_sideload.1167632448 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 177176194 ps |
| CPU time | 3.64 seconds |
| Started | Oct 09 10:16:05 AM UTC 24 |
| Finished | Oct 09 10:16:10 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167632448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1167632448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/35.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_aes.1320808093 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 44217150 ps |
| CPU time | 3.36 seconds |
| Started | Oct 09 10:16:06 AM UTC 24 |
| Finished | Oct 09 10:16:11 AM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320808093 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1320808093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/35.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_kmac.1710947022 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 100124075 ps |
| CPU time | 3.68 seconds |
| Started | Oct 09 10:16:06 AM UTC 24 |
| Finished | Oct 09 10:16:11 AM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710947022 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1710947022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/35.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_otbn.891866890 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 1654565048 ps |
| CPU time | 41.49 seconds |
| Started | Oct 09 10:16:07 AM UTC 24 |
| Finished | Oct 09 10:16:50 AM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891866890 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.891866890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/35.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_protect.3894458882 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 144302943 ps |
| CPU time | 5.82 seconds |
| Started | Oct 09 10:16:09 AM UTC 24 |
| Finished | Oct 09 10:16:16 AM UTC 24 |
| Peak memory | 217464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894458882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3894458882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/35.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/35.keymgr_smoke.4255699314 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 118974237 ps |
| CPU time | 4.71 seconds |
| Started | Oct 09 10:16:04 AM UTC 24 |
| Finished | Oct 09 10:16:10 AM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255699314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.4255699314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/35.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all.1961222300 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 21781193179 ps |
| CPU time | 506.28 seconds |
| Started | Oct 09 10:16:11 AM UTC 24 |
| Finished | Oct 09 10:24:44 AM UTC 24 |
| Peak memory | 231668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961222300 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1961222300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/35.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/35.keymgr_sw_invalid_input.1518576173 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 812965519 ps |
| CPU time | 24.9 seconds |
| Started | Oct 09 10:16:09 AM UTC 24 |
| Finished | Oct 09 10:16:35 AM UTC 24 |
| Peak memory | 229748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518576173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1518576173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/35.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/35.keymgr_sync_async_fault_cross.823784338 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 115955386 ps |
| CPU time | 2.37 seconds |
| Started | Oct 09 10:16:09 AM UTC 24 |
| Finished | Oct 09 10:16:13 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823784338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.823784338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/35.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/36.keymgr_alert_test.65080420 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 14910720 ps |
| CPU time | 1.37 seconds |
| Started | Oct 09 10:16:18 AM UTC 24 |
| Finished | Oct 09 10:16:21 AM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65080420 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.65080420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/36.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/36.keymgr_custom_cm.1304869231 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 213379564 ps |
| CPU time | 3.79 seconds |
| Started | Oct 09 10:16:16 AM UTC 24 |
| Finished | Oct 09 10:16:21 AM UTC 24 |
| Peak memory | 227840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304869231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1304869231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/36.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/36.keymgr_direct_to_disabled.2920592727 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 244988618 ps |
| CPU time | 3.12 seconds |
| Started | Oct 09 10:16:14 AM UTC 24 |
| Finished | Oct 09 10:16:19 AM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920592727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2920592727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/36.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/36.keymgr_hwsw_invalid_input.4077165801 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 396435362 ps |
| CPU time | 3.28 seconds |
| Started | Oct 09 10:16:15 AM UTC 24 |
| Finished | Oct 09 10:16:19 AM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077165801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.4077165801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/36.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/36.keymgr_kmac_rsp_err.92119582 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 796149288 ps |
| CPU time | 4.8 seconds |
| Started | Oct 09 10:16:15 AM UTC 24 |
| Finished | Oct 09 10:16:21 AM UTC 24 |
| Peak memory | 231628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92119582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.92119582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/36.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/36.keymgr_lc_disable.606818133 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 44177400 ps |
| CPU time | 2.83 seconds |
| Started | Oct 09 10:16:15 AM UTC 24 |
| Finished | Oct 09 10:16:19 AM UTC 24 |
| Peak memory | 223740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606818133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.606818133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/36.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/36.keymgr_random.4184603938 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 283895646 ps |
| CPU time | 11.8 seconds |
| Started | Oct 09 10:16:14 AM UTC 24 |
| Finished | Oct 09 10:16:27 AM UTC 24 |
| Peak memory | 223548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184603938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.4184603938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/36.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/36.keymgr_sideload.287809700 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 185034101 ps |
| CPU time | 2.26 seconds |
| Started | Oct 09 10:16:13 AM UTC 24 |
| Finished | Oct 09 10:16:16 AM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287809700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.287809700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/36.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_aes.2736964954 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 2026007785 ps |
| CPU time | 20.39 seconds |
| Started | Oct 09 10:16:13 AM UTC 24 |
| Finished | Oct 09 10:16:35 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736964954 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2736964954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/36.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_kmac.1553349152 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 283917445 ps |
| CPU time | 3.74 seconds |
| Started | Oct 09 10:16:13 AM UTC 24 |
| Finished | Oct 09 10:16:18 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553349152 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1553349152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/36.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_otbn.3275190055 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 376080455 ps |
| CPU time | 6.69 seconds |
| Started | Oct 09 10:16:13 AM UTC 24 |
| Finished | Oct 09 10:16:21 AM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275190055 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3275190055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/36.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_protect.1887543305 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 410053818 ps |
| CPU time | 5.44 seconds |
| Started | Oct 09 10:16:16 AM UTC 24 |
| Finished | Oct 09 10:16:22 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887543305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1887543305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/36.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/36.keymgr_smoke.3881026444 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 61867198 ps |
| CPU time | 2.46 seconds |
| Started | Oct 09 10:16:12 AM UTC 24 |
| Finished | Oct 09 10:16:15 AM UTC 24 |
| Peak memory | 215356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881026444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3881026444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/36.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/36.keymgr_stress_all_with_rand_reset.1016393236 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 840188053 ps |
| CPU time | 30.5 seconds |
| Started | Oct 09 10:16:18 AM UTC 24 |
| Finished | Oct 09 10:16:50 AM UTC 24 |
| Peak memory | 231136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1016393236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymg r_stress_all_with_rand_reset.1016393236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/36.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/36.keymgr_sw_invalid_input.894880913 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 270245531 ps |
| CPU time | 9.54 seconds |
| Started | Oct 09 10:16:15 AM UTC 24 |
| Finished | Oct 09 10:16:25 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894880913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.894880913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/36.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/36.keymgr_sync_async_fault_cross.2298663152 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 87008673 ps |
| CPU time | 2.21 seconds |
| Started | Oct 09 10:16:17 AM UTC 24 |
| Finished | Oct 09 10:16:20 AM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298663152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2298663152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/36.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/37.keymgr_alert_test.2211095903 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 32448800 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 10:16:28 AM UTC 24 |
| Finished | Oct 09 10:16:30 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211095903 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2211095903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/37.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/37.keymgr_cfg_regwen.1655747 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1657378686 ps |
| CPU time | 7.13 seconds |
| Started | Oct 09 10:16:22 AM UTC 24 |
| Finished | Oct 09 10:16:30 AM UTC 24 |
| Peak memory | 225588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1655747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/37.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/37.keymgr_custom_cm.2973255426 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 141858002 ps |
| CPU time | 5.63 seconds |
| Started | Oct 09 10:16:26 AM UTC 24 |
| Finished | Oct 09 10:16:32 AM UTC 24 |
| Peak memory | 230240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973255426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2973255426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/37.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/37.keymgr_direct_to_disabled.2970839983 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 1601832767 ps |
| CPU time | 18.64 seconds |
| Started | Oct 09 10:16:22 AM UTC 24 |
| Finished | Oct 09 10:16:42 AM UTC 24 |
| Peak memory | 217320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970839983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2970839983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/37.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/37.keymgr_hwsw_invalid_input.2310535157 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 68222489 ps |
| CPU time | 2.9 seconds |
| Started | Oct 09 10:16:22 AM UTC 24 |
| Finished | Oct 09 10:16:26 AM UTC 24 |
| Peak memory | 231620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310535157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2310535157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/37.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/37.keymgr_kmac_rsp_err.4224501952 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 233766446 ps |
| CPU time | 5 seconds |
| Started | Oct 09 10:16:23 AM UTC 24 |
| Finished | Oct 09 10:16:30 AM UTC 24 |
| Peak memory | 225456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224501952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.4224501952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/37.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/37.keymgr_lc_disable.857291610 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 334073197 ps |
| CPU time | 5.58 seconds |
| Started | Oct 09 10:16:22 AM UTC 24 |
| Finished | Oct 09 10:16:29 AM UTC 24 |
| Peak memory | 229884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857291610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.857291610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/37.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/37.keymgr_random.2966525985 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 3692504805 ps |
| CPU time | 22.61 seconds |
| Started | Oct 09 10:16:22 AM UTC 24 |
| Finished | Oct 09 10:16:46 AM UTC 24 |
| Peak memory | 217468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966525985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2966525985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/37.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/37.keymgr_sideload.2635851620 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 558767526 ps |
| CPU time | 6.34 seconds |
| Started | Oct 09 10:16:20 AM UTC 24 |
| Finished | Oct 09 10:16:27 AM UTC 24 |
| Peak memory | 215568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635851620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2635851620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/37.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_aes.4277411301 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 604262522 ps |
| CPU time | 4.12 seconds |
| Started | Oct 09 10:16:21 AM UTC 24 |
| Finished | Oct 09 10:16:26 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277411301 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.4277411301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/37.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_kmac.2657799593 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 169913018 ps |
| CPU time | 3.7 seconds |
| Started | Oct 09 10:16:21 AM UTC 24 |
| Finished | Oct 09 10:16:25 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657799593 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2657799593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/37.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_otbn.3937847081 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 50589126 ps |
| CPU time | 3.76 seconds |
| Started | Oct 09 10:16:21 AM UTC 24 |
| Finished | Oct 09 10:16:26 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937847081 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3937847081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/37.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_protect.3848685310 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 182868176 ps |
| CPU time | 5.8 seconds |
| Started | Oct 09 10:16:27 AM UTC 24 |
| Finished | Oct 09 10:16:34 AM UTC 24 |
| Peak memory | 219780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848685310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3848685310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/37.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/37.keymgr_smoke.3314650857 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 373790666 ps |
| CPU time | 3.83 seconds |
| Started | Oct 09 10:16:19 AM UTC 24 |
| Finished | Oct 09 10:16:24 AM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314650857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3314650857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/37.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all.3649325155 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 52235263797 ps |
| CPU time | 234.05 seconds |
| Started | Oct 09 10:16:27 AM UTC 24 |
| Finished | Oct 09 10:20:25 AM UTC 24 |
| Peak memory | 229740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649325155 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3649325155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/37.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all_with_rand_reset.2705764762 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 457571990 ps |
| CPU time | 15.02 seconds |
| Started | Oct 09 10:16:27 AM UTC 24 |
| Finished | Oct 09 10:16:43 AM UTC 24 |
| Peak memory | 230144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2705764762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymg r_stress_all_with_rand_reset.2705764762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/37.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/37.keymgr_sw_invalid_input.667093958 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 77209491 ps |
| CPU time | 5.5 seconds |
| Started | Oct 09 10:16:22 AM UTC 24 |
| Finished | Oct 09 10:16:29 AM UTC 24 |
| Peak memory | 217320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667093958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.667093958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/37.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/37.keymgr_sync_async_fault_cross.1075153705 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 115720624 ps |
| CPU time | 2.35 seconds |
| Started | Oct 09 10:16:27 AM UTC 24 |
| Finished | Oct 09 10:16:30 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075153705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1075153705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/37.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/38.keymgr_alert_test.3749941726 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 138458476 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 10:16:37 AM UTC 24 |
| Finished | Oct 09 10:16:39 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749941726 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3749941726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/38.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/38.keymgr_cfg_regwen.3076265811 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 464699300 ps |
| CPU time | 9.73 seconds |
| Started | Oct 09 10:16:31 AM UTC 24 |
| Finished | Oct 09 10:16:42 AM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076265811 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3076265811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/38.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/38.keymgr_custom_cm.2306828848 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 224573231 ps |
| CPU time | 3.91 seconds |
| Started | Oct 09 10:16:36 AM UTC 24 |
| Finished | Oct 09 10:16:41 AM UTC 24 |
| Peak memory | 217660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306828848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2306828848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/38.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/38.keymgr_direct_to_disabled.1001228160 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 70941572 ps |
| CPU time | 2.77 seconds |
| Started | Oct 09 10:16:32 AM UTC 24 |
| Finished | Oct 09 10:16:36 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001228160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1001228160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/38.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/38.keymgr_kmac_rsp_err.3478597922 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 165515368 ps |
| CPU time | 5.61 seconds |
| Started | Oct 09 10:16:34 AM UTC 24 |
| Finished | Oct 09 10:16:41 AM UTC 24 |
| Peak memory | 231544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478597922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3478597922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/38.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/38.keymgr_lc_disable.1933471987 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 40791844 ps |
| CPU time | 3.32 seconds |
| Started | Oct 09 10:16:32 AM UTC 24 |
| Finished | Oct 09 10:16:36 AM UTC 24 |
| Peak memory | 229688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933471987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1933471987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/38.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/38.keymgr_random.2111965725 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 110402457 ps |
| CPU time | 3.13 seconds |
| Started | Oct 09 10:16:31 AM UTC 24 |
| Finished | Oct 09 10:16:35 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111965725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2111965725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/38.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/38.keymgr_sideload.499741835 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 68123473 ps |
| CPU time | 3.21 seconds |
| Started | Oct 09 10:16:28 AM UTC 24 |
| Finished | Oct 09 10:16:33 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499741835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.499741835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/38.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_aes.3087302632 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 281892318 ps |
| CPU time | 4.6 seconds |
| Started | Oct 09 10:16:29 AM UTC 24 |
| Finished | Oct 09 10:16:35 AM UTC 24 |
| Peak memory | 217472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087302632 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3087302632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/38.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_kmac.521779475 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 823676712 ps |
| CPU time | 10.67 seconds |
| Started | Oct 09 10:16:29 AM UTC 24 |
| Finished | Oct 09 10:16:41 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521779475 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.521779475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/38.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_otbn.1446436125 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 156257159 ps |
| CPU time | 5.97 seconds |
| Started | Oct 09 10:16:29 AM UTC 24 |
| Finished | Oct 09 10:16:37 AM UTC 24 |
| Peak memory | 217460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446436125 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1446436125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/38.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_protect.649668606 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 64799880 ps |
| CPU time | 2.62 seconds |
| Started | Oct 09 10:16:36 AM UTC 24 |
| Finished | Oct 09 10:16:40 AM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649668606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.649668606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/38.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/38.keymgr_smoke.3279012841 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 996046894 ps |
| CPU time | 24.11 seconds |
| Started | Oct 09 10:16:28 AM UTC 24 |
| Finished | Oct 09 10:16:54 AM UTC 24 |
| Peak memory | 217668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279012841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3279012841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/38.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all_with_rand_reset.2030827654 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 310512976 ps |
| CPU time | 11.24 seconds |
| Started | Oct 09 10:16:37 AM UTC 24 |
| Finished | Oct 09 10:16:49 AM UTC 24 |
| Peak memory | 231740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2030827654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymg r_stress_all_with_rand_reset.2030827654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/38.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/38.keymgr_sw_invalid_input.3794915294 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 109291300 ps |
| CPU time | 5.24 seconds |
| Started | Oct 09 10:16:33 AM UTC 24 |
| Finished | Oct 09 10:16:39 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794915294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3794915294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/38.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/38.keymgr_sync_async_fault_cross.1281735762 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 358029170 ps |
| CPU time | 2.85 seconds |
| Started | Oct 09 10:16:36 AM UTC 24 |
| Finished | Oct 09 10:16:40 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281735762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1281735762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/38.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/39.keymgr_alert_test.4291846462 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 43119665 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 10:16:44 AM UTC 24 |
| Finished | Oct 09 10:16:47 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291846462 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.4291846462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/39.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/39.keymgr_cfg_regwen.2886508875 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 193139028 ps |
| CPU time | 5.11 seconds |
| Started | Oct 09 10:16:41 AM UTC 24 |
| Finished | Oct 09 10:16:47 AM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886508875 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2886508875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/39.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/39.keymgr_direct_to_disabled.1660194893 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 289730522 ps |
| CPU time | 3.63 seconds |
| Started | Oct 09 10:16:42 AM UTC 24 |
| Finished | Oct 09 10:16:47 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660194893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1660194893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/39.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/39.keymgr_hwsw_invalid_input.2433713021 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 45849886 ps |
| CPU time | 2.95 seconds |
| Started | Oct 09 10:16:43 AM UTC 24 |
| Finished | Oct 09 10:16:47 AM UTC 24 |
| Peak memory | 231588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433713021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2433713021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/39.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/39.keymgr_kmac_rsp_err.2945472148 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 124784335 ps |
| CPU time | 4.47 seconds |
| Started | Oct 09 10:16:43 AM UTC 24 |
| Finished | Oct 09 10:16:48 AM UTC 24 |
| Peak memory | 223480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945472148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2945472148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/39.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/39.keymgr_lc_disable.3745970265 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 47631711 ps |
| CPU time | 3.7 seconds |
| Started | Oct 09 10:16:42 AM UTC 24 |
| Finished | Oct 09 10:16:48 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745970265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3745970265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/39.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/39.keymgr_random.1073101550 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 494868233 ps |
| CPU time | 7.23 seconds |
| Started | Oct 09 10:16:41 AM UTC 24 |
| Finished | Oct 09 10:16:49 AM UTC 24 |
| Peak memory | 223688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073101550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1073101550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/39.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/39.keymgr_sideload.3615563385 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 669955257 ps |
| CPU time | 5.41 seconds |
| Started | Oct 09 10:16:38 AM UTC 24 |
| Finished | Oct 09 10:16:45 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615563385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3615563385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/39.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_aes.347610150 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 143112206 ps |
| CPU time | 3.45 seconds |
| Started | Oct 09 10:16:40 AM UTC 24 |
| Finished | Oct 09 10:16:44 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347610150 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.347610150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/39.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_kmac.81330917 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 307764371 ps |
| CPU time | 2.44 seconds |
| Started | Oct 09 10:16:40 AM UTC 24 |
| Finished | Oct 09 10:16:43 AM UTC 24 |
| Peak memory | 215536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81330917 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.81330917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/39.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_otbn.3112331048 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 32680798 ps |
| CPU time | 3.2 seconds |
| Started | Oct 09 10:16:41 AM UTC 24 |
| Finished | Oct 09 10:16:45 AM UTC 24 |
| Peak memory | 217660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112331048 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3112331048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/39.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_protect.4246108952 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 2918545342 ps |
| CPU time | 13.95 seconds |
| Started | Oct 09 10:16:44 AM UTC 24 |
| Finished | Oct 09 10:17:00 AM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246108952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.4246108952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/39.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/39.keymgr_smoke.3111352567 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 981161588 ps |
| CPU time | 3.58 seconds |
| Started | Oct 09 10:16:38 AM UTC 24 |
| Finished | Oct 09 10:16:43 AM UTC 24 |
| Peak memory | 215416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111352567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3111352567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/39.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all.3905177773 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 664978585 ps |
| CPU time | 26.89 seconds |
| Started | Oct 09 10:16:44 AM UTC 24 |
| Finished | Oct 09 10:17:13 AM UTC 24 |
| Peak memory | 231592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905177773 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3905177773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/39.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all_with_rand_reset.62700067 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 1769436028 ps |
| CPU time | 40.42 seconds |
| Started | Oct 09 10:16:44 AM UTC 24 |
| Finished | Oct 09 10:17:27 AM UTC 24 |
| Peak memory | 231996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=62700067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_ stress_all_with_rand_reset.62700067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/39.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/39.keymgr_sw_invalid_input.3184933539 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 1002129529 ps |
| CPU time | 24.71 seconds |
| Started | Oct 09 10:16:43 AM UTC 24 |
| Finished | Oct 09 10:17:09 AM UTC 24 |
| Peak memory | 223544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184933539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3184933539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/39.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/39.keymgr_sync_async_fault_cross.559685961 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 131662124 ps |
| CPU time | 2.23 seconds |
| Started | Oct 09 10:16:44 AM UTC 24 |
| Finished | Oct 09 10:16:48 AM UTC 24 |
| Peak memory | 217404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559685961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.559685961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/39.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/4.keymgr_alert_test.1201052146 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 22208803 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:12:00 AM UTC 24 |
| Finished | Oct 09 10:12:02 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201052146 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1201052146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/4.keymgr_cfg_regwen.660446288 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 70622869 ps |
| CPU time | 4.39 seconds |
| Started | Oct 09 10:11:53 AM UTC 24 |
| Finished | Oct 09 10:11:58 AM UTC 24 |
| Peak memory | 225800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660446288 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.660446288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/4.keymgr_custom_cm.3743044081 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 31688218 ps |
| CPU time | 2.26 seconds |
| Started | Oct 09 10:11:56 AM UTC 24 |
| Finished | Oct 09 10:12:00 AM UTC 24 |
| Peak memory | 213836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743044081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3743044081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/4.keymgr_direct_to_disabled.1273610621 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 111858391 ps |
| CPU time | 4.25 seconds |
| Started | Oct 09 10:11:55 AM UTC 24 |
| Finished | Oct 09 10:12:00 AM UTC 24 |
| Peak memory | 215536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273610621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1273610621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/4.keymgr_hwsw_invalid_input.789594392 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 121282766 ps |
| CPU time | 5.97 seconds |
| Started | Oct 09 10:11:56 AM UTC 24 |
| Finished | Oct 09 10:12:03 AM UTC 24 |
| Peak memory | 230440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789594392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.789594392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/4.keymgr_kmac_rsp_err.2548449441 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 82729132 ps |
| CPU time | 3.44 seconds |
| Started | Oct 09 10:11:56 AM UTC 24 |
| Finished | Oct 09 10:12:01 AM UTC 24 |
| Peak memory | 223680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548449441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2548449441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/4.keymgr_random.2138660598 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 134225911 ps |
| CPU time | 7.24 seconds |
| Started | Oct 09 10:11:53 AM UTC 24 |
| Finished | Oct 09 10:12:01 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138660598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2138660598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/4.keymgr_sec_cm.2812708712 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2138549023 ps |
| CPU time | 10.13 seconds |
| Started | Oct 09 10:12:00 AM UTC 24 |
| Finished | Oct 09 10:12:11 AM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812708712 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2812708712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/4.keymgr_sideload.2517024805 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 274401334 ps |
| CPU time | 6.12 seconds |
| Started | Oct 09 10:11:51 AM UTC 24 |
| Finished | Oct 09 10:11:59 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517024805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2517024805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_aes.19766849 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 63144659 ps |
| CPU time | 4.97 seconds |
| Started | Oct 09 10:11:53 AM UTC 24 |
| Finished | Oct 09 10:11:59 AM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19766849 -assert nopostproc +UVM_TESTNAME=keymgr_base_ test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.19766849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_kmac.928755112 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 111342366 ps |
| CPU time | 3.08 seconds |
| Started | Oct 09 10:11:53 AM UTC 24 |
| Finished | Oct 09 10:11:57 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928755112 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.928755112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_otbn.4039935010 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 155079645 ps |
| CPU time | 3.13 seconds |
| Started | Oct 09 10:11:53 AM UTC 24 |
| Finished | Oct 09 10:11:57 AM UTC 24 |
| Peak memory | 217460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039935010 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.4039935010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_protect.2101278336 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 293735220 ps |
| CPU time | 4.39 seconds |
| Started | Oct 09 10:11:57 AM UTC 24 |
| Finished | Oct 09 10:12:03 AM UTC 24 |
| Peak memory | 215608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101278336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2101278336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/4.keymgr_smoke.2919580632 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 62617571 ps |
| CPU time | 2.91 seconds |
| Started | Oct 09 10:11:51 AM UTC 24 |
| Finished | Oct 09 10:11:55 AM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919580632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2919580632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/4.keymgr_sw_invalid_input.445955583 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1197224338 ps |
| CPU time | 23.74 seconds |
| Started | Oct 09 10:11:56 AM UTC 24 |
| Finished | Oct 09 10:12:21 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445955583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.445955583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/4.keymgr_sync_async_fault_cross.1042912984 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 272342296 ps |
| CPU time | 3.28 seconds |
| Started | Oct 09 10:11:58 AM UTC 24 |
| Finished | Oct 09 10:12:02 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042912984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1042912984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/40.keymgr_alert_test.3465394299 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 29269059 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 10:16:53 AM UTC 24 |
| Finished | Oct 09 10:16:55 AM UTC 24 |
| Peak memory | 212740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465394299 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3465394299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/40.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/40.keymgr_custom_cm.13501608 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 93193351 ps |
| CPU time | 4.29 seconds |
| Started | Oct 09 10:16:50 AM UTC 24 |
| Finished | Oct 09 10:16:56 AM UTC 24 |
| Peak memory | 231848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13501608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.13501608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/40.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/40.keymgr_direct_to_disabled.968392561 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 27514346 ps |
| CPU time | 1.85 seconds |
| Started | Oct 09 10:16:49 AM UTC 24 |
| Finished | Oct 09 10:16:52 AM UTC 24 |
| Peak memory | 214840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968392561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.968392561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/40.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/40.keymgr_hwsw_invalid_input.2446695007 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 114399179 ps |
| CPU time | 3.22 seconds |
| Started | Oct 09 10:16:49 AM UTC 24 |
| Finished | Oct 09 10:16:54 AM UTC 24 |
| Peak memory | 223468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446695007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2446695007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/40.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/40.keymgr_kmac_rsp_err.2503692110 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 276220660 ps |
| CPU time | 3.69 seconds |
| Started | Oct 09 10:16:50 AM UTC 24 |
| Finished | Oct 09 10:16:55 AM UTC 24 |
| Peak memory | 223408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503692110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2503692110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/40.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/40.keymgr_lc_disable.870777526 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 437286589 ps |
| CPU time | 5.03 seconds |
| Started | Oct 09 10:16:49 AM UTC 24 |
| Finished | Oct 09 10:16:55 AM UTC 24 |
| Peak memory | 217404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870777526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.870777526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/40.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/40.keymgr_random.1280156867 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 54993471 ps |
| CPU time | 3.75 seconds |
| Started | Oct 09 10:16:48 AM UTC 24 |
| Finished | Oct 09 10:16:53 AM UTC 24 |
| Peak memory | 217200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280156867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1280156867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/40.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/40.keymgr_sideload.579709361 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 174415873 ps |
| CPU time | 6.71 seconds |
| Started | Oct 09 10:16:45 AM UTC 24 |
| Finished | Oct 09 10:16:54 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579709361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.579709361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/40.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_aes.827460094 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 153009997 ps |
| CPU time | 4.86 seconds |
| Started | Oct 09 10:16:47 AM UTC 24 |
| Finished | Oct 09 10:16:53 AM UTC 24 |
| Peak memory | 217724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827460094 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.827460094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/40.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_kmac.450130047 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 69829051 ps |
| CPU time | 2.87 seconds |
| Started | Oct 09 10:16:45 AM UTC 24 |
| Finished | Oct 09 10:16:50 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450130047 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.450130047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/40.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_otbn.2602907919 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 207289542 ps |
| CPU time | 5.45 seconds |
| Started | Oct 09 10:16:47 AM UTC 24 |
| Finished | Oct 09 10:16:53 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602907919 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2602907919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/40.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_protect.2306836838 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 149381628 ps |
| CPU time | 4.84 seconds |
| Started | Oct 09 10:16:50 AM UTC 24 |
| Finished | Oct 09 10:16:57 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306836838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2306836838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/40.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/40.keymgr_smoke.3215598101 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 172924657 ps |
| CPU time | 5.55 seconds |
| Started | Oct 09 10:16:44 AM UTC 24 |
| Finished | Oct 09 10:16:52 AM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215598101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3215598101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/40.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all.259652041 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 3679316489 ps |
| CPU time | 25.11 seconds |
| Started | Oct 09 10:16:51 AM UTC 24 |
| Finished | Oct 09 10:17:17 AM UTC 24 |
| Peak memory | 225844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259652041 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.259652041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/40.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/40.keymgr_sw_invalid_input.3494150769 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 86186471 ps |
| CPU time | 5.5 seconds |
| Started | Oct 09 10:16:49 AM UTC 24 |
| Finished | Oct 09 10:16:56 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494150769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3494150769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/40.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/40.keymgr_sync_async_fault_cross.97114964 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1013598300 ps |
| CPU time | 10.87 seconds |
| Started | Oct 09 10:16:50 AM UTC 24 |
| Finished | Oct 09 10:17:03 AM UTC 24 |
| Peak memory | 219428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97114964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.97114964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/40.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/41.keymgr_alert_test.3448118135 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 21606819 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 10:16:59 AM UTC 24 |
| Finished | Oct 09 10:17:02 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448118135 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3448118135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/41.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/41.keymgr_direct_to_disabled.89357985 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 249431936 ps |
| CPU time | 8.01 seconds |
| Started | Oct 09 10:16:56 AM UTC 24 |
| Finished | Oct 09 10:17:05 AM UTC 24 |
| Peak memory | 227632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89357985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.89357985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/41.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/41.keymgr_hwsw_invalid_input.2416413422 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 361883290 ps |
| CPU time | 9.56 seconds |
| Started | Oct 09 10:16:57 AM UTC 24 |
| Finished | Oct 09 10:17:08 AM UTC 24 |
| Peak memory | 231644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416413422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2416413422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/41.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/41.keymgr_kmac_rsp_err.2659608852 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 151201284 ps |
| CPU time | 3.09 seconds |
| Started | Oct 09 10:16:57 AM UTC 24 |
| Finished | Oct 09 10:17:01 AM UTC 24 |
| Peak memory | 229552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659608852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2659608852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/41.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/41.keymgr_lc_disable.4204342109 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 44303647 ps |
| CPU time | 3.8 seconds |
| Started | Oct 09 10:16:56 AM UTC 24 |
| Finished | Oct 09 10:17:00 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204342109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.4204342109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/41.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/41.keymgr_random.133224915 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 65560999 ps |
| CPU time | 4.29 seconds |
| Started | Oct 09 10:16:55 AM UTC 24 |
| Finished | Oct 09 10:17:01 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133224915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.133224915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/41.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/41.keymgr_sideload.1215916506 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 144691148 ps |
| CPU time | 4.59 seconds |
| Started | Oct 09 10:16:54 AM UTC 24 |
| Finished | Oct 09 10:17:00 AM UTC 24 |
| Peak memory | 217244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215916506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1215916506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/41.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_aes.2356349174 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 131926297 ps |
| CPU time | 3.66 seconds |
| Started | Oct 09 10:16:54 AM UTC 24 |
| Finished | Oct 09 10:16:59 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356349174 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2356349174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/41.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_kmac.3039930017 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 45588417 ps |
| CPU time | 2.63 seconds |
| Started | Oct 09 10:16:54 AM UTC 24 |
| Finished | Oct 09 10:16:58 AM UTC 24 |
| Peak memory | 215312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039930017 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3039930017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/41.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_otbn.3173636212 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 82139682 ps |
| CPU time | 3.63 seconds |
| Started | Oct 09 10:16:54 AM UTC 24 |
| Finished | Oct 09 10:16:59 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173636212 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3173636212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/41.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_protect.405633264 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 292900995 ps |
| CPU time | 4.89 seconds |
| Started | Oct 09 10:16:57 AM UTC 24 |
| Finished | Oct 09 10:17:03 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405633264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.405633264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/41.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/41.keymgr_smoke.558514486 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 32958948 ps |
| CPU time | 2.96 seconds |
| Started | Oct 09 10:16:53 AM UTC 24 |
| Finished | Oct 09 10:16:57 AM UTC 24 |
| Peak memory | 215152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558514486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.558514486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/41.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all.3799440235 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 6128534989 ps |
| CPU time | 67.28 seconds |
| Started | Oct 09 10:16:58 AM UTC 24 |
| Finished | Oct 09 10:18:07 AM UTC 24 |
| Peak memory | 227956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799440235 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3799440235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/41.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/41.keymgr_sw_invalid_input.1056192831 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 185769659 ps |
| CPU time | 7.11 seconds |
| Started | Oct 09 10:16:56 AM UTC 24 |
| Finished | Oct 09 10:17:04 AM UTC 24 |
| Peak memory | 223616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056192831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1056192831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/41.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/41.keymgr_sync_async_fault_cross.659161112 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 747587802 ps |
| CPU time | 9.36 seconds |
| Started | Oct 09 10:16:58 AM UTC 24 |
| Finished | Oct 09 10:17:09 AM UTC 24 |
| Peak memory | 219448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659161112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.659161112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/41.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/42.keymgr_alert_test.1054847263 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 20268604 ps |
| CPU time | 1.36 seconds |
| Started | Oct 09 10:17:07 AM UTC 24 |
| Finished | Oct 09 10:17:10 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054847263 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1054847263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/42.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/42.keymgr_custom_cm.2972912561 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 92168542 ps |
| CPU time | 2.45 seconds |
| Started | Oct 09 10:17:06 AM UTC 24 |
| Finished | Oct 09 10:17:09 AM UTC 24 |
| Peak memory | 229696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972912561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2972912561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/42.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/42.keymgr_direct_to_disabled.843834733 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 1368618414 ps |
| CPU time | 3.66 seconds |
| Started | Oct 09 10:17:03 AM UTC 24 |
| Finished | Oct 09 10:17:08 AM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843834733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.843834733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/42.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/42.keymgr_hwsw_invalid_input.416704629 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 66976733 ps |
| CPU time | 2.64 seconds |
| Started | Oct 09 10:17:04 AM UTC 24 |
| Finished | Oct 09 10:17:08 AM UTC 24 |
| Peak memory | 223872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416704629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.416704629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/42.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/42.keymgr_kmac_rsp_err.922954742 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 142514156 ps |
| CPU time | 2.26 seconds |
| Started | Oct 09 10:17:04 AM UTC 24 |
| Finished | Oct 09 10:17:08 AM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922954742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.922954742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/42.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/42.keymgr_lc_disable.3154681109 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 134219287 ps |
| CPU time | 4.19 seconds |
| Started | Oct 09 10:17:04 AM UTC 24 |
| Finished | Oct 09 10:17:10 AM UTC 24 |
| Peak memory | 217540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154681109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3154681109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/42.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/42.keymgr_random.988330257 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 200196537 ps |
| CPU time | 7.32 seconds |
| Started | Oct 09 10:17:02 AM UTC 24 |
| Finished | Oct 09 10:17:11 AM UTC 24 |
| Peak memory | 219588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988330257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.988330257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/42.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/42.keymgr_sideload.3435306038 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 141699896 ps |
| CPU time | 2.65 seconds |
| Started | Oct 09 10:17:01 AM UTC 24 |
| Finished | Oct 09 10:17:04 AM UTC 24 |
| Peak memory | 217316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435306038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3435306038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/42.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_aes.2003106806 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 376589519 ps |
| CPU time | 8.74 seconds |
| Started | Oct 09 10:17:01 AM UTC 24 |
| Finished | Oct 09 10:17:11 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003106806 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2003106806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/42.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_kmac.2075639138 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 64145852 ps |
| CPU time | 3.71 seconds |
| Started | Oct 09 10:17:01 AM UTC 24 |
| Finished | Oct 09 10:17:06 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075639138 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2075639138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/42.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_otbn.2972778799 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 210974879 ps |
| CPU time | 8.48 seconds |
| Started | Oct 09 10:17:02 AM UTC 24 |
| Finished | Oct 09 10:17:12 AM UTC 24 |
| Peak memory | 217536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972778799 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2972778799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/42.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_protect.1067730051 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 142018731 ps |
| CPU time | 6.02 seconds |
| Started | Oct 09 10:17:06 AM UTC 24 |
| Finished | Oct 09 10:17:13 AM UTC 24 |
| Peak memory | 217276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067730051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1067730051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/42.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/42.keymgr_smoke.2083683387 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 39839574 ps |
| CPU time | 3.09 seconds |
| Started | Oct 09 10:16:59 AM UTC 24 |
| Finished | Oct 09 10:17:03 AM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083683387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2083683387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/42.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/42.keymgr_sw_invalid_input.3419576651 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 72032847 ps |
| CPU time | 3.86 seconds |
| Started | Oct 09 10:17:04 AM UTC 24 |
| Finished | Oct 09 10:17:09 AM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419576651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3419576651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/42.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/42.keymgr_sync_async_fault_cross.3752743473 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 169518375 ps |
| CPU time | 5.72 seconds |
| Started | Oct 09 10:17:06 AM UTC 24 |
| Finished | Oct 09 10:17:13 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752743473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3752743473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/42.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/43.keymgr_alert_test.2224010594 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 9210719 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 10:17:13 AM UTC 24 |
| Finished | Oct 09 10:17:15 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224010594 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2224010594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/43.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/43.keymgr_custom_cm.3141187765 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 169977286 ps |
| CPU time | 5.04 seconds |
| Started | Oct 09 10:17:12 AM UTC 24 |
| Finished | Oct 09 10:17:18 AM UTC 24 |
| Peak memory | 223884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141187765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3141187765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/43.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/43.keymgr_direct_to_disabled.4288696777 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 88199511 ps |
| CPU time | 2.87 seconds |
| Started | Oct 09 10:17:11 AM UTC 24 |
| Finished | Oct 09 10:17:15 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288696777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.4288696777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/43.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/43.keymgr_hwsw_invalid_input.28626808 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 346940451 ps |
| CPU time | 9.51 seconds |
| Started | Oct 09 10:17:11 AM UTC 24 |
| Finished | Oct 09 10:17:21 AM UTC 24 |
| Peak memory | 223536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28626808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.28626808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/43.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/43.keymgr_kmac_rsp_err.1286502341 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 280992388 ps |
| CPU time | 3.79 seconds |
| Started | Oct 09 10:17:11 AM UTC 24 |
| Finished | Oct 09 10:17:16 AM UTC 24 |
| Peak memory | 223408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286502341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1286502341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/43.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/43.keymgr_lc_disable.3404668309 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 75220783 ps |
| CPU time | 4.72 seconds |
| Started | Oct 09 10:17:11 AM UTC 24 |
| Finished | Oct 09 10:17:17 AM UTC 24 |
| Peak memory | 225664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404668309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3404668309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/43.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/43.keymgr_random.2612620180 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 158997307 ps |
| CPU time | 5.97 seconds |
| Started | Oct 09 10:17:09 AM UTC 24 |
| Finished | Oct 09 10:17:16 AM UTC 24 |
| Peak memory | 223548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612620180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2612620180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/43.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/43.keymgr_sideload.1183629494 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 91931446 ps |
| CPU time | 4.04 seconds |
| Started | Oct 09 10:17:08 AM UTC 24 |
| Finished | Oct 09 10:17:13 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183629494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1183629494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/43.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_aes.1923669236 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 1577088460 ps |
| CPU time | 14.62 seconds |
| Started | Oct 09 10:17:09 AM UTC 24 |
| Finished | Oct 09 10:17:25 AM UTC 24 |
| Peak memory | 217352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923669236 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1923669236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/43.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_kmac.3012673980 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 55988094 ps |
| CPU time | 2.38 seconds |
| Started | Oct 09 10:17:09 AM UTC 24 |
| Finished | Oct 09 10:17:13 AM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012673980 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3012673980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/43.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_otbn.1486878965 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 576432276 ps |
| CPU time | 17.34 seconds |
| Started | Oct 09 10:17:09 AM UTC 24 |
| Finished | Oct 09 10:17:28 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486878965 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1486878965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/43.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_protect.1390059675 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 114191036 ps |
| CPU time | 2.2 seconds |
| Started | Oct 09 10:17:12 AM UTC 24 |
| Finished | Oct 09 10:17:15 AM UTC 24 |
| Peak memory | 223820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390059675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1390059675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/43.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/43.keymgr_smoke.2983031338 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 240028434 ps |
| CPU time | 6.46 seconds |
| Started | Oct 09 10:17:07 AM UTC 24 |
| Finished | Oct 09 10:17:15 AM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983031338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2983031338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/43.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/43.keymgr_stress_all.4144023627 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1190279151 ps |
| CPU time | 48.75 seconds |
| Started | Oct 09 10:17:13 AM UTC 24 |
| Finished | Oct 09 10:18:03 AM UTC 24 |
| Peak memory | 231276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144023627 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.4144023627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/43.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/43.keymgr_stress_all_with_rand_reset.727812087 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 848247189 ps |
| CPU time | 16.55 seconds |
| Started | Oct 09 10:17:13 AM UTC 24 |
| Finished | Oct 09 10:17:31 AM UTC 24 |
| Peak memory | 229748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=727812087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr _stress_all_with_rand_reset.727812087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/43.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/43.keymgr_sw_invalid_input.2030133457 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 186598475 ps |
| CPU time | 5.53 seconds |
| Started | Oct 09 10:17:11 AM UTC 24 |
| Finished | Oct 09 10:17:17 AM UTC 24 |
| Peak memory | 217576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030133457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2030133457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/43.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/43.keymgr_sync_async_fault_cross.4109686130 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 1739935210 ps |
| CPU time | 17.96 seconds |
| Started | Oct 09 10:17:13 AM UTC 24 |
| Finished | Oct 09 10:17:32 AM UTC 24 |
| Peak memory | 219640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109686130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.4109686130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/43.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/44.keymgr_alert_test.134331282 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 78029320 ps |
| CPU time | 1.38 seconds |
| Started | Oct 09 10:17:22 AM UTC 24 |
| Finished | Oct 09 10:17:24 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134331282 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.134331282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/44.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/44.keymgr_cfg_regwen.3168567828 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 171583030 ps |
| CPU time | 4.68 seconds |
| Started | Oct 09 10:17:16 AM UTC 24 |
| Finished | Oct 09 10:17:22 AM UTC 24 |
| Peak memory | 231688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168567828 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3168567828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/44.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/44.keymgr_custom_cm.2307940556 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 123918964 ps |
| CPU time | 2.48 seconds |
| Started | Oct 09 10:17:19 AM UTC 24 |
| Finished | Oct 09 10:17:22 AM UTC 24 |
| Peak memory | 217732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307940556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2307940556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/44.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/44.keymgr_direct_to_disabled.325647855 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 133597438 ps |
| CPU time | 4.03 seconds |
| Started | Oct 09 10:17:16 AM UTC 24 |
| Finished | Oct 09 10:17:21 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325647855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.325647855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/44.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/44.keymgr_hwsw_invalid_input.1305024058 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 286650823 ps |
| CPU time | 7.55 seconds |
| Started | Oct 09 10:17:17 AM UTC 24 |
| Finished | Oct 09 10:17:26 AM UTC 24 |
| Peak memory | 229764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305024058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1305024058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/44.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/44.keymgr_kmac_rsp_err.3896645260 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 70889066 ps |
| CPU time | 3.73 seconds |
| Started | Oct 09 10:17:17 AM UTC 24 |
| Finished | Oct 09 10:17:22 AM UTC 24 |
| Peak memory | 230172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896645260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3896645260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/44.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/44.keymgr_lc_disable.1993571024 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 653659051 ps |
| CPU time | 7.52 seconds |
| Started | Oct 09 10:17:16 AM UTC 24 |
| Finished | Oct 09 10:17:25 AM UTC 24 |
| Peak memory | 229696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993571024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1993571024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/44.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/44.keymgr_random.1996080408 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 85390384 ps |
| CPU time | 5.73 seconds |
| Started | Oct 09 10:17:16 AM UTC 24 |
| Finished | Oct 09 10:17:23 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996080408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1996080408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/44.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/44.keymgr_sideload.3779787399 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 2180433646 ps |
| CPU time | 30.84 seconds |
| Started | Oct 09 10:17:15 AM UTC 24 |
| Finished | Oct 09 10:17:47 AM UTC 24 |
| Peak memory | 217656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779787399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3779787399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/44.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_aes.3918595269 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 117290567 ps |
| CPU time | 5.29 seconds |
| Started | Oct 09 10:17:15 AM UTC 24 |
| Finished | Oct 09 10:17:21 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918595269 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3918595269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/44.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_kmac.1382669746 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 240683176 ps |
| CPU time | 4.01 seconds |
| Started | Oct 09 10:17:15 AM UTC 24 |
| Finished | Oct 09 10:17:20 AM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382669746 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1382669746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/44.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_otbn.357874718 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 740031303 ps |
| CPU time | 8.46 seconds |
| Started | Oct 09 10:17:16 AM UTC 24 |
| Finished | Oct 09 10:17:25 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357874718 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.357874718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/44.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_protect.3746808467 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 82850133 ps |
| CPU time | 2.45 seconds |
| Started | Oct 09 10:17:19 AM UTC 24 |
| Finished | Oct 09 10:17:22 AM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746808467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3746808467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/44.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/44.keymgr_smoke.4191330249 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 55067900 ps |
| CPU time | 2.88 seconds |
| Started | Oct 09 10:17:14 AM UTC 24 |
| Finished | Oct 09 10:17:18 AM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191330249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.4191330249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/44.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/44.keymgr_stress_all.866039125 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 398844655 ps |
| CPU time | 20.76 seconds |
| Started | Oct 09 10:17:20 AM UTC 24 |
| Finished | Oct 09 10:17:42 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866039125 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.866039125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/44.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/44.keymgr_stress_all_with_rand_reset.3812775579 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 1414687515 ps |
| CPU time | 22.46 seconds |
| Started | Oct 09 10:17:21 AM UTC 24 |
| Finished | Oct 09 10:17:45 AM UTC 24 |
| Peak memory | 231744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3812775579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymg r_stress_all_with_rand_reset.3812775579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/44.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/44.keymgr_sw_invalid_input.3522919002 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 242342355 ps |
| CPU time | 4.48 seconds |
| Started | Oct 09 10:17:17 AM UTC 24 |
| Finished | Oct 09 10:17:23 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522919002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3522919002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/44.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/44.keymgr_sync_async_fault_cross.2408764864 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 177447091 ps |
| CPU time | 2.83 seconds |
| Started | Oct 09 10:17:19 AM UTC 24 |
| Finished | Oct 09 10:17:23 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408764864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2408764864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/44.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/45.keymgr_alert_test.3055062182 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 55473731 ps |
| CPU time | 1.43 seconds |
| Started | Oct 09 10:17:28 AM UTC 24 |
| Finished | Oct 09 10:17:30 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055062182 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3055062182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/45.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/45.keymgr_custom_cm.1397279844 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 147422260 ps |
| CPU time | 2.83 seconds |
| Started | Oct 09 10:17:26 AM UTC 24 |
| Finished | Oct 09 10:17:30 AM UTC 24 |
| Peak memory | 226188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397279844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1397279844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/45.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/45.keymgr_direct_to_disabled.3899810621 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 26120513 ps |
| CPU time | 2.23 seconds |
| Started | Oct 09 10:17:24 AM UTC 24 |
| Finished | Oct 09 10:17:27 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899810621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3899810621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/45.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/45.keymgr_hwsw_invalid_input.3918419676 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 113569941 ps |
| CPU time | 3.45 seconds |
| Started | Oct 09 10:17:25 AM UTC 24 |
| Finished | Oct 09 10:17:29 AM UTC 24 |
| Peak memory | 223548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918419676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3918419676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/45.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/45.keymgr_kmac_rsp_err.14784613 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 129976717 ps |
| CPU time | 4.44 seconds |
| Started | Oct 09 10:17:25 AM UTC 24 |
| Finished | Oct 09 10:17:31 AM UTC 24 |
| Peak memory | 223504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14784613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.14784613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/45.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/45.keymgr_lc_disable.1053270273 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 681794177 ps |
| CPU time | 6.65 seconds |
| Started | Oct 09 10:17:24 AM UTC 24 |
| Finished | Oct 09 10:17:32 AM UTC 24 |
| Peak memory | 227832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053270273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1053270273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/45.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/45.keymgr_random.1834326251 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 658273520 ps |
| CPU time | 10.51 seconds |
| Started | Oct 09 10:17:24 AM UTC 24 |
| Finished | Oct 09 10:17:35 AM UTC 24 |
| Peak memory | 223480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834326251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1834326251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/45.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/45.keymgr_sideload.3394610134 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 5350065681 ps |
| CPU time | 38.37 seconds |
| Started | Oct 09 10:17:22 AM UTC 24 |
| Finished | Oct 09 10:18:02 AM UTC 24 |
| Peak memory | 217528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394610134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3394610134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/45.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_aes.353831823 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 777355415 ps |
| CPU time | 7.82 seconds |
| Started | Oct 09 10:17:23 AM UTC 24 |
| Finished | Oct 09 10:17:32 AM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353831823 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.353831823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/45.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_kmac.1888803760 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 100758382 ps |
| CPU time | 3.83 seconds |
| Started | Oct 09 10:17:23 AM UTC 24 |
| Finished | Oct 09 10:17:28 AM UTC 24 |
| Peak memory | 215536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888803760 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1888803760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/45.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_otbn.32078242 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 104585942 ps |
| CPU time | 3.48 seconds |
| Started | Oct 09 10:17:23 AM UTC 24 |
| Finished | Oct 09 10:17:28 AM UTC 24 |
| Peak memory | 215536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32078242 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.32078242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/45.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_protect.4070895819 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 98294393 ps |
| CPU time | 4.81 seconds |
| Started | Oct 09 10:17:26 AM UTC 24 |
| Finished | Oct 09 10:17:32 AM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070895819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.4070895819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/45.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/45.keymgr_smoke.3686579907 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 362803847 ps |
| CPU time | 5.42 seconds |
| Started | Oct 09 10:17:22 AM UTC 24 |
| Finished | Oct 09 10:17:29 AM UTC 24 |
| Peak memory | 215416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686579907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3686579907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/45.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all.2689560326 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 571488591 ps |
| CPU time | 27.15 seconds |
| Started | Oct 09 10:17:27 AM UTC 24 |
| Finished | Oct 09 10:17:56 AM UTC 24 |
| Peak memory | 230796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689560326 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2689560326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/45.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/45.keymgr_sw_invalid_input.1593956446 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 249127779 ps |
| CPU time | 11.09 seconds |
| Started | Oct 09 10:17:25 AM UTC 24 |
| Finished | Oct 09 10:17:37 AM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593956446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1593956446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/45.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/45.keymgr_sync_async_fault_cross.2765342515 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 130997412 ps |
| CPU time | 3.75 seconds |
| Started | Oct 09 10:17:26 AM UTC 24 |
| Finished | Oct 09 10:17:31 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765342515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2765342515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/45.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/46.keymgr_alert_test.3633277265 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 29642134 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 10:17:34 AM UTC 24 |
| Finished | Oct 09 10:17:36 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633277265 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3633277265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/46.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/46.keymgr_custom_cm.1579851651 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 235333171 ps |
| CPU time | 4.87 seconds |
| Started | Oct 09 10:17:33 AM UTC 24 |
| Finished | Oct 09 10:17:39 AM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579851651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1579851651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/46.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/46.keymgr_direct_to_disabled.1647491567 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 131473530 ps |
| CPU time | 3.94 seconds |
| Started | Oct 09 10:17:31 AM UTC 24 |
| Finished | Oct 09 10:17:36 AM UTC 24 |
| Peak memory | 219444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647491567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1647491567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/46.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/46.keymgr_hwsw_invalid_input.1152358335 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 162582487 ps |
| CPU time | 4.7 seconds |
| Started | Oct 09 10:17:33 AM UTC 24 |
| Finished | Oct 09 10:17:38 AM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152358335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1152358335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/46.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/46.keymgr_kmac_rsp_err.476949566 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 172539021 ps |
| CPU time | 3.72 seconds |
| Started | Oct 09 10:17:33 AM UTC 24 |
| Finished | Oct 09 10:17:37 AM UTC 24 |
| Peak memory | 223416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476949566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.476949566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/46.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/46.keymgr_lc_disable.3751529618 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 223861633 ps |
| CPU time | 3.78 seconds |
| Started | Oct 09 10:17:32 AM UTC 24 |
| Finished | Oct 09 10:17:37 AM UTC 24 |
| Peak memory | 217464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751529618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3751529618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/46.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/46.keymgr_random.3187411633 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 92623247 ps |
| CPU time | 5.02 seconds |
| Started | Oct 09 10:17:31 AM UTC 24 |
| Finished | Oct 09 10:17:37 AM UTC 24 |
| Peak memory | 217596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187411633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3187411633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/46.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/46.keymgr_sideload.2177439383 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 87151360 ps |
| CPU time | 2.66 seconds |
| Started | Oct 09 10:17:29 AM UTC 24 |
| Finished | Oct 09 10:17:32 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177439383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2177439383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/46.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_aes.879817420 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 255593831 ps |
| CPU time | 3.65 seconds |
| Started | Oct 09 10:17:30 AM UTC 24 |
| Finished | Oct 09 10:17:35 AM UTC 24 |
| Peak memory | 215232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879817420 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.879817420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/46.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_kmac.575598225 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 67444734 ps |
| CPU time | 2.78 seconds |
| Started | Oct 09 10:17:29 AM UTC 24 |
| Finished | Oct 09 10:17:33 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575598225 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.575598225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/46.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_otbn.3161536528 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 74784540 ps |
| CPU time | 2.3 seconds |
| Started | Oct 09 10:17:30 AM UTC 24 |
| Finished | Oct 09 10:17:33 AM UTC 24 |
| Peak memory | 215588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161536528 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3161536528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/46.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_protect.421691824 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 113479420 ps |
| CPU time | 3.75 seconds |
| Started | Oct 09 10:17:34 AM UTC 24 |
| Finished | Oct 09 10:17:39 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421691824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.421691824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/46.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/46.keymgr_smoke.938137932 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 53106476 ps |
| CPU time | 3.39 seconds |
| Started | Oct 09 10:17:29 AM UTC 24 |
| Finished | Oct 09 10:17:33 AM UTC 24 |
| Peak memory | 215296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938137932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.938137932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/46.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all.3271907164 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 6553899043 ps |
| CPU time | 49.26 seconds |
| Started | Oct 09 10:17:34 AM UTC 24 |
| Finished | Oct 09 10:18:25 AM UTC 24 |
| Peak memory | 225720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271907164 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3271907164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/46.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all_with_rand_reset.1811935865 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 2253998148 ps |
| CPU time | 27.95 seconds |
| Started | Oct 09 10:17:34 AM UTC 24 |
| Finished | Oct 09 10:18:03 AM UTC 24 |
| Peak memory | 231724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1811935865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymg r_stress_all_with_rand_reset.1811935865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/46.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/46.keymgr_sw_invalid_input.2303594423 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 15581674199 ps |
| CPU time | 41.22 seconds |
| Started | Oct 09 10:17:33 AM UTC 24 |
| Finished | Oct 09 10:18:15 AM UTC 24 |
| Peak memory | 227784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303594423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2303594423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/46.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/46.keymgr_sync_async_fault_cross.1953395572 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 209786108 ps |
| CPU time | 3.41 seconds |
| Started | Oct 09 10:17:34 AM UTC 24 |
| Finished | Oct 09 10:17:38 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953395572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1953395572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/46.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/47.keymgr_alert_test.2851509038 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 31158188 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 10:17:40 AM UTC 24 |
| Finished | Oct 09 10:17:42 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851509038 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2851509038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/47.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/47.keymgr_cfg_regwen.4035392159 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 171824064 ps |
| CPU time | 9.85 seconds |
| Started | Oct 09 10:17:38 AM UTC 24 |
| Finished | Oct 09 10:17:49 AM UTC 24 |
| Peak memory | 223468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035392159 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.4035392159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/47.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/47.keymgr_custom_cm.2798508354 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 164251623 ps |
| CPU time | 4.22 seconds |
| Started | Oct 09 10:17:39 AM UTC 24 |
| Finished | Oct 09 10:17:45 AM UTC 24 |
| Peak memory | 223876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798508354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2798508354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/47.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/47.keymgr_direct_to_disabled.2359395903 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 342007740 ps |
| CPU time | 4.81 seconds |
| Started | Oct 09 10:17:38 AM UTC 24 |
| Finished | Oct 09 10:17:44 AM UTC 24 |
| Peak memory | 227560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359395903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2359395903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/47.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/47.keymgr_hwsw_invalid_input.3952832040 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 55884989 ps |
| CPU time | 4.41 seconds |
| Started | Oct 09 10:17:38 AM UTC 24 |
| Finished | Oct 09 10:17:44 AM UTC 24 |
| Peak memory | 217320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952832040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3952832040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/47.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/47.keymgr_kmac_rsp_err.3525662690 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 63119169 ps |
| CPU time | 3.05 seconds |
| Started | Oct 09 10:17:38 AM UTC 24 |
| Finished | Oct 09 10:17:42 AM UTC 24 |
| Peak memory | 229928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525662690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3525662690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/47.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/47.keymgr_lc_disable.1180215479 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 367216255 ps |
| CPU time | 4.11 seconds |
| Started | Oct 09 10:17:38 AM UTC 24 |
| Finished | Oct 09 10:17:43 AM UTC 24 |
| Peak memory | 217540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180215479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1180215479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/47.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/47.keymgr_random.1325301273 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 341197888 ps |
| CPU time | 6.97 seconds |
| Started | Oct 09 10:17:38 AM UTC 24 |
| Finished | Oct 09 10:17:46 AM UTC 24 |
| Peak memory | 229644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325301273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1325301273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/47.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/47.keymgr_sideload.3524227910 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 54792077 ps |
| CPU time | 3.51 seconds |
| Started | Oct 09 10:17:34 AM UTC 24 |
| Finished | Oct 09 10:17:39 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524227910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3524227910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/47.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_aes.1933004323 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 3333761794 ps |
| CPU time | 22.24 seconds |
| Started | Oct 09 10:17:37 AM UTC 24 |
| Finished | Oct 09 10:18:00 AM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933004323 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1933004323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/47.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_kmac.17573489 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 381617492 ps |
| CPU time | 6.28 seconds |
| Started | Oct 09 10:17:35 AM UTC 24 |
| Finished | Oct 09 10:17:43 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17573489 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.17573489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/47.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_otbn.3907170234 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 769629635 ps |
| CPU time | 8.52 seconds |
| Started | Oct 09 10:17:37 AM UTC 24 |
| Finished | Oct 09 10:17:46 AM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907170234 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3907170234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/47.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_protect.3114132984 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 740914517 ps |
| CPU time | 8.28 seconds |
| Started | Oct 09 10:17:39 AM UTC 24 |
| Finished | Oct 09 10:17:49 AM UTC 24 |
| Peak memory | 227892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114132984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3114132984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/47.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/47.keymgr_smoke.1092350629 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 110569788 ps |
| CPU time | 2.73 seconds |
| Started | Oct 09 10:17:34 AM UTC 24 |
| Finished | Oct 09 10:17:38 AM UTC 24 |
| Peak memory | 217264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092350629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1092350629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/47.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all.1388151358 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 6876148190 ps |
| CPU time | 81.33 seconds |
| Started | Oct 09 10:17:40 AM UTC 24 |
| Finished | Oct 09 10:19:03 AM UTC 24 |
| Peak memory | 231688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388151358 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1388151358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/47.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all_with_rand_reset.1494317653 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 1272244669 ps |
| CPU time | 29.26 seconds |
| Started | Oct 09 10:17:40 AM UTC 24 |
| Finished | Oct 09 10:18:10 AM UTC 24 |
| Peak memory | 231652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1494317653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymg r_stress_all_with_rand_reset.1494317653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/47.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/47.keymgr_sw_invalid_input.3464596358 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 499029553 ps |
| CPU time | 5.59 seconds |
| Started | Oct 09 10:17:38 AM UTC 24 |
| Finished | Oct 09 10:17:45 AM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464596358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3464596358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/47.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/48.keymgr_alert_test.2685353513 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 36416462 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 10:17:48 AM UTC 24 |
| Finished | Oct 09 10:17:51 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685353513 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2685353513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/48.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/48.keymgr_cfg_regwen.3558101953 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 39063443 ps |
| CPU time | 4.16 seconds |
| Started | Oct 09 10:17:44 AM UTC 24 |
| Finished | Oct 09 10:17:50 AM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558101953 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3558101953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/48.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/48.keymgr_custom_cm.1878723112 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 110650094 ps |
| CPU time | 3.17 seconds |
| Started | Oct 09 10:17:47 AM UTC 24 |
| Finished | Oct 09 10:17:51 AM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878723112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1878723112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/48.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/48.keymgr_direct_to_disabled.2863544590 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 94107633 ps |
| CPU time | 2.46 seconds |
| Started | Oct 09 10:17:44 AM UTC 24 |
| Finished | Oct 09 10:17:48 AM UTC 24 |
| Peak memory | 223496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863544590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2863544590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/48.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/48.keymgr_hwsw_invalid_input.1074741599 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 361984852 ps |
| CPU time | 5.94 seconds |
| Started | Oct 09 10:17:46 AM UTC 24 |
| Finished | Oct 09 10:17:53 AM UTC 24 |
| Peak memory | 231456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074741599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1074741599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/48.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/48.keymgr_lc_disable.1158239072 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 182552852 ps |
| CPU time | 3.29 seconds |
| Started | Oct 09 10:17:46 AM UTC 24 |
| Finished | Oct 09 10:17:50 AM UTC 24 |
| Peak memory | 231636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158239072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1158239072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/48.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/48.keymgr_random.3335018530 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 450561480 ps |
| CPU time | 11.71 seconds |
| Started | Oct 09 10:17:44 AM UTC 24 |
| Finished | Oct 09 10:17:57 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335018530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3335018530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/48.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/48.keymgr_sideload.1107374086 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 607476336 ps |
| CPU time | 9.4 seconds |
| Started | Oct 09 10:17:43 AM UTC 24 |
| Finished | Oct 09 10:17:54 AM UTC 24 |
| Peak memory | 217668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107374086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1107374086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/48.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_aes.604390481 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 1057617611 ps |
| CPU time | 12.49 seconds |
| Started | Oct 09 10:17:43 AM UTC 24 |
| Finished | Oct 09 10:17:57 AM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604390481 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.604390481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/48.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_kmac.347582256 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 142407872 ps |
| CPU time | 2.42 seconds |
| Started | Oct 09 10:17:43 AM UTC 24 |
| Finished | Oct 09 10:17:47 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347582256 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.347582256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/48.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_otbn.3331518274 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 475909696 ps |
| CPU time | 3.45 seconds |
| Started | Oct 09 10:17:44 AM UTC 24 |
| Finished | Oct 09 10:17:49 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331518274 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3331518274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/48.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_protect.3768527528 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 53028665 ps |
| CPU time | 2.21 seconds |
| Started | Oct 09 10:17:47 AM UTC 24 |
| Finished | Oct 09 10:17:50 AM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768527528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3768527528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/48.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/48.keymgr_smoke.594629965 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 125515361 ps |
| CPU time | 5.65 seconds |
| Started | Oct 09 10:17:41 AM UTC 24 |
| Finished | Oct 09 10:17:48 AM UTC 24 |
| Peak memory | 217356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594629965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.594629965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/48.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all.4197890647 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 1771092420 ps |
| CPU time | 17.74 seconds |
| Started | Oct 09 10:17:48 AM UTC 24 |
| Finished | Oct 09 10:18:07 AM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197890647 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.4197890647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/48.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all_with_rand_reset.36262765 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 446209009 ps |
| CPU time | 27.98 seconds |
| Started | Oct 09 10:17:48 AM UTC 24 |
| Finished | Oct 09 10:18:18 AM UTC 24 |
| Peak memory | 231672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=36262765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_ stress_all_with_rand_reset.36262765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/48.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/48.keymgr_sw_invalid_input.3437051808 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 111853821 ps |
| CPU time | 5.62 seconds |
| Started | Oct 09 10:17:46 AM UTC 24 |
| Finished | Oct 09 10:17:52 AM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437051808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3437051808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/48.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/48.keymgr_sync_async_fault_cross.2409932683 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1183443116 ps |
| CPU time | 2.13 seconds |
| Started | Oct 09 10:17:47 AM UTC 24 |
| Finished | Oct 09 10:17:50 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409932683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.2409932683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/48.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/49.keymgr_alert_test.4293612488 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 23737051 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 10:17:55 AM UTC 24 |
| Finished | Oct 09 10:17:57 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293612488 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.4293612488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/49.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/49.keymgr_cfg_regwen.1363125068 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 158902234 ps |
| CPU time | 11.03 seconds |
| Started | Oct 09 10:17:51 AM UTC 24 |
| Finished | Oct 09 10:18:03 AM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363125068 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1363125068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/49.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/49.keymgr_custom_cm.693976506 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 51913732 ps |
| CPU time | 2.44 seconds |
| Started | Oct 09 10:17:53 AM UTC 24 |
| Finished | Oct 09 10:17:57 AM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693976506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.693976506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/49.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/49.keymgr_direct_to_disabled.2132135260 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 316251959 ps |
| CPU time | 2.35 seconds |
| Started | Oct 09 10:17:51 AM UTC 24 |
| Finished | Oct 09 10:17:54 AM UTC 24 |
| Peak memory | 223468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132135260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2132135260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/49.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/49.keymgr_kmac_rsp_err.1153896765 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 1481067414 ps |
| CPU time | 6.99 seconds |
| Started | Oct 09 10:17:53 AM UTC 24 |
| Finished | Oct 09 10:18:01 AM UTC 24 |
| Peak memory | 231500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153896765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1153896765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/49.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/49.keymgr_lc_disable.1950693333 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 41716565 ps |
| CPU time | 2.94 seconds |
| Started | Oct 09 10:17:51 AM UTC 24 |
| Finished | Oct 09 10:17:55 AM UTC 24 |
| Peak memory | 215608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950693333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1950693333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/49.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/49.keymgr_random.3159232008 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 193308156 ps |
| CPU time | 7.45 seconds |
| Started | Oct 09 10:17:51 AM UTC 24 |
| Finished | Oct 09 10:18:00 AM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159232008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3159232008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/49.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/49.keymgr_sideload.963625877 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 75655809 ps |
| CPU time | 2.61 seconds |
| Started | Oct 09 10:17:50 AM UTC 24 |
| Finished | Oct 09 10:17:53 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963625877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.963625877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/49.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_aes.1511831200 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 37357605 ps |
| CPU time | 3.12 seconds |
| Started | Oct 09 10:17:50 AM UTC 24 |
| Finished | Oct 09 10:17:54 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511831200 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1511831200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/49.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_kmac.306366203 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 62271499 ps |
| CPU time | 3.06 seconds |
| Started | Oct 09 10:17:50 AM UTC 24 |
| Finished | Oct 09 10:17:54 AM UTC 24 |
| Peak memory | 215600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306366203 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.306366203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/49.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_otbn.287475382 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 119748301 ps |
| CPU time | 2.7 seconds |
| Started | Oct 09 10:17:50 AM UTC 24 |
| Finished | Oct 09 10:17:54 AM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287475382 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.287475382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/49.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/49.keymgr_smoke.1252392457 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 118255137 ps |
| CPU time | 2.97 seconds |
| Started | Oct 09 10:17:49 AM UTC 24 |
| Finished | Oct 09 10:17:53 AM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252392457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1252392457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/49.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all.1922493043 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 671656038 ps |
| CPU time | 30 seconds |
| Started | Oct 09 10:17:55 AM UTC 24 |
| Finished | Oct 09 10:18:26 AM UTC 24 |
| Peak memory | 231612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922493043 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1922493043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/49.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all_with_rand_reset.2827537068 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 1671381904 ps |
| CPU time | 18.09 seconds |
| Started | Oct 09 10:17:55 AM UTC 24 |
| Finished | Oct 09 10:18:14 AM UTC 24 |
| Peak memory | 231932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2827537068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymg r_stress_all_with_rand_reset.2827537068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/49.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/49.keymgr_sw_invalid_input.1036333401 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 219938002 ps |
| CPU time | 8.54 seconds |
| Started | Oct 09 10:17:51 AM UTC 24 |
| Finished | Oct 09 10:18:01 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036333401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1036333401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/49.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/49.keymgr_sync_async_fault_cross.2315148837 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 593123938 ps |
| CPU time | 6.66 seconds |
| Started | Oct 09 10:17:55 AM UTC 24 |
| Finished | Oct 09 10:18:03 AM UTC 24 |
| Peak memory | 219640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315148837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2315148837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/49.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/5.keymgr_alert_test.2234400340 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 12355002 ps |
| CPU time | 0.99 seconds |
| Started | Oct 09 10:12:07 AM UTC 24 |
| Finished | Oct 09 10:12:09 AM UTC 24 |
| Peak memory | 212848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234400340 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2234400340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/5.keymgr_cfg_regwen.1249364056 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 65341956 ps |
| CPU time | 3.75 seconds |
| Started | Oct 09 10:12:02 AM UTC 24 |
| Finished | Oct 09 10:12:06 AM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249364056 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1249364056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/5.keymgr_direct_to_disabled.4127406382 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 2130878188 ps |
| CPU time | 16.72 seconds |
| Started | Oct 09 10:12:03 AM UTC 24 |
| Finished | Oct 09 10:12:21 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127406382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.4127406382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/5.keymgr_hwsw_invalid_input.3190779561 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 293039358 ps |
| CPU time | 2.67 seconds |
| Started | Oct 09 10:12:04 AM UTC 24 |
| Finished | Oct 09 10:12:08 AM UTC 24 |
| Peak memory | 231468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190779561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3190779561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/5.keymgr_lc_disable.268863692 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 138434259 ps |
| CPU time | 3.86 seconds |
| Started | Oct 09 10:12:03 AM UTC 24 |
| Finished | Oct 09 10:12:08 AM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268863692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.268863692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/5.keymgr_random.1190144354 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 61654761 ps |
| CPU time | 3.58 seconds |
| Started | Oct 09 10:12:02 AM UTC 24 |
| Finished | Oct 09 10:12:06 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190144354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1190144354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/5.keymgr_sideload.1618551847 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 212860977 ps |
| CPU time | 3.14 seconds |
| Started | Oct 09 10:12:00 AM UTC 24 |
| Finished | Oct 09 10:12:05 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618551847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1618551847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_aes.2726006766 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1302958118 ps |
| CPU time | 9.53 seconds |
| Started | Oct 09 10:12:00 AM UTC 24 |
| Finished | Oct 09 10:12:11 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726006766 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2726006766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_kmac.2677604095 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 95980869 ps |
| CPU time | 3.29 seconds |
| Started | Oct 09 10:12:00 AM UTC 24 |
| Finished | Oct 09 10:12:05 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677604095 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2677604095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_otbn.1558141584 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 113667270 ps |
| CPU time | 5.19 seconds |
| Started | Oct 09 10:12:01 AM UTC 24 |
| Finished | Oct 09 10:12:08 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558141584 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1558141584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_protect.1203111571 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 169326469 ps |
| CPU time | 3.22 seconds |
| Started | Oct 09 10:12:05 AM UTC 24 |
| Finished | Oct 09 10:12:10 AM UTC 24 |
| Peak memory | 227568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203111571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1203111571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/5.keymgr_smoke.1739449021 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 139814074 ps |
| CPU time | 4.32 seconds |
| Started | Oct 09 10:12:00 AM UTC 24 |
| Finished | Oct 09 10:12:06 AM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739449021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1739449021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all.3072541725 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 6154793913 ps |
| CPU time | 37.37 seconds |
| Started | Oct 09 10:12:05 AM UTC 24 |
| Finished | Oct 09 10:12:44 AM UTC 24 |
| Peak memory | 217456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072541725 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3072541725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/5.keymgr_sw_invalid_input.2976038452 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 822452097 ps |
| CPU time | 26.61 seconds |
| Started | Oct 09 10:12:03 AM UTC 24 |
| Finished | Oct 09 10:12:31 AM UTC 24 |
| Peak memory | 217320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976038452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2976038452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/5.keymgr_sync_async_fault_cross.1701811047 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 103324620 ps |
| CPU time | 3.79 seconds |
| Started | Oct 09 10:12:05 AM UTC 24 |
| Finished | Oct 09 10:12:10 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701811047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1701811047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/6.keymgr_alert_test.3678955477 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 87965597 ps |
| CPU time | 1.29 seconds |
| Started | Oct 09 10:12:14 AM UTC 24 |
| Finished | Oct 09 10:12:17 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678955477 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3678955477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/6.keymgr_cfg_regwen.3061431061 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 45286206 ps |
| CPU time | 3.66 seconds |
| Started | Oct 09 10:12:10 AM UTC 24 |
| Finished | Oct 09 10:12:15 AM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061431061 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3061431061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/6.keymgr_custom_cm.2179887302 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 760819801 ps |
| CPU time | 4.97 seconds |
| Started | Oct 09 10:12:12 AM UTC 24 |
| Finished | Oct 09 10:12:18 AM UTC 24 |
| Peak memory | 231848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179887302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2179887302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/6.keymgr_direct_to_disabled.3173453712 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 680692702 ps |
| CPU time | 5.64 seconds |
| Started | Oct 09 10:12:10 AM UTC 24 |
| Finished | Oct 09 10:12:17 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173453712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3173453712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/6.keymgr_hwsw_invalid_input.3741878363 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 189456256 ps |
| CPU time | 2.73 seconds |
| Started | Oct 09 10:12:12 AM UTC 24 |
| Finished | Oct 09 10:12:15 AM UTC 24 |
| Peak memory | 223548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741878363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3741878363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/6.keymgr_kmac_rsp_err.1837316239 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 86867630 ps |
| CPU time | 4.96 seconds |
| Started | Oct 09 10:12:12 AM UTC 24 |
| Finished | Oct 09 10:12:18 AM UTC 24 |
| Peak memory | 223676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837316239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1837316239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/6.keymgr_lc_disable.1862980050 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 30669303 ps |
| CPU time | 2.76 seconds |
| Started | Oct 09 10:12:10 AM UTC 24 |
| Finished | Oct 09 10:12:14 AM UTC 24 |
| Peak memory | 225596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862980050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1862980050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/6.keymgr_random.1552943795 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1196760092 ps |
| CPU time | 29.43 seconds |
| Started | Oct 09 10:12:10 AM UTC 24 |
| Finished | Oct 09 10:12:41 AM UTC 24 |
| Peak memory | 227712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552943795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1552943795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/6.keymgr_sideload.1784736822 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 27420678 ps |
| CPU time | 2.35 seconds |
| Started | Oct 09 10:12:08 AM UTC 24 |
| Finished | Oct 09 10:12:11 AM UTC 24 |
| Peak memory | 217668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784736822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1784736822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_aes.2916660569 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 536905450 ps |
| CPU time | 13.59 seconds |
| Started | Oct 09 10:12:09 AM UTC 24 |
| Finished | Oct 09 10:12:24 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916660569 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2916660569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_kmac.1659992914 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 261370292 ps |
| CPU time | 5.57 seconds |
| Started | Oct 09 10:12:09 AM UTC 24 |
| Finished | Oct 09 10:12:16 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659992914 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1659992914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_otbn.1696979215 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 101783861 ps |
| CPU time | 3.86 seconds |
| Started | Oct 09 10:12:09 AM UTC 24 |
| Finished | Oct 09 10:12:14 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696979215 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1696979215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_protect.3573411533 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 279721072 ps |
| CPU time | 4.31 seconds |
| Started | Oct 09 10:12:12 AM UTC 24 |
| Finished | Oct 09 10:12:17 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573411533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3573411533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/6.keymgr_smoke.3248245470 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 278767022 ps |
| CPU time | 4.49 seconds |
| Started | Oct 09 10:12:07 AM UTC 24 |
| Finished | Oct 09 10:12:12 AM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248245470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3248245470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all.3152815129 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 535131755 ps |
| CPU time | 5.39 seconds |
| Started | Oct 09 10:12:13 AM UTC 24 |
| Finished | Oct 09 10:12:20 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152815129 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3152815129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/6.keymgr_sw_invalid_input.1012211787 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 304307612 ps |
| CPU time | 5.82 seconds |
| Started | Oct 09 10:12:12 AM UTC 24 |
| Finished | Oct 09 10:12:18 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012211787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1012211787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/6.keymgr_sync_async_fault_cross.1385389910 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 88849214 ps |
| CPU time | 3.11 seconds |
| Started | Oct 09 10:12:13 AM UTC 24 |
| Finished | Oct 09 10:12:17 AM UTC 24 |
| Peak memory | 217404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385389910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1385389910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/6.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/7.keymgr_alert_test.3081723068 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 9954053 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 10:12:23 AM UTC 24 |
| Finished | Oct 09 10:12:25 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081723068 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3081723068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/7.keymgr_custom_cm.3068431551 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1167499844 ps |
| CPU time | 6.25 seconds |
| Started | Oct 09 10:12:19 AM UTC 24 |
| Finished | Oct 09 10:12:27 AM UTC 24 |
| Peak memory | 227904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068431551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3068431551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/7.keymgr_direct_to_disabled.3586214574 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 8045817507 ps |
| CPU time | 37.44 seconds |
| Started | Oct 09 10:12:18 AM UTC 24 |
| Finished | Oct 09 10:12:57 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586214574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3586214574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/7.keymgr_hwsw_invalid_input.2591984297 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 3569768125 ps |
| CPU time | 35 seconds |
| Started | Oct 09 10:12:19 AM UTC 24 |
| Finished | Oct 09 10:12:56 AM UTC 24 |
| Peak memory | 223528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591984297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2591984297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/7.keymgr_lc_disable.120347612 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 468355769 ps |
| CPU time | 4.23 seconds |
| Started | Oct 09 10:12:18 AM UTC 24 |
| Finished | Oct 09 10:12:23 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120347612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.120347612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/7.keymgr_random.3676490778 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 64400131 ps |
| CPU time | 5.57 seconds |
| Started | Oct 09 10:12:17 AM UTC 24 |
| Finished | Oct 09 10:12:23 AM UTC 24 |
| Peak memory | 227904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676490778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3676490778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/7.keymgr_sideload.473048615 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 793662762 ps |
| CPU time | 38.13 seconds |
| Started | Oct 09 10:12:15 AM UTC 24 |
| Finished | Oct 09 10:12:55 AM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473048615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.473048615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_aes.252208188 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 51520838 ps |
| CPU time | 2.83 seconds |
| Started | Oct 09 10:12:16 AM UTC 24 |
| Finished | Oct 09 10:12:20 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252208188 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.252208188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_kmac.561072452 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 186233173 ps |
| CPU time | 5.08 seconds |
| Started | Oct 09 10:12:16 AM UTC 24 |
| Finished | Oct 09 10:12:22 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561072452 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.561072452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_otbn.2284082394 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 19201970420 ps |
| CPU time | 69.26 seconds |
| Started | Oct 09 10:12:17 AM UTC 24 |
| Finished | Oct 09 10:13:28 AM UTC 24 |
| Peak memory | 217452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284082394 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2284082394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_protect.471898173 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 343056252 ps |
| CPU time | 5.39 seconds |
| Started | Oct 09 10:12:20 AM UTC 24 |
| Finished | Oct 09 10:12:27 AM UTC 24 |
| Peak memory | 223460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471898173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.471898173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/7.keymgr_smoke.3196989067 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 158026792 ps |
| CPU time | 6.32 seconds |
| Started | Oct 09 10:12:14 AM UTC 24 |
| Finished | Oct 09 10:12:22 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196989067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3196989067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/7.keymgr_sw_invalid_input.2494765250 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 177947531 ps |
| CPU time | 4.05 seconds |
| Started | Oct 09 10:12:18 AM UTC 24 |
| Finished | Oct 09 10:12:23 AM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494765250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2494765250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/7.keymgr_sync_async_fault_cross.2985451218 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 108717737 ps |
| CPU time | 4.02 seconds |
| Started | Oct 09 10:12:21 AM UTC 24 |
| Finished | Oct 09 10:12:26 AM UTC 24 |
| Peak memory | 219520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985451218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2985451218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/7.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/8.keymgr_alert_test.3894864160 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 29351692 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 10:12:32 AM UTC 24 |
| Finished | Oct 09 10:12:35 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894864160 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3894864160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/8.keymgr_cfg_regwen.1751089515 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 674564748 ps |
| CPU time | 11.53 seconds |
| Started | Oct 09 10:12:26 AM UTC 24 |
| Finished | Oct 09 10:12:39 AM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751089515 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1751089515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/8.keymgr_direct_to_disabled.2296832473 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 54367673 ps |
| CPU time | 3.49 seconds |
| Started | Oct 09 10:12:27 AM UTC 24 |
| Finished | Oct 09 10:12:31 AM UTC 24 |
| Peak memory | 217320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296832473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2296832473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/8.keymgr_kmac_rsp_err.1477461691 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 153170965 ps |
| CPU time | 3.5 seconds |
| Started | Oct 09 10:12:29 AM UTC 24 |
| Finished | Oct 09 10:12:33 AM UTC 24 |
| Peak memory | 223624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477461691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1477461691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/8.keymgr_lc_disable.1434423189 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 226331684 ps |
| CPU time | 6.71 seconds |
| Started | Oct 09 10:12:28 AM UTC 24 |
| Finished | Oct 09 10:12:35 AM UTC 24 |
| Peak memory | 219448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434423189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1434423189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/8.keymgr_random.1444427832 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 299364172 ps |
| CPU time | 4.67 seconds |
| Started | Oct 09 10:12:25 AM UTC 24 |
| Finished | Oct 09 10:12:31 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444427832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1444427832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/8.keymgr_sideload.340494857 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 45351551 ps |
| CPU time | 2.66 seconds |
| Started | Oct 09 10:12:24 AM UTC 24 |
| Finished | Oct 09 10:12:28 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340494857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.340494857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_aes.3258701897 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 46405519 ps |
| CPU time | 3.1 seconds |
| Started | Oct 09 10:12:24 AM UTC 24 |
| Finished | Oct 09 10:12:28 AM UTC 24 |
| Peak memory | 217664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258701897 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3258701897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_otbn.2037508047 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 525148332 ps |
| CPU time | 3.29 seconds |
| Started | Oct 09 10:12:25 AM UTC 24 |
| Finished | Oct 09 10:12:30 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037508047 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2037508047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_protect.3525699222 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 21484832 ps |
| CPU time | 1.98 seconds |
| Started | Oct 09 10:12:30 AM UTC 24 |
| Finished | Oct 09 10:12:33 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525699222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3525699222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/8.keymgr_smoke.3658573729 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 5555524330 ps |
| CPU time | 46.51 seconds |
| Started | Oct 09 10:12:23 AM UTC 24 |
| Finished | Oct 09 10:13:11 AM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658573729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3658573729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/8.keymgr_sw_invalid_input.1628692054 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 132523024 ps |
| CPU time | 6.51 seconds |
| Started | Oct 09 10:12:28 AM UTC 24 |
| Finished | Oct 09 10:12:35 AM UTC 24 |
| Peak memory | 223492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628692054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1628692054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/8.keymgr_sync_async_fault_cross.252057847 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 93251576 ps |
| CPU time | 2.5 seconds |
| Started | Oct 09 10:12:31 AM UTC 24 |
| Finished | Oct 09 10:12:35 AM UTC 24 |
| Peak memory | 217404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252057847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.252057847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/8.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/9.keymgr_alert_test.2310868419 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 21155097 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 10:12:45 AM UTC 24 |
| Finished | Oct 09 10:12:47 AM UTC 24 |
| Peak memory | 212840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310868419 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2310868419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/9.keymgr_cfg_regwen.2969338504 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 2217965522 ps |
| CPU time | 30.99 seconds |
| Started | Oct 09 10:12:37 AM UTC 24 |
| Finished | Oct 09 10:13:09 AM UTC 24 |
| Peak memory | 225580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969338504 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2969338504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/9.keymgr_direct_to_disabled.536266481 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 150547202 ps |
| CPU time | 3.25 seconds |
| Started | Oct 09 10:12:37 AM UTC 24 |
| Finished | Oct 09 10:12:41 AM UTC 24 |
| Peak memory | 215416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536266481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.536266481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/9.keymgr_hwsw_invalid_input.3550698170 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 153520352 ps |
| CPU time | 6.2 seconds |
| Started | Oct 09 10:12:40 AM UTC 24 |
| Finished | Oct 09 10:12:48 AM UTC 24 |
| Peak memory | 223564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550698170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3550698170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/9.keymgr_kmac_rsp_err.1734912858 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 429581280 ps |
| CPU time | 5.1 seconds |
| Started | Oct 09 10:12:42 AM UTC 24 |
| Finished | Oct 09 10:12:48 AM UTC 24 |
| Peak memory | 231564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734912858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1734912858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/9.keymgr_lc_disable.3532989905 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 129336257 ps |
| CPU time | 6.47 seconds |
| Started | Oct 09 10:12:38 AM UTC 24 |
| Finished | Oct 09 10:12:46 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532989905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3532989905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/9.keymgr_random.4276707201 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 212426867 ps |
| CPU time | 5.12 seconds |
| Started | Oct 09 10:12:37 AM UTC 24 |
| Finished | Oct 09 10:12:43 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276707201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.4276707201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/9.keymgr_sideload.1675352659 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 141938792 ps |
| CPU time | 5.28 seconds |
| Started | Oct 09 10:12:35 AM UTC 24 |
| Finished | Oct 09 10:12:41 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675352659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1675352659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_aes.3429828729 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 719646259 ps |
| CPU time | 21.62 seconds |
| Started | Oct 09 10:12:36 AM UTC 24 |
| Finished | Oct 09 10:12:59 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429828729 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3429828729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_kmac.3417050603 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 176686422 ps |
| CPU time | 5.87 seconds |
| Started | Oct 09 10:12:36 AM UTC 24 |
| Finished | Oct 09 10:12:43 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417050603 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3417050603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_otbn.2775242092 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 157925366 ps |
| CPU time | 7.61 seconds |
| Started | Oct 09 10:12:36 AM UTC 24 |
| Finished | Oct 09 10:12:45 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775242092 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2775242092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_protect.1723426438 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 192819033 ps |
| CPU time | 3.86 seconds |
| Started | Oct 09 10:12:43 AM UTC 24 |
| Finished | Oct 09 10:12:48 AM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723426438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1723426438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/9.keymgr_smoke.244877306 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 126718110 ps |
| CPU time | 4.04 seconds |
| Started | Oct 09 10:12:34 AM UTC 24 |
| Finished | Oct 09 10:12:39 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244877306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.244877306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all.1434498394 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 13195809745 ps |
| CPU time | 93.96 seconds |
| Started | Oct 09 10:12:44 AM UTC 24 |
| Finished | Oct 09 10:14:20 AM UTC 24 |
| Peak memory | 231932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434498394 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1434498394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/9.keymgr_sw_invalid_input.2580334875 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 1349755563 ps |
| CPU time | 18.02 seconds |
| Started | Oct 09 10:12:39 AM UTC 24 |
| Finished | Oct 09 10:12:59 AM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580334875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2580334875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/coverage/default/9.keymgr_sync_async_fault_cross.1622522995 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 173162970 ps |
| CPU time | 4.97 seconds |
| Started | Oct 09 10:12:44 AM UTC 24 |
| Finished | Oct 09 10:12:50 AM UTC 24 |
| Peak memory | 219376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622522995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1622522995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/9.keymgr_sync_async_fault_cross/latest |
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