Module Definition
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Module Instance : tb.dut.u_ctrl.u_data_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.78 96.67 33.33 100.00 88.89 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.15 97.44 33.33 100.00 90.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : keymgr_data_en_state
Line No.TotalCoveredPercent
TOTAL302996.67
ALWAYS6933100.00
ALWAYS79272696.30

68 // SEC_CM: DATA.FSM.SPARSE 69 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StCtrlDataIdle) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StCtrlDataIdle): 69.1 `ifdef SIMULATION 69.2 prim_sparse_fsm_flop #( 69.3 .StateEnumT(state_e), 69.4 .Width($bits(state_e)), 69.5 .ResetValue($bits(state_e)'(StCtrlDataIdle)), 69.6 .EnableAlertTriggerSVA(1), 69.7 .CustomForceName("state_q") 69.8 ) u_state_regs ( 69.9 .clk_i ( clk_i ), 69.10 .rst_ni ( rst_ni ), 69.11 .state_i ( state_d ), 69.12 .state_o ( ) 69.13 ); 69.14 always_ff @(posedge clk_i or negedge rst_ni) begin 69.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  69.16 1/1 state_q <= StCtrlDataIdle; Tests: T1 T2 T3  69.17 end else begin 69.18 1/1 state_q <= state_d; Tests: T1 T2 T3  69.19 end 69.20 end 69.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 69.22 else begin 69.23 `ifdef UVM 69.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 69.25 "../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_data_en_state.sv", 69, "", 1); 69.26 `else 69.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 69.28 `PRIM_STRINGIFY(u_state_regs_A)); 69.29 `endif 69.30 end 69.31 `else 69.32 prim_sparse_fsm_flop #( 69.33 .StateEnumT(state_e), 69.34 .Width($bits(state_e)), 69.35 .ResetValue($bits(state_e)'(StCtrlDataIdle)), 69.36 .EnableAlertTriggerSVA(1) 69.37 ) u_state_regs ( 69.38 .clk_i ( `PRIM_FLOP_CLK ), 69.39 .rst_ni ( `PRIM_FLOP_RST ), 69.40 .state_i ( state_d ), 69.41 .state_o ( state_q ) 69.42 ); 69.43 `endif70 71 // The below control path is used for modulating the datapath to sideload and sw keys. 72 // This path is separate from the data_valid_o path, thus creating two separate attack points. 73 // The data is only enabled when a non-advance operation is invoked. 74 // When an advance operation is called, the data is disabled. It will stay disabled until an 75 // entire completion sequence is seen (op_done_o assert -> start_i de-assertion). 76 // When a generate operation is called, the data is enabled. However, any indication of this 77 // supposedly being an advance call will force the path to disable again. 78 always_comb begin 79 1/1 state_d = state_q; Tests: T1 T2 T3  80 1/1 fsm_err_o = 1'b0; Tests: T1 T2 T3  81 1/1 data_hw_en_o = 1'b0; Tests: T1 T2 T3  82 1/1 data_sw_en_o = 1'b0; Tests: T1 T2 T3  83 1/1 unique case (state_q) Tests: T1 T2 T3  84 85 StCtrlDataIdle: begin 86 1/1 if (adv_en_i) begin Tests: T1 T2 T3  87 1/1 state_d = StCtrlDataDis; Tests: T1 T2 T3  88 1/1 end else if ((id_en_i || gen_en_i) && mubi4_test_true_strict(hw_sel_i)) begin Tests: T1 T2 T3  89 1/1 state_d = StCtrlDataHwEn; Tests: T1 T3 T4  90 1/1 end else if ((id_en_i || gen_en_i) && mubi4_test_false_strict(hw_sel_i)) begin Tests: T1 T2 T3  91 1/1 state_d = StCtrlDataSwEn; Tests: T1 T2 T4  92 1/1 end else if (id_en_i || gen_en_i) begin Tests: T1 T2 T3  93 0/1 ==> state_d = StCtrlDataDis; 94 end MISSING_ELSE 95 end 96 97 StCtrlDataHwEn: begin 98 1/1 data_hw_en_o = 1'b1; Tests: T1 T3 T4  99 1/1 if (op_done_i) begin Tests: T1 T3 T4  100 1/1 state_d = StCtrlDataWait; Tests: T1 T3 T4  101 1/1 end else if (adv_en_i || mubi4_test_false_loose(hw_sel_i)) begin Tests: T1 T3 T4  102 1/1 state_d = StCtrlDataDis; Tests: T5 T6 T7  103 end MISSING_ELSE 104 end 105 106 StCtrlDataSwEn: begin 107 1/1 data_sw_en_o = 1'b1; Tests: T1 T2 T4  108 1/1 if (op_done_i) begin Tests: T1 T2 T4  109 1/1 state_d = StCtrlDataWait; Tests: T1 T2 T4  110 1/1 end else if (adv_en_i || mubi4_test_true_loose(hw_sel_i)) begin Tests: T1 T2 T4  111 1/1 state_d = StCtrlDataDis; Tests: T8 T9  112 end MISSING_ELSE 113 end 114 115 StCtrlDataDis: begin 116 1/1 if (op_done_i) begin Tests: T1 T2 T3  117 1/1 state_d = StCtrlDataWait; Tests: T1 T2 T3  118 end MISSING_ELSE 119 end 120 121 StCtrlDataWait: begin 122 1/1 if (!op_start_i) begin Tests: T1 T2 T3  123 1/1 state_d = StCtrlDataIdle; Tests: T1 T2 T3  124 end ==> MISSING_ELSE 125 end 126 127 default: begin 128 fsm_err_o = 1'b1;

Cond Coverage for Module : keymgr_data_en_state
TotalCoveredPercent
Conditions3133.33
Logical3133.33
Non-Logical00
Event00

 LINE       92
 EXPRESSION (id_en_i || gen_en_i)
             ---1---    ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

FSM Coverage for Module : keymgr_data_en_state
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 9 9 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrlDataDis 87 Covered T1,T2,T3
StCtrlDataHwEn 89 Covered T1,T3,T4
StCtrlDataIdle 123 Covered T1,T2,T3
StCtrlDataSwEn 91 Covered T1,T2,T4
StCtrlDataWait 100 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCtrlDataDis->StCtrlDataWait 117 Covered T1,T2,T3
StCtrlDataHwEn->StCtrlDataDis 102 Covered T5,T6,T7
StCtrlDataHwEn->StCtrlDataWait 100 Covered T1,T3,T4
StCtrlDataIdle->StCtrlDataDis 87 Covered T1,T2,T3
StCtrlDataIdle->StCtrlDataHwEn 89 Covered T1,T3,T4
StCtrlDataIdle->StCtrlDataSwEn 91 Covered T1,T2,T4
StCtrlDataSwEn->StCtrlDataDis 111 Covered T8,T9
StCtrlDataSwEn->StCtrlDataWait 109 Covered T1,T2,T4
StCtrlDataWait->StCtrlDataIdle 123 Covered T1,T2,T3



Branch Coverage for Module : keymgr_data_en_state
Line No.TotalCoveredPercent
Branches 18 16 88.89
IF 69 2 2 100.00
CASE 83 16 14 87.50


69 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StCtrlDataIdle) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


83 unique case (state_q) -1- 84 85 StCtrlDataIdle: begin 86 if (adv_en_i) begin -2- 87 state_d = StCtrlDataDis; ==> 88 end else if ((id_en_i || gen_en_i) && mubi4_test_true_strict(hw_sel_i)) begin -3- 89 state_d = StCtrlDataHwEn; ==> 90 end else if ((id_en_i || gen_en_i) && mubi4_test_false_strict(hw_sel_i)) begin -4- 91 state_d = StCtrlDataSwEn; ==> 92 end else if (id_en_i || gen_en_i) begin -5- 93 state_d = StCtrlDataDis; ==> 94 end MISSING_ELSE ==> 95 end 96 97 StCtrlDataHwEn: begin 98 data_hw_en_o = 1'b1; 99 if (op_done_i) begin -6- 100 state_d = StCtrlDataWait; ==> 101 end else if (adv_en_i || mubi4_test_false_loose(hw_sel_i)) begin -7- 102 state_d = StCtrlDataDis; ==> 103 end MISSING_ELSE ==> 104 end 105 106 StCtrlDataSwEn: begin 107 data_sw_en_o = 1'b1; 108 if (op_done_i) begin -8- 109 state_d = StCtrlDataWait; ==> 110 end else if (adv_en_i || mubi4_test_true_loose(hw_sel_i)) begin -9- 111 state_d = StCtrlDataDis; ==> 112 end MISSING_ELSE ==> 113 end 114 115 StCtrlDataDis: begin 116 if (op_done_i) begin -10- 117 state_d = StCtrlDataWait; ==> 118 end MISSING_ELSE ==> 119 end 120 121 StCtrlDataWait: begin 122 if (!op_start_i) begin -11- 123 state_d = StCtrlDataIdle; ==> 124 end MISSING_ELSE ==> 125 end 126 127 default: begin 128 fsm_err_o = 1'b1; ==>

Branches:
-1--2--3--4--5--6--7--8--9--10--11-StatusTests
StCtrlDataIdle 1 - - - - - - - - - Covered T1,T2,T3
StCtrlDataIdle 0 1 - - - - - - - - Covered T1,T3,T4
StCtrlDataIdle 0 0 1 - - - - - - - Covered T1,T2,T4
StCtrlDataIdle 0 0 0 1 - - - - - - Not Covered
StCtrlDataIdle 0 0 0 0 - - - - - - Covered T1,T2,T3
StCtrlDataHwEn - - - - 1 - - - - - Covered T1,T3,T4
StCtrlDataHwEn - - - - 0 1 - - - - Covered T5,T6,T7
StCtrlDataHwEn - - - - 0 0 - - - - Covered T1,T3,T4
StCtrlDataSwEn - - - - - - 1 - - - Covered T1,T2,T4
StCtrlDataSwEn - - - - - - 0 1 - - Covered T8,T9
StCtrlDataSwEn - - - - - - 0 0 - - Covered T1,T2,T4
StCtrlDataDis - - - - - - - - 1 - Covered T1,T2,T3
StCtrlDataDis - - - - - - - - 0 - Covered T1,T2,T3
StCtrlDataWait - - - - - - - - - 1 Covered T1,T2,T3
StCtrlDataWait - - - - - - - - - 0 Not Covered
default - - - - - - - - - - Covered T10,T11,T12


Assert Coverage for Module : keymgr_data_en_state
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
u_state_regs_A 21705443 21550665 0 0


u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21705443 21550665 0 0
T1 5456 5398 0 0
T2 18058 17959 0 0
T3 17046 16955 0 0
T4 5438 5384 0 0
T13 1307 1207 0 0
T14 4324 4161 0 0
T15 4964 4817 0 0
T16 4832 4772 0 0
T17 9788 9733 0 0
T18 11952 11877 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%