Module Definition
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Module Instance : tb.dut.u_cfgen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.15 100.00 94.44 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.15 100.00 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sw_binding_regwen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.25 100.00 94.74 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.25 100.00 94.74 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : keymgr_cfg_en
Line No.TotalCoveredPercent
TOTAL1919100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN3811100.00
ALWAYS4166100.00
ALWAYS5288100.00

29 30 1/1 assign vld_clr = init_q && clr_i; Tests: T1 T2 T3  31 1/1 assign vld_set = init_q && set_i; Tests: T1 T2 T3  32 1/1 assign vld_dis = init_q && !en_i; Tests: T1 T2 T3  33 34 // the same cycle where clear is asserted should already block future 35 // configuration 36 logic out_clr; 37 1/1 assign out_clr = NonInitClr ? clr_i : vld_clr; Tests: T1 T2 T3  38 1/1 assign out_o = ~out_clr & out_q & en_i; Tests: T1 T2 T3  39 40 always_ff @(posedge clk_i or negedge rst_ni) begin 41 1/1 if (!rst_ni) begin Tests: T1 T2 T3  42 1/1 init_q <= '0; Tests: T1 T2 T3  43 1/1 end else if (init_q && !en_i) begin Tests: T1 T2 T3  44 1/1 init_q <= '0; Tests: T74 T5 T92  45 1/1 end else if (init_i && en_i) begin Tests: T1 T2 T3  46 1/1 init_q <= 1'b1; Tests: T1 T2 T3  47 end MISSING_ELSE 48 end 49 50 // clearing the configure enable always has higher priority than setting 51 always_ff @(posedge clk_i or negedge rst_ni) begin 52 1/1 if (!rst_ni) begin Tests: T1 T2 T3  53 1/1 out_q <= 1'b1; Tests: T1 T2 T3  54 1/1 end else if (vld_dis) begin Tests: T1 T2 T3  55 1/1 out_q <= 1'b0; Tests: T74 T5 T92  56 1/1 end else if (vld_set) begin Tests: T1 T2 T3  57 1/1 out_q <= 1'b1; Tests: T1 T2 T3  58 1/1 end else if (out_clr) begin Tests: T1 T2 T3  59 1/1 out_q <= 1'b0; Tests: T1 T2 T3  60 end MISSING_ELSE

Cond Coverage for Module : keymgr_cfg_en
TotalCoveredPercent
Conditions1919100.00
Logical1919100.00
Non-Logical00
Event00

 LINE       30
 EXPRESSION (init_q && clr_i)
             ---1--    --2--
-1--2-StatusTests
01CoveredT4,T15,T17
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       31
 EXPRESSION (init_q && set_i)
             ---1--    --2--
-1--2-StatusTests
01CoveredT74,T5,T92
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       32
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT74,T5,T92

 LINE       38
 EXPRESSION (((~out_clr)) & out_q & en_i)
             ------1-----   --2--   --3-
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T14,T15
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       43
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT74,T5,T92

 LINE       45
 EXPRESSION (init_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Module : keymgr_cfg_en
Line No.TotalCoveredPercent
Branches 9 9 100.00
IF 41 4 4 100.00
IF 52 5 5 100.00


41 if (!rst_ni) begin -1- 42 init_q <= '0; ==> 43 end else if (init_q && !en_i) begin -2- 44 init_q <= '0; ==> 45 end else if (init_i && en_i) begin -3- 46 init_q <= 1'b1; ==> 47 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T74,T5,T92
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


52 if (!rst_ni) begin -1- 53 out_q <= 1'b1; ==> 54 end else if (vld_dis) begin -2- 55 out_q <= 1'b0; ==> 56 end else if (vld_set) begin -3- 57 out_q <= 1'b1; ==> 58 end else if (out_clr) begin -4- 59 out_q <= 1'b0; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T74,T5,T92
0 0 1 - Covered T1,T2,T3
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_cfgen
Line No.TotalCoveredPercent
TOTAL1919100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN3811100.00
ALWAYS4166100.00
ALWAYS5288100.00

29 30 1/1 assign vld_clr = init_q && clr_i; Tests: T1 T2 T3  31 1/1 assign vld_set = init_q && set_i; Tests: T1 T2 T3  32 1/1 assign vld_dis = init_q && !en_i; Tests: T1 T2 T3  33 34 // the same cycle where clear is asserted should already block future 35 // configuration 36 logic out_clr; 37 1/1 assign out_clr = NonInitClr ? clr_i : vld_clr; Tests: T1 T2 T3  38 1/1 assign out_o = ~out_clr & out_q & en_i; Tests: T1 T2 T3  39 40 always_ff @(posedge clk_i or negedge rst_ni) begin 41 1/1 if (!rst_ni) begin Tests: T1 T2 T3  42 1/1 init_q <= '0; Tests: T1 T2 T3  43 1/1 end else if (init_q && !en_i) begin Tests: T1 T2 T3  44 1/1 init_q <= '0; Tests: T74 T5 T92  45 1/1 end else if (init_i && en_i) begin Tests: T1 T2 T3  46 1/1 init_q <= 1'b1; Tests: T1 T2 T3  47 end MISSING_ELSE 48 end 49 50 // clearing the configure enable always has higher priority than setting 51 always_ff @(posedge clk_i or negedge rst_ni) begin 52 1/1 if (!rst_ni) begin Tests: T1 T2 T3  53 1/1 out_q <= 1'b1; Tests: T1 T2 T3  54 1/1 end else if (vld_dis) begin Tests: T1 T2 T3  55 1/1 out_q <= 1'b0; Tests: T74 T5 T92  56 1/1 end else if (vld_set) begin Tests: T1 T2 T3  57 1/1 out_q <= 1'b1; Tests: T1 T2 T3  58 1/1 end else if (out_clr) begin Tests: T1 T2 T3  59 1/1 out_q <= 1'b0; Tests: T1 T2 T3  60 end MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_cfgen
TotalCoveredPercent
Conditions181794.44
Logical181794.44
Non-Logical00
Event00

 LINE       30
 EXPRESSION (init_q && clr_i)
             ---1--    --2--
-1--2-StatusTests
01CoveredT74,T5,T92
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       31
 EXPRESSION (init_q && set_i)
             ---1--    --2--
-1--2-StatusTests
01CoveredT74,T5,T92
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       32
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT74,T5,T92

 LINE       38
 EXPRESSION (((~out_clr)) & out_q & en_i)
             ------1-----   --2--   --3-
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       43
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT74,T5,T92

 LINE       45
 EXPRESSION (init_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_cfgen
Line No.TotalCoveredPercent
Branches 9 9 100.00
IF 41 4 4 100.00
IF 52 5 5 100.00


41 if (!rst_ni) begin -1- 42 init_q <= '0; ==> 43 end else if (init_q && !en_i) begin -2- 44 init_q <= '0; ==> 45 end else if (init_i && en_i) begin -3- 46 init_q <= 1'b1; ==> 47 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T74,T5,T92
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


52 if (!rst_ni) begin -1- 53 out_q <= 1'b1; ==> 54 end else if (vld_dis) begin -2- 55 out_q <= 1'b0; ==> 56 end else if (vld_set) begin -3- 57 out_q <= 1'b1; ==> 58 end else if (out_clr) begin -4- 59 out_q <= 1'b0; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T74,T5,T92
0 0 1 - Covered T1,T2,T3
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_sw_binding_regwen
Line No.TotalCoveredPercent
TOTAL1919100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN3811100.00
ALWAYS4166100.00
ALWAYS5288100.00

29 30 1/1 assign vld_clr = init_q && clr_i; Tests: T1 T2 T3  31 1/1 assign vld_set = init_q && set_i; Tests: T1 T2 T3  32 1/1 assign vld_dis = init_q && !en_i; Tests: T1 T2 T3  33 34 // the same cycle where clear is asserted should already block future 35 // configuration 36 logic out_clr; 37 1/1 assign out_clr = NonInitClr ? clr_i : vld_clr; Tests: T4 T14 T15  38 1/1 assign out_o = ~out_clr & out_q & en_i; Tests: T1 T2 T3  39 40 always_ff @(posedge clk_i or negedge rst_ni) begin 41 1/1 if (!rst_ni) begin Tests: T1 T2 T3  42 1/1 init_q <= '0; Tests: T1 T2 T3  43 1/1 end else if (init_q && !en_i) begin Tests: T1 T2 T3  44 1/1 init_q <= '0; Tests: T74 T5 T92  45 1/1 end else if (init_i && en_i) begin Tests: T1 T2 T3  46 1/1 init_q <= 1'b1; Tests: T1 T2 T3  47 end MISSING_ELSE 48 end 49 50 // clearing the configure enable always has higher priority than setting 51 always_ff @(posedge clk_i or negedge rst_ni) begin 52 1/1 if (!rst_ni) begin Tests: T1 T2 T3  53 1/1 out_q <= 1'b1; Tests: T1 T2 T3  54 1/1 end else if (vld_dis) begin Tests: T1 T2 T3  55 1/1 out_q <= 1'b0; Tests: T74 T5 T92  56 1/1 end else if (vld_set) begin Tests: T1 T2 T3  57 1/1 out_q <= 1'b1; Tests: T1 T2 T3  58 1/1 end else if (out_clr) begin Tests: T1 T2 T3  59 1/1 out_q <= 1'b0; Tests: T4 T14 T15  60 end MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sw_binding_regwen
TotalCoveredPercent
Conditions191894.74
Logical191894.74
Non-Logical00
Event00

 LINE       30
 EXPRESSION (init_q && clr_i)
             ---1--    --2--
-1--2-StatusTests
01CoveredT4,T15,T17
10CoveredT1,T2,T3
11CoveredT14,T15,T18

 LINE       31
 EXPRESSION (init_q && set_i)
             ---1--    --2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       32
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT74,T5,T92

 LINE       38
 EXPRESSION (((~out_clr)) & out_q & en_i)
             ------1-----   --2--   --3-
-1--2--3-StatusTests
011CoveredT4,T14,T15
101CoveredT4,T14,T15
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       43
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT74,T5,T92

 LINE       45
 EXPRESSION (init_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT65,T130,T131
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_sw_binding_regwen
Line No.TotalCoveredPercent
Branches 9 9 100.00
IF 41 4 4 100.00
IF 52 5 5 100.00


41 if (!rst_ni) begin -1- 42 init_q <= '0; ==> 43 end else if (init_q && !en_i) begin -2- 44 init_q <= '0; ==> 45 end else if (init_i && en_i) begin -3- 46 init_q <= 1'b1; ==> 47 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T74,T5,T92
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


52 if (!rst_ni) begin -1- 53 out_q <= 1'b1; ==> 54 end else if (vld_dis) begin -2- 55 out_q <= 1'b0; ==> 56 end else if (vld_set) begin -3- 57 out_q <= 1'b1; ==> 58 end else if (out_clr) begin -4- 59 out_q <= 1'b0; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T74,T5,T92
0 0 1 - Covered T1,T2,T3
0 0 0 1 Covered T4,T14,T15
0 0 0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%