Line Coverage for Module :
prim_lc_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 3/3 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Assert Coverage for Module :
prim_lc_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
877 |
877 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23597045 |
23435244 |
0 |
0 |
T1 |
8844 |
8759 |
0 |
0 |
T2 |
4312 |
4238 |
0 |
0 |
T3 |
14628 |
14535 |
0 |
0 |
T4 |
5785 |
5698 |
0 |
0 |
T5 |
10121 |
10051 |
0 |
0 |
T14 |
138302 |
138202 |
0 |
0 |
T15 |
3043 |
2944 |
0 |
0 |
T16 |
8438 |
8347 |
0 |
0 |
T17 |
4014 |
3925 |
0 |
0 |
T18 |
54324 |
54236 |
0 |
0 |
gen_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23597045 |
23428188 |
0 |
2631 |
T1 |
8844 |
8756 |
0 |
3 |
T2 |
4312 |
4235 |
0 |
3 |
T3 |
14628 |
14532 |
0 |
3 |
T4 |
5785 |
5695 |
0 |
3 |
T5 |
10121 |
10048 |
0 |
3 |
T14 |
138302 |
138199 |
0 |
3 |
T15 |
3043 |
2941 |
0 |
3 |
T16 |
8438 |
8344 |
0 |
3 |
T17 |
4014 |
3922 |
0 |
3 |
T18 |
54324 |
54233 |
0 |
3 |