Unified Coverage Report :: Module :: prim_count

Module : prim_count

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reseed_ctrl.u_reseed_cnt	100.00			100.00
tb.dut.u_ctrl.u_cnt	100.00			100.00
tb.dut.u_kmac_if.u_cnt	100.00			100.00

---

Module Instance : tb.dut.u_reseed_ctrl.u_reseed_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.78	100.00	93.33			100.00		u_reseed_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.u_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.62	100.00	98.11		100.00	100.00	100.00	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_kmac_if.u_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.75	100.00	90.91		100.00	92.86	100.00	u_kmac_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_count ( parameter Width=5,ResetValue=31,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.u_kmac_if.u_cnt

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	42	42	100.00
Total Bits 0->1	21	21	100.00
Total Bits 1->0	21	21	100.00

Ports	9	9	100.00
Port Bits	42	42	100.00
Port Bits 0->1	21	21	100.00
Port Bits 1->0	21	21	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T14,T15,T37	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_cnt_i[4:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
incr_en_i	Unreachable	Unreachable		Unreachable		INPUT
decr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=16,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.u_reseed_ctrl.u_reseed_cnt

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	74	74	100.00
Total Bits 0->1	37	37	100.00
Total Bits 1->0	37	37	100.00

Ports	7	7	100.00
Port Bits	74	74	100.00
Port Bits 0->1	37	37	100.00
Port Bits 1->0	37	37	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T14,T15,T37	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[15:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[15:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=3,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.u_ctrl.u_cnt

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	22	22	100.00
Total Bits 0->1	11	11	100.00
Total Bits 1->0	11	11	100.00

Ports	7	7	100.00
Port Bits	22	22	100.00
Port Bits 0->1	11	11	100.00
Port Bits 1->0	11	11	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T14,T15,T37	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT

Toggle Coverage for Instance : tb.dut.u_reseed_ctrl.u_reseed_cnt

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	74	74	100.00
Total Bits 0->1	37	37	100.00
Total Bits 1->0	37	37	100.00

Ports	7	7	100.00
Port Bits	74	74	100.00
Port Bits 0->1	37	37	100.00
Port Bits 1->0	37	37	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T14,T15,T37	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[15:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[15:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.u_cnt

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	22	22	100.00
Total Bits 0->1	11	11	100.00
Total Bits 1->0	11	11	100.00

Ports	7	7	100.00
Port Bits	22	22	100.00
Port Bits 0->1	11	11	100.00
Port Bits 1->0	11	11	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T14,T15,T37	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT

Toggle Coverage for Instance : tb.dut.u_kmac_if.u_cnt

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	42	42	100.00
Total Bits 0->1	21	21	100.00
Total Bits 1->0	21	21	100.00

Ports	9	9	100.00
Port Bits	42	42	100.00
Port Bits 0->1	21	21	100.00
Port Bits 1->0	21	21	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T14,T15,T37	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_cnt_i[4:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
incr_en_i	Unreachable	Unreachable		Unreachable		INPUT
decr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT