Module Definition
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Module Instance : tb.dut.u_kmac_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.75 100.00 90.91 100.00 92.86 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.35 100.00 90.91 100.00 100.00 93.18 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cnt 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : keymgr_kmac_if
Line No.TotalCoveredPercent
TOTAL112112100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13511100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13811100.00
ALWAYS16133100.00
ALWAYS16933100.00
ALWAYS1725656100.00
CONT_ASSIGN28711100.00
ALWAYS29688100.00
CONT_ASSIGN31311100.00
CONT_ASSIGN31811100.00
CONT_ASSIGN31911100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS33099100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34311100.00
CONT_ASSIGN34411100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35111100.00
CONT_ASSIGN35611100.00
CONT_ASSIGN35711100.00
ALWAYS36344100.00
CONT_ASSIGN36911100.00
CONT_ASSIGN37511100.00
ALWAYS37977100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39411100.00

133 // this is basically for scenarios where *DataWidth % KmacDataIfWidth != 0 134 1/1 assign adv_data = KDFMaxWidth'(adv_data_i); Tests: T1 T2 T3  135 1/1 assign id_data = KDFMaxWidth'(id_data_i); Tests: T1 T2 T3  136 1/1 assign gen_data = KDFMaxWidth'(gen_data_i); Tests: T1 T2 T3  137 138 1/1 assign start = adv_en_i | id_en_i | gen_en_i; Tests: T1 T2 T3  139 140 logic cnt_err; 141 // SEC_CM: KMAC_IF.CTR.REDUN 142 prim_count #( 143 .Width(CntWidth), 144 .ResetValue({CntWidth{1'b1}}) 145 ) u_cnt ( 146 .clk_i, 147 .rst_ni, 148 .clr_i(cnt_clr), 149 .set_i(cnt_set), 150 .set_cnt_i(rounds), 151 .incr_en_i(1'b0), 152 .decr_en_i(cnt_en), 153 .step_i(CntWidth'(1'b1)), 154 .commit_i(1'b1), 155 .cnt_o(cnt), 156 .cnt_after_commit_o(), 157 .err_o(cnt_err) 158 ); 159 160 always_ff @(posedge clk_i or negedge rst_ni) begin 161 1/1 if (!rst_ni) begin Tests: T1 T2 T3  162 1/1 inputs_invalid_q <= '0; Tests: T1 T2 T3  163 end else begin 164 1/1 inputs_invalid_q <= inputs_invalid_d; Tests: T1 T2 T3  165 end 166 end 167 168 // SEC_CM: KMAC_IF.FSM.SPARSE 169 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, data_state_e, StIdle) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, data_state_e, StIdle): 169.1 `ifdef SIMULATION 169.2 prim_sparse_fsm_flop #( 169.3 .StateEnumT(data_state_e), 169.4 .Width($bits(data_state_e)), 169.5 .ResetValue($bits(data_state_e)'(StIdle)), 169.6 .EnableAlertTriggerSVA(1), 169.7 .CustomForceName("state_q") 169.8 ) u_state_regs ( 169.9 .clk_i ( clk_i ), 169.10 .rst_ni ( rst_ni ), 169.11 .state_i ( state_d ), 169.12 .state_o ( ) 169.13 ); 169.14 always_ff @(posedge clk_i or negedge rst_ni) begin 169.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  169.16 1/1 state_q <= StIdle; Tests: T1 T2 T3  169.17 end else begin 169.18 1/1 state_q <= state_d; Tests: T1 T2 T3  169.19 end 169.20 end 169.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 169.22 else begin 169.23 `ifdef UVM 169.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 169.25 "../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv", 169, "", 1); 169.26 `else 169.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 169.28 `PRIM_STRINGIFY(u_state_regs_A)); 169.29 `endif 169.30 end 169.31 `else 169.32 prim_sparse_fsm_flop #( 169.33 .StateEnumT(data_state_e), 169.34 .Width($bits(data_state_e)), 169.35 .ResetValue($bits(data_state_e)'(StIdle)), 169.36 .EnableAlertTriggerSVA(1) 169.37 ) u_state_regs ( 169.38 .clk_i ( `PRIM_FLOP_CLK ), 169.39 .rst_ni ( `PRIM_FLOP_RST ), 169.40 .state_i ( state_d ), 169.41 .state_o ( state_q ) 169.42 ); 169.43 `endif170 171 always_comb begin 172 1/1 cnt_clr = 1'b0; Tests: T1 T2 T3  173 1/1 cnt_set = 1'b0; Tests: T1 T2 T3  174 1/1 cnt_en = 1'b0; Tests: T1 T2 T3  175 1/1 valid = 1'b0; Tests: T1 T2 T3  176 1/1 last = 1'b0; Tests: T1 T2 T3  177 1/1 strb = '0; Tests: T1 T2 T3  178 1/1 done_o = 1'b0; Tests: T1 T2 T3  179 1/1 state_d = state_q; Tests: T1 T2 T3  180 1/1 rounds = '0; Tests: T1 T2 T3  181 182 1/1 clr_err = '0; Tests: T1 T2 T3  183 1/1 fsm_error_o = '0; Tests: T1 T2 T3  184 1/1 kmac_error_o = '0; Tests: T1 T2 T3  185 186 1/1 kmac_done_vld = '0; Tests: T1 T2 T3  187 188 1/1 cmd_chk = 1'b1; Tests: T1 T2 T3  189 190 1/1 unique case (state_q) Tests: T1 T2 T3  191 192 StIdle: begin 193 // if for some reason multiple bits are set, adv_en has priority 194 // as the current key state will be destroyed 195 196 // cross check for commands once transaction begins 197 1/1 cmd_chk = '0; Tests: T1 T2 T3  198 1/1 if (start) begin Tests: T1 T2 T3  199 1/1 cnt_set = 1'b1; Tests: T1 T2 T3  200 1/1 if (adv_en_i) begin Tests: T1 T2 T3  201 1/1 rounds = LastAdvRound; Tests: T1 T2 T3  202 1/1 end else if (id_en_i) begin Tests: T1 T2 T3  203 1/1 rounds = LastIdRound; Tests: T1 T2 T4  204 1/1 end else if (gen_en_i) begin Tests: T1 T2 T3  205 1/1 rounds = LastGenRound; Tests: T1 T2 T3  206 end ==> MISSING_ELSE 207 // in case we are sending only 1 entry 208 1/1 state_d = (rounds == 0) ? StTxLast : StTx; Tests: T1 T2 T3  209 end MISSING_ELSE 210 end 211 212 StTx: begin 213 1/1 valid = 1'b1; Tests: T1 T2 T3  214 1/1 strb = {IfBytes{1'b1}}; Tests: T1 T2 T3  215 216 // transaction accepted 217 1/1 if (kmac_data_i.ready) begin Tests: T1 T2 T3  218 1/1 cnt_en = 1'b1; Tests: T1 T2 T3  219 220 // second to last beat 221 1/1 if (cnt == CntWidth'(1'b1)) begin Tests: T1 T2 T3  222 1/1 state_d = StTxLast; Tests: T1 T2 T3  223 end MISSING_ELSE 224 end MISSING_ELSE 225 226 end 227 228 StTxLast: begin 229 1/1 valid = 1'b1; Tests: T1 T2 T3  230 1/1 last = 1'b1; Tests: T1 T2 T3  231 232 1/1 if (adv_en_i) begin Tests: T1 T2 T3  233 1/1 strb = AdvByteMask; Tests: T1 T2 T3  234 1/1 end else if (id_en_i) begin Tests: T1 T2 T3  235 1/1 strb = IdByteMask; Tests: T1 T2 T4  236 1/1 end else if (gen_en_i) begin Tests: T1 T2 T3  237 1/1 strb = GenByteMask; Tests: T1 T2 T3  238 end MISSING_ELSE 239 240 // transaction accepted 241 1/1 cnt_clr = kmac_data_i.ready; Tests: T1 T2 T3  242 1/1 state_d = kmac_data_i.ready ? StOpWait : StTxLast; Tests: T1 T2 T3  243 244 end 245 246 StOpWait: begin 247 1/1 kmac_done_vld = 1'b1; Tests: T1 T2 T3  248 1/1 if (kmac_data_i.done) begin Tests: T1 T2 T3  249 1/1 kmac_error_o = kmac_data_i.error; Tests: T1 T2 T3  250 1/1 done_o = 1'b1; Tests: T1 T2 T3  251 1/1 state_d = StClean; Tests: T1 T2 T3  252 end MISSING_ELSE 253 end 254 255 StClean: begin 256 1/1 cmd_chk = '0; Tests: T1 T2 T3  257 1/1 done_o = 1'b1; Tests: T1 T2 T3  258 259 // wait for control side to ack done by waiting start de-assertion 260 1/1 if (!start) begin Tests: T1 T2 T3  261 1/1 done_o = 1'b0; Tests: T1 T2 T3  262 1/1 clr_err = 1'b1; Tests: T1 T2 T3  263 1/1 state_d = StIdle; Tests: T1 T2 T3  264 end ==> MISSING_ELSE 265 end 266 267 // trigger error 268 default: begin 269 // This state is terminal 270 done_o = 1'b1; 271 fsm_error_o = 1'b1; 272 end 273 274 endcase // unique case (state_q) 275 276 // unconditional error transitions 277 // counter errors may disturb the fsm flow and are 278 // treated like fsm errors 279 1/1 if (cnt_err) begin Tests: T1 T2 T3  280 1/1 state_d = StError; Tests: T10 T11 T12  281 1/1 fsm_error_o = 1; Tests: T10 T11 T12  282 1/1 done_o = 1'b1; Tests: T10 T11 T12  283 end MISSING_ELSE 284 end 285 286 // when transaction is not complete, populate the data with random 287 1/1 assign data_o = start && done_o ? Tests: T1 T2 T3  288 {kmac_data_i.digest_share1, 289 kmac_data_i.digest_share0} : 290 {{DecoyOutputCopies{entropy_i[1]}}, 291 {DecoyOutputCopies{entropy_i[0]}}}; 292 293 // The input invalid check is done whenever transactions are ongoing with kmac 294 // once set, it cannot be unset until transactions are fully complete 295 always_comb begin 296 1/1 inputs_invalid_d = inputs_invalid_q; Tests: T1 T2 T3  297 298 1/1 if (clr_err) begin Tests: T1 T2 T3  299 1/1 inputs_invalid_d = '0; Tests: T1 T2 T3  300 1/1 end else if (valid) begin Tests: T1 T2 T3  301 1/1 inputs_invalid_d[OpAdvance] = adv_en_i & (inputs_invalid_i[OpAdvance] | Tests: T1 T2 T3  302 inputs_invalid_q[OpAdvance]); 303 1/1 inputs_invalid_d[OpGenId] = id_en_i & (inputs_invalid_i[OpGenId] | Tests: T1 T2 T3  304 inputs_invalid_q[OpGenId]); 305 1/1 inputs_invalid_d[OpGenSwOut] = gen_en_i & (inputs_invalid_i[OpGenSwOut]| Tests: T1 T2 T3  306 inputs_invalid_q[OpGenSwOut]); 307 1/1 inputs_invalid_d[OpGenHwOut] = gen_en_i & (inputs_invalid_i[OpGenHwOut]| Tests: T1 T2 T3  308 inputs_invalid_q[OpGenHwOut]); 309 end MISSING_ELSE 310 end 311 312 // immediately assert errors 313 1/1 assign inputs_invalid_o = |inputs_invalid_d; Tests: T1 T2 T3  314 315 // Permute Share 1 of the entropy input once more to get the decoy data. 316 // Share 0 and 1 are used as is for data_o (connected to the sideload ports). 317 logic [RandWidth-1:0] decoy_entropy; 318 1/1 assign decoy_entropy = perm_data(entropy_i[1], RndCnstRandPerm); Tests: T1 T2 T3  319 1/1 assign decoy_data = {DecoyCopies{decoy_entropy}}; Tests: T1 T2 T3  320 321 logic [CntWidth-1:0] adv_sel, id_sel, gen_sel; 322 1/1 assign adv_sel = LastAdvRound - cnt; Tests: T1 T2 T3  323 1/1 assign id_sel = LastIdRound - cnt; Tests: T1 T2 T3  324 1/1 assign gen_sel = LastGenRound - cnt; Tests: T1 T2 T3  325 326 // The count is maintained as a downcount 327 // so a subtract is necessary to send the right byte 328 // alternatively we can also reverse the order of the input 329 always_comb begin 330 1/1 kmac_data_o.data = decoy_data; Tests: T1 T2 T3  331 1/1 if (|cmd_error_o || inputs_invalid_o || fsm_error_o) begin Tests: T1 T2 T3  332 1/1 kmac_data_o.data = decoy_data; Tests: T15 T19 T10  333 1/1 end else if (valid && adv_en_i) begin Tests: T1 T2 T3  334 1/1 kmac_data_o.data = adv_data[adv_sel]; Tests: T1 T2 T3  335 1/1 end else if (valid && id_en_i) begin Tests: T1 T2 T3  336 1/1 kmac_data_o.data = id_data[id_sel]; Tests: T1 T2 T4  337 1/1 end else if (valid && gen_en_i) begin Tests: T1 T2 T3  338 1/1 kmac_data_o.data = gen_data[gen_sel]; Tests: T1 T2 T3  339 end MISSING_ELSE 340 end 341 342 1/1 assign kmac_data_o.valid = valid; Tests: T1 T2 T3  343 1/1 assign kmac_data_o.last = last; Tests: T1 T2 T3  344 1/1 assign kmac_data_o.strb = strb; Tests: T1 T2 T3  345 346 // kmac done is asserted outside of expected window 347 // SEC_CM: KMAC_IF_DONE.CTRL.CONSISTENCY 348 logic kmac_done_err_q, kmac_done_err_d; 349 1/1 assign kmac_done_err_d = ~kmac_done_vld & kmac_data_i.done | Tests: T1 T2 T3  350 kmac_done_err_q; 351 1/1 assign kmac_done_error_o = kmac_done_err_q; Tests: T1 T2 T3  352 353 354 // the enables must be 1 hot 355 logic [2:0] enables_d, enables_q, enables_sub; 356 1/1 assign enables_d = {adv_en_i, id_en_i, gen_en_i}; Tests: T1 T2 T3  357 1/1 assign enables_sub = enables_d - 1'b1; Tests: T1 T2 T3  358 359 // cross check to ensure the one-hot command that kicked off 360 // the transaction remains consistent throughout. 361 logic cmd_consty_err_q, cmd_consty_err_d; 362 always_ff @(posedge clk_i or negedge rst_ni) begin 363 1/1 if (!rst_ni) begin Tests: T1 T2 T3  364 1/1 enables_q <= '0; Tests: T1 T2 T3  365 1/1 end else if (cnt_set) begin Tests: T1 T2 T3  366 1/1 enables_q <= enables_d; Tests: T1 T2 T3  367 end MISSING_ELSE 368 end 369 1/1 assign cmd_consty_err_d = (cmd_chk & (enables_q != enables_d)) | Tests: T1 T2 T3  370 cmd_consty_err_q; 371 372 // if a one hot error occurs, latch onto it permanently 373 // SEC_CM: KMAC_IF_CMD.CTRL.CONSISTENCY 374 logic one_hot_err_q, one_hot_err_d; 375 1/1 assign one_hot_err_d = |(enables_d & enables_sub) | Tests: T1 T2 T3  376 one_hot_err_q; 377 378 always_ff @(posedge clk_i or negedge rst_ni) begin 379 1/1 if (!rst_ni) begin Tests: T1 T2 T3  380 1/1 one_hot_err_q <= '0; Tests: T1 T2 T3  381 1/1 kmac_done_err_q <= '0; Tests: T1 T2 T3  382 1/1 cmd_consty_err_q <= '0; Tests: T1 T2 T3  383 end else begin 384 1/1 one_hot_err_q <= one_hot_err_d; Tests: T1 T2 T3  385 1/1 kmac_done_err_q <= kmac_done_err_d; Tests: T1 T2 T3  386 1/1 cmd_consty_err_q <= cmd_consty_err_d; Tests: T1 T2 T3  387 end 388 end 389 390 // command error occurs if kmac errors or if the command itself is invalid 391 1/1 assign cmd_error_o = one_hot_err_q | cmd_consty_err_q; Tests: T1 T2 T3  392 393 // request entropy to churn whenever a transaction is accepted 394 1/1 assign prng_en_o = kmac_data_o.valid & kmac_data_i.ready; Tests: T1 T2 T3 

Cond Coverage for Module : keymgr_kmac_if
TotalCoveredPercent
Conditions777090.91
Logical777090.91
Non-Logical00
Event00

 LINE       138
 EXPRESSION (adv_en_i | id_en_i | gen_en_i)
             ----1---   ---2---   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT1,T2,T4
100CoveredT1,T2,T3

 LINE       208
 EXPRESSION ((rounds == 5'b0) ? StTxLast : StTx)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       208
 SUB-EXPRESSION (rounds == 5'b0)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       221
 EXPRESSION (cnt == 5'(1'b1))
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       242
 EXPRESSION (kmac_data_i.ready ? StOpWait : StTxLast)
             --------1--------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       287
 EXPRESSION 
 Number  Term
      1  (start && done_o) ? ({kmac_data_i.digest_share1, kmac_data_i.digest_share0}) : ({{DecoyOutputCopies {entropy_i[1]}}, {DecoyOutputCopies {entropy_i[0]}}}))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       287
 SUB-EXPRESSION (start && done_o)
                 --1--    ---2--
-1--2-StatusTests
01CoveredT15,T10,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       301
 EXPRESSION (adv_en_i & (inputs_invalid_i[OpAdvance] | inputs_invalid_q[OpAdvance]))
             ----1---   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT20,T21,T22
10CoveredT1,T2,T3
11CoveredT23,T24,T21

 LINE       301
 SUB-EXPRESSION (inputs_invalid_i[OpAdvance] | inputs_invalid_q[OpAdvance])
                 -------------1-------------   -------------2-------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT20,T23,T24

 LINE       303
 EXPRESSION (id_en_i & (inputs_invalid_i[OpGenId] | inputs_invalid_q[OpGenId]))
             ---1---   ---------------------------2---------------------------
-1--2-StatusTests
01CoveredT20,T22,T25
10CoveredT1,T2,T4
11Not Covered

 LINE       303
 SUB-EXPRESSION (inputs_invalid_i[OpGenId] | inputs_invalid_q[OpGenId])
                 ------------1------------   ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT20,T22,T25

 LINE       305
 EXPRESSION (gen_en_i & (inputs_invalid_i[OpGenSwOut] | inputs_invalid_q[OpGenSwOut]))
             ----1---   ------------------------------2------------------------------
-1--2-StatusTests
01CoveredT15,T18,T19
10CoveredT1,T2,T3
11CoveredT19,T5,T26

 LINE       305
 SUB-EXPRESSION (inputs_invalid_i[OpGenSwOut] | inputs_invalid_q[OpGenSwOut])
                 --------------1-------------   --------------2-------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT15,T18,T19

 LINE       307
 EXPRESSION (gen_en_i & (inputs_invalid_i[OpGenHwOut] | inputs_invalid_q[OpGenHwOut]))
             ----1---   ------------------------------2------------------------------
-1--2-StatusTests
01CoveredT15,T18,T19
10CoveredT1,T2,T3
11CoveredT19,T5,T26

 LINE       307
 SUB-EXPRESSION (inputs_invalid_i[OpGenHwOut] | inputs_invalid_q[OpGenHwOut])
                 --------------1-------------   --------------2-------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT15,T18,T19

 LINE       331
 EXPRESSION (((|cmd_error_o)) || inputs_invalid_o || fsm_error_o)
             --------1-------    --------2-------    -----3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT10,T11,T12
010CoveredT19,T5,T26
100CoveredT15,T20,T27

 LINE       333
 EXPRESSION (valid && adv_en_i)
             --1--    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       335
 EXPRESSION (valid && id_en_i)
             --1--    ---2---
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       337
 EXPRESSION (valid && gen_en_i)
             --1--    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT15,T20,T27
11CoveredT1,T2,T3

 LINE       349
 EXPRESSION ((((~kmac_done_vld)) & kmac_data_i.done) | kmac_done_err_q)
             -------------------1-------------------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT1,T2,T3

 LINE       349
 SUB-EXPRESSION (((~kmac_done_vld)) & kmac_data_i.done)
                 ---------1--------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       369
 EXPRESSION ((cmd_chk & (enables_q != enables_d)) | cmd_consty_err_q)
             ------------------1-----------------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT15,T20,T27
10CoveredT15,T20,T27

 LINE       369
 SUB-EXPRESSION (cmd_chk & (enables_q != enables_d))
                 ---1---   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT15,T20,T27

 LINE       369
 SUB-EXPRESSION (enables_q != enables_d)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       375
 EXPRESSION (((|(enables_d & enables_sub))) | one_hot_err_q)
             ---------------1--------------   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T31,T32
10CoveredT22,T31,T32

 LINE       391
 EXPRESSION (one_hot_err_q | cmd_consty_err_q)
             ------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT15,T20,T27
10CoveredT22,T33,T34

 LINE       394
 EXPRESSION (kmac_data_o.valid & kmac_data_i.ready)
             --------1--------   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT1,T2,T3

FSM Coverage for Module : keymgr_kmac_if
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 11 6 54.55
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StClean 251 Covered T1,T2,T3
StError 280 Covered T10,T11,T12
StIdle 263 Covered T1,T2,T3
StOpWait 242 Covered T1,T2,T3
StTx 208 Covered T1,T2,T3
StTxLast 208 Covered T1,T2,T3


transitionsLine No.CoveredTests
StClean->StError 280 Not Covered
StClean->StIdle 263 Covered T1,T2,T3
StIdle->StError 280 Covered T10,T11,T12
StIdle->StTx 208 Covered T1,T2,T3
StIdle->StTxLast 208 Not Covered
StOpWait->StClean 251 Covered T1,T2,T3
StOpWait->StError 280 Not Covered
StTx->StError 280 Not Covered
StTx->StTxLast 222 Covered T1,T2,T3
StTxLast->StError 280 Not Covered
StTxLast->StOpWait 242 Covered T1,T2,T3



Branch Coverage for Module : keymgr_kmac_if
Line No.TotalCoveredPercent
Branches 42 39 92.86
TERNARY 287 2 2 100.00
IF 161 2 2 100.00
IF 169 2 2 100.00
CASE 190 21 18 85.71
IF 279 2 2 100.00
IF 298 3 3 100.00
IF 331 5 5 100.00
IF 363 3 3 100.00
IF 379 2 2 100.00


287 assign data_o = start && done_o ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


161 if (!rst_ni) begin -1- 162 inputs_invalid_q <= '0; ==> 163 end else begin 164 inputs_invalid_q <= inputs_invalid_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


169 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, data_state_e, StIdle) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


190 unique case (state_q) -1- 191 192 StIdle: begin 193 // if for some reason multiple bits are set, adv_en has priority 194 // as the current key state will be destroyed 195 196 // cross check for commands once transaction begins 197 cmd_chk = '0; 198 if (start) begin -2- 199 cnt_set = 1'b1; 200 if (adv_en_i) begin -3- 201 rounds = LastAdvRound; ==> 202 end else if (id_en_i) begin -4- 203 rounds = LastIdRound; ==> 204 end else if (gen_en_i) begin -5- 205 rounds = LastGenRound; ==> 206 end MISSING_ELSE ==> 207 // in case we are sending only 1 entry 208 state_d = (rounds == 0) ? StTxLast : StTx; -6- ==> ==> 209 end MISSING_ELSE ==> 210 end 211 212 StTx: begin 213 valid = 1'b1; 214 strb = {IfBytes{1'b1}}; 215 216 // transaction accepted 217 if (kmac_data_i.ready) begin -7- 218 cnt_en = 1'b1; 219 220 // second to last beat 221 if (cnt == CntWidth'(1'b1)) begin -8- 222 state_d = StTxLast; ==> 223 end MISSING_ELSE ==> 224 end MISSING_ELSE ==> 225 226 end 227 228 StTxLast: begin 229 valid = 1'b1; 230 last = 1'b1; 231 232 if (adv_en_i) begin -9- 233 strb = AdvByteMask; ==> 234 end else if (id_en_i) begin -10- 235 strb = IdByteMask; ==> 236 end else if (gen_en_i) begin -11- 237 strb = GenByteMask; ==> 238 end MISSING_ELSE ==> 239 240 // transaction accepted 241 cnt_clr = kmac_data_i.ready; 242 state_d = kmac_data_i.ready ? StOpWait : StTxLast; -12- ==> ==> 243 244 end 245 246 StOpWait: begin 247 kmac_done_vld = 1'b1; 248 if (kmac_data_i.done) begin -13- 249 kmac_error_o = kmac_data_i.error; ==> 250 done_o = 1'b1; 251 state_d = StClean; 252 end MISSING_ELSE ==> 253 end 254 255 StClean: begin 256 cmd_chk = '0; 257 done_o = 1'b1; 258 259 // wait for control side to ack done by waiting start de-assertion 260 if (!start) begin -14- 261 done_o = 1'b0; ==> 262 clr_err = 1'b1; 263 state_d = StIdle; 264 end MISSING_ELSE ==> 265 end 266 267 // trigger error 268 default: begin 269 // This state is terminal 270 done_o = 1'b1; ==>

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTests
StIdle 1 1 - - - - - - - - - - - Covered T1,T2,T3
StIdle 1 0 1 - - - - - - - - - - Covered T1,T2,T4
StIdle 1 0 0 1 - - - - - - - - - Covered T1,T2,T3
StIdle 1 0 0 0 - - - - - - - - - Not Covered
StIdle 1 - - - 1 - - - - - - - - Not Covered
StIdle 1 - - - 0 - - - - - - - - Covered T1,T2,T3
StIdle 0 - - - - - - - - - - - - Covered T1,T2,T3
StTx - - - - - 1 1 - - - - - - Covered T1,T2,T3
StTx - - - - - 1 0 - - - - - - Covered T1,T2,T3
StTx - - - - - 0 - - - - - - - Covered T2,T3,T4
StTxLast - - - - - - - 1 - - - - - Covered T1,T2,T3
StTxLast - - - - - - - 0 1 - - - - Covered T1,T2,T4
StTxLast - - - - - - - 0 0 1 - - - Covered T1,T2,T3
StTxLast - - - - - - - 0 0 0 - - - Covered T15,T20,T27
StTxLast - - - - - - - - - - 1 - - Covered T1,T2,T3
StTxLast - - - - - - - - - - 0 - - Covered T2,T3,T4
StOpWait - - - - - - - - - - - 1 - Covered T1,T2,T3
StOpWait - - - - - - - - - - - 0 - Covered T1,T2,T3
StClean - - - - - - - - - - - - 1 Covered T1,T2,T3
StClean - - - - - - - - - - - - 0 Not Covered
default - - - - - - - - - - - - - Covered T10,T11,T12


279 if (cnt_err) begin -1- 280 state_d = StError; ==> 281 fsm_error_o = 1; 282 done_o = 1'b1; 283 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3


298 if (clr_err) begin -1- 299 inputs_invalid_d = '0; ==> 300 end else if (valid) begin -2- 301 inputs_invalid_d[OpAdvance] = adv_en_i & (inputs_invalid_i[OpAdvance] | ==> 302 inputs_invalid_q[OpAdvance]); 303 inputs_invalid_d[OpGenId] = id_en_i & (inputs_invalid_i[OpGenId] | 304 inputs_invalid_q[OpGenId]); 305 inputs_invalid_d[OpGenSwOut] = gen_en_i & (inputs_invalid_i[OpGenSwOut]| 306 inputs_invalid_q[OpGenSwOut]); 307 inputs_invalid_d[OpGenHwOut] = gen_en_i & (inputs_invalid_i[OpGenHwOut]| 308 inputs_invalid_q[OpGenHwOut]); 309 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


331 if (|cmd_error_o || inputs_invalid_o || fsm_error_o) begin -1- 332 kmac_data_o.data = decoy_data; ==> 333 end else if (valid && adv_en_i) begin -2- 334 kmac_data_o.data = adv_data[adv_sel]; ==> 335 end else if (valid && id_en_i) begin -3- 336 kmac_data_o.data = id_data[id_sel]; ==> 337 end else if (valid && gen_en_i) begin -4- 338 kmac_data_o.data = gen_data[gen_sel]; ==> 339 end MISSING_ELSE ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T15,T19,T10
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T2,T4
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3


363 if (!rst_ni) begin -1- 364 enables_q <= '0; ==> 365 end else if (cnt_set) begin -2- 366 enables_q <= enables_d; ==> 367 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


379 if (!rst_ni) begin -1- 380 one_hot_err_q <= '0; ==> 381 kmac_done_err_q <= '0; 382 cmd_consty_err_q <= '0; 383 end else begin 384 one_hot_err_q <= one_hot_err_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : keymgr_kmac_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AdvRemBytes_A 875 875 0 0
GenRemBytes_A 875 875 0 0
IdRemBytes_A 875 875 0 0
LastStrb_A 21286633 13894069 0 0
u_state_regs_A 21705443 21550665 0 0


AdvRemBytes_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 875 875 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

GenRemBytes_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 875 875 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

IdRemBytes_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 875 875 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

LastStrb_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21286633 13894069 0 0
T1 5456 338 0 0
T2 18058 13621 0 0
T3 17046 11694 0 0
T4 5438 2296 0 0
T13 1307 0 0 0
T14 4324 0 0 0
T15 2423 102 0 0
T16 4832 338 0 0
T17 9788 4343 0 0
T18 11952 3161 0 0
T35 0 4605 0 0
T36 0 18229 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21705443 21550665 0 0
T1 5456 5398 0 0
T2 18058 17959 0 0
T3 17046 16955 0 0
T4 5438 5384 0 0
T13 1307 1207 0 0
T14 4324 4161 0 0
T15 4964 4817 0 0
T16 4832 4772 0 0
T17 9788 9733 0 0
T18 11952 11877 0 0

Line Coverage for Instance : tb.dut.u_kmac_if
Line No.TotalCoveredPercent
TOTAL112112100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13511100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13811100.00
ALWAYS16133100.00
ALWAYS16933100.00
ALWAYS1725656100.00
CONT_ASSIGN28711100.00
ALWAYS29688100.00
CONT_ASSIGN31311100.00
CONT_ASSIGN31811100.00
CONT_ASSIGN31911100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS33099100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34311100.00
CONT_ASSIGN34411100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35111100.00
CONT_ASSIGN35611100.00
CONT_ASSIGN35711100.00
ALWAYS36344100.00
CONT_ASSIGN36911100.00
CONT_ASSIGN37511100.00
ALWAYS37977100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39411100.00

133 // this is basically for scenarios where *DataWidth % KmacDataIfWidth != 0 134 1/1 assign adv_data = KDFMaxWidth'(adv_data_i); Tests: T1 T2 T3  135 1/1 assign id_data = KDFMaxWidth'(id_data_i); Tests: T1 T2 T3  136 1/1 assign gen_data = KDFMaxWidth'(gen_data_i); Tests: T1 T2 T3  137 138 1/1 assign start = adv_en_i | id_en_i | gen_en_i; Tests: T1 T2 T3  139 140 logic cnt_err; 141 // SEC_CM: KMAC_IF.CTR.REDUN 142 prim_count #( 143 .Width(CntWidth), 144 .ResetValue({CntWidth{1'b1}}) 145 ) u_cnt ( 146 .clk_i, 147 .rst_ni, 148 .clr_i(cnt_clr), 149 .set_i(cnt_set), 150 .set_cnt_i(rounds), 151 .incr_en_i(1'b0), 152 .decr_en_i(cnt_en), 153 .step_i(CntWidth'(1'b1)), 154 .commit_i(1'b1), 155 .cnt_o(cnt), 156 .cnt_after_commit_o(), 157 .err_o(cnt_err) 158 ); 159 160 always_ff @(posedge clk_i or negedge rst_ni) begin 161 1/1 if (!rst_ni) begin Tests: T1 T2 T3  162 1/1 inputs_invalid_q <= '0; Tests: T1 T2 T3  163 end else begin 164 1/1 inputs_invalid_q <= inputs_invalid_d; Tests: T1 T2 T3  165 end 166 end 167 168 // SEC_CM: KMAC_IF.FSM.SPARSE 169 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, data_state_e, StIdle) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, data_state_e, StIdle): 169.1 `ifdef SIMULATION 169.2 prim_sparse_fsm_flop #( 169.3 .StateEnumT(data_state_e), 169.4 .Width($bits(data_state_e)), 169.5 .ResetValue($bits(data_state_e)'(StIdle)), 169.6 .EnableAlertTriggerSVA(1), 169.7 .CustomForceName("state_q") 169.8 ) u_state_regs ( 169.9 .clk_i ( clk_i ), 169.10 .rst_ni ( rst_ni ), 169.11 .state_i ( state_d ), 169.12 .state_o ( ) 169.13 ); 169.14 always_ff @(posedge clk_i or negedge rst_ni) begin 169.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  169.16 1/1 state_q <= StIdle; Tests: T1 T2 T3  169.17 end else begin 169.18 1/1 state_q <= state_d; Tests: T1 T2 T3  169.19 end 169.20 end 169.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 169.22 else begin 169.23 `ifdef UVM 169.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 169.25 "../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv", 169, "", 1); 169.26 `else 169.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 169.28 `PRIM_STRINGIFY(u_state_regs_A)); 169.29 `endif 169.30 end 169.31 `else 169.32 prim_sparse_fsm_flop #( 169.33 .StateEnumT(data_state_e), 169.34 .Width($bits(data_state_e)), 169.35 .ResetValue($bits(data_state_e)'(StIdle)), 169.36 .EnableAlertTriggerSVA(1) 169.37 ) u_state_regs ( 169.38 .clk_i ( `PRIM_FLOP_CLK ), 169.39 .rst_ni ( `PRIM_FLOP_RST ), 169.40 .state_i ( state_d ), 169.41 .state_o ( state_q ) 169.42 ); 169.43 `endif170 171 always_comb begin 172 1/1 cnt_clr = 1'b0; Tests: T1 T2 T3  173 1/1 cnt_set = 1'b0; Tests: T1 T2 T3  174 1/1 cnt_en = 1'b0; Tests: T1 T2 T3  175 1/1 valid = 1'b0; Tests: T1 T2 T3  176 1/1 last = 1'b0; Tests: T1 T2 T3  177 1/1 strb = '0; Tests: T1 T2 T3  178 1/1 done_o = 1'b0; Tests: T1 T2 T3  179 1/1 state_d = state_q; Tests: T1 T2 T3  180 1/1 rounds = '0; Tests: T1 T2 T3  181 182 1/1 clr_err = '0; Tests: T1 T2 T3  183 1/1 fsm_error_o = '0; Tests: T1 T2 T3  184 1/1 kmac_error_o = '0; Tests: T1 T2 T3  185 186 1/1 kmac_done_vld = '0; Tests: T1 T2 T3  187 188 1/1 cmd_chk = 1'b1; Tests: T1 T2 T3  189 190 1/1 unique case (state_q) Tests: T1 T2 T3  191 192 StIdle: begin 193 // if for some reason multiple bits are set, adv_en has priority 194 // as the current key state will be destroyed 195 196 // cross check for commands once transaction begins 197 1/1 cmd_chk = '0; Tests: T1 T2 T3  198 1/1 if (start) begin Tests: T1 T2 T3  199 1/1 cnt_set = 1'b1; Tests: T1 T2 T3  200 1/1 if (adv_en_i) begin Tests: T1 T2 T3  201 1/1 rounds = LastAdvRound; Tests: T1 T2 T3  202 1/1 end else if (id_en_i) begin Tests: T1 T2 T3  203 1/1 rounds = LastIdRound; Tests: T1 T2 T4  204 1/1 end else if (gen_en_i) begin Tests: T1 T2 T3  205 1/1 rounds = LastGenRound; Tests: T1 T2 T3  206 end ==> MISSING_ELSE 207 // in case we are sending only 1 entry 208 1/1 state_d = (rounds == 0) ? StTxLast : StTx; Tests: T1 T2 T3  209 end MISSING_ELSE 210 end 211 212 StTx: begin 213 1/1 valid = 1'b1; Tests: T1 T2 T3  214 1/1 strb = {IfBytes{1'b1}}; Tests: T1 T2 T3  215 216 // transaction accepted 217 1/1 if (kmac_data_i.ready) begin Tests: T1 T2 T3  218 1/1 cnt_en = 1'b1; Tests: T1 T2 T3  219 220 // second to last beat 221 1/1 if (cnt == CntWidth'(1'b1)) begin Tests: T1 T2 T3  222 1/1 state_d = StTxLast; Tests: T1 T2 T3  223 end MISSING_ELSE 224 end MISSING_ELSE 225 226 end 227 228 StTxLast: begin 229 1/1 valid = 1'b1; Tests: T1 T2 T3  230 1/1 last = 1'b1; Tests: T1 T2 T3  231 232 1/1 if (adv_en_i) begin Tests: T1 T2 T3  233 1/1 strb = AdvByteMask; Tests: T1 T2 T3  234 1/1 end else if (id_en_i) begin Tests: T1 T2 T3  235 1/1 strb = IdByteMask; Tests: T1 T2 T4  236 1/1 end else if (gen_en_i) begin Tests: T1 T2 T3  237 1/1 strb = GenByteMask; Tests: T1 T2 T3  238 end MISSING_ELSE 239 240 // transaction accepted 241 1/1 cnt_clr = kmac_data_i.ready; Tests: T1 T2 T3  242 1/1 state_d = kmac_data_i.ready ? StOpWait : StTxLast; Tests: T1 T2 T3  243 244 end 245 246 StOpWait: begin 247 1/1 kmac_done_vld = 1'b1; Tests: T1 T2 T3  248 1/1 if (kmac_data_i.done) begin Tests: T1 T2 T3  249 1/1 kmac_error_o = kmac_data_i.error; Tests: T1 T2 T3  250 1/1 done_o = 1'b1; Tests: T1 T2 T3  251 1/1 state_d = StClean; Tests: T1 T2 T3  252 end MISSING_ELSE 253 end 254 255 StClean: begin 256 1/1 cmd_chk = '0; Tests: T1 T2 T3  257 1/1 done_o = 1'b1; Tests: T1 T2 T3  258 259 // wait for control side to ack done by waiting start de-assertion 260 1/1 if (!start) begin Tests: T1 T2 T3  261 1/1 done_o = 1'b0; Tests: T1 T2 T3  262 1/1 clr_err = 1'b1; Tests: T1 T2 T3  263 1/1 state_d = StIdle; Tests: T1 T2 T3  264 end ==> MISSING_ELSE 265 end 266 267 // trigger error 268 default: begin 269 // This state is terminal 270 done_o = 1'b1; 271 fsm_error_o = 1'b1; 272 end 273 274 endcase // unique case (state_q) 275 276 // unconditional error transitions 277 // counter errors may disturb the fsm flow and are 278 // treated like fsm errors 279 1/1 if (cnt_err) begin Tests: T1 T2 T3  280 1/1 state_d = StError; Tests: T10 T11 T12  281 1/1 fsm_error_o = 1; Tests: T10 T11 T12  282 1/1 done_o = 1'b1; Tests: T10 T11 T12  283 end MISSING_ELSE 284 end 285 286 // when transaction is not complete, populate the data with random 287 1/1 assign data_o = start && done_o ? Tests: T1 T2 T3  288 {kmac_data_i.digest_share1, 289 kmac_data_i.digest_share0} : 290 {{DecoyOutputCopies{entropy_i[1]}}, 291 {DecoyOutputCopies{entropy_i[0]}}}; 292 293 // The input invalid check is done whenever transactions are ongoing with kmac 294 // once set, it cannot be unset until transactions are fully complete 295 always_comb begin 296 1/1 inputs_invalid_d = inputs_invalid_q; Tests: T1 T2 T3  297 298 1/1 if (clr_err) begin Tests: T1 T2 T3  299 1/1 inputs_invalid_d = '0; Tests: T1 T2 T3  300 1/1 end else if (valid) begin Tests: T1 T2 T3  301 1/1 inputs_invalid_d[OpAdvance] = adv_en_i & (inputs_invalid_i[OpAdvance] | Tests: T1 T2 T3  302 inputs_invalid_q[OpAdvance]); 303 1/1 inputs_invalid_d[OpGenId] = id_en_i & (inputs_invalid_i[OpGenId] | Tests: T1 T2 T3  304 inputs_invalid_q[OpGenId]); 305 1/1 inputs_invalid_d[OpGenSwOut] = gen_en_i & (inputs_invalid_i[OpGenSwOut]| Tests: T1 T2 T3  306 inputs_invalid_q[OpGenSwOut]); 307 1/1 inputs_invalid_d[OpGenHwOut] = gen_en_i & (inputs_invalid_i[OpGenHwOut]| Tests: T1 T2 T3  308 inputs_invalid_q[OpGenHwOut]); 309 end MISSING_ELSE 310 end 311 312 // immediately assert errors 313 1/1 assign inputs_invalid_o = |inputs_invalid_d; Tests: T1 T2 T3  314 315 // Permute Share 1 of the entropy input once more to get the decoy data. 316 // Share 0 and 1 are used as is for data_o (connected to the sideload ports). 317 logic [RandWidth-1:0] decoy_entropy; 318 1/1 assign decoy_entropy = perm_data(entropy_i[1], RndCnstRandPerm); Tests: T1 T2 T3  319 1/1 assign decoy_data = {DecoyCopies{decoy_entropy}}; Tests: T1 T2 T3  320 321 logic [CntWidth-1:0] adv_sel, id_sel, gen_sel; 322 1/1 assign adv_sel = LastAdvRound - cnt; Tests: T1 T2 T3  323 1/1 assign id_sel = LastIdRound - cnt; Tests: T1 T2 T3  324 1/1 assign gen_sel = LastGenRound - cnt; Tests: T1 T2 T3  325 326 // The count is maintained as a downcount 327 // so a subtract is necessary to send the right byte 328 // alternatively we can also reverse the order of the input 329 always_comb begin 330 1/1 kmac_data_o.data = decoy_data; Tests: T1 T2 T3  331 1/1 if (|cmd_error_o || inputs_invalid_o || fsm_error_o) begin Tests: T1 T2 T3  332 1/1 kmac_data_o.data = decoy_data; Tests: T15 T19 T10  333 1/1 end else if (valid && adv_en_i) begin Tests: T1 T2 T3  334 1/1 kmac_data_o.data = adv_data[adv_sel]; Tests: T1 T2 T3  335 1/1 end else if (valid && id_en_i) begin Tests: T1 T2 T3  336 1/1 kmac_data_o.data = id_data[id_sel]; Tests: T1 T2 T4  337 1/1 end else if (valid && gen_en_i) begin Tests: T1 T2 T3  338 1/1 kmac_data_o.data = gen_data[gen_sel]; Tests: T1 T2 T3  339 end MISSING_ELSE 340 end 341 342 1/1 assign kmac_data_o.valid = valid; Tests: T1 T2 T3  343 1/1 assign kmac_data_o.last = last; Tests: T1 T2 T3  344 1/1 assign kmac_data_o.strb = strb; Tests: T1 T2 T3  345 346 // kmac done is asserted outside of expected window 347 // SEC_CM: KMAC_IF_DONE.CTRL.CONSISTENCY 348 logic kmac_done_err_q, kmac_done_err_d; 349 1/1 assign kmac_done_err_d = ~kmac_done_vld & kmac_data_i.done | Tests: T1 T2 T3  350 kmac_done_err_q; 351 1/1 assign kmac_done_error_o = kmac_done_err_q; Tests: T1 T2 T3  352 353 354 // the enables must be 1 hot 355 logic [2:0] enables_d, enables_q, enables_sub; 356 1/1 assign enables_d = {adv_en_i, id_en_i, gen_en_i}; Tests: T1 T2 T3  357 1/1 assign enables_sub = enables_d - 1'b1; Tests: T1 T2 T3  358 359 // cross check to ensure the one-hot command that kicked off 360 // the transaction remains consistent throughout. 361 logic cmd_consty_err_q, cmd_consty_err_d; 362 always_ff @(posedge clk_i or negedge rst_ni) begin 363 1/1 if (!rst_ni) begin Tests: T1 T2 T3  364 1/1 enables_q <= '0; Tests: T1 T2 T3  365 1/1 end else if (cnt_set) begin Tests: T1 T2 T3  366 1/1 enables_q <= enables_d; Tests: T1 T2 T3  367 end MISSING_ELSE 368 end 369 1/1 assign cmd_consty_err_d = (cmd_chk & (enables_q != enables_d)) | Tests: T1 T2 T3  370 cmd_consty_err_q; 371 372 // if a one hot error occurs, latch onto it permanently 373 // SEC_CM: KMAC_IF_CMD.CTRL.CONSISTENCY 374 logic one_hot_err_q, one_hot_err_d; 375 1/1 assign one_hot_err_d = |(enables_d & enables_sub) | Tests: T1 T2 T3  376 one_hot_err_q; 377 378 always_ff @(posedge clk_i or negedge rst_ni) begin 379 1/1 if (!rst_ni) begin Tests: T1 T2 T3  380 1/1 one_hot_err_q <= '0; Tests: T1 T2 T3  381 1/1 kmac_done_err_q <= '0; Tests: T1 T2 T3  382 1/1 cmd_consty_err_q <= '0; Tests: T1 T2 T3  383 end else begin 384 1/1 one_hot_err_q <= one_hot_err_d; Tests: T1 T2 T3  385 1/1 kmac_done_err_q <= kmac_done_err_d; Tests: T1 T2 T3  386 1/1 cmd_consty_err_q <= cmd_consty_err_d; Tests: T1 T2 T3  387 end 388 end 389 390 // command error occurs if kmac errors or if the command itself is invalid 391 1/1 assign cmd_error_o = one_hot_err_q | cmd_consty_err_q; Tests: T1 T2 T3  392 393 // request entropy to churn whenever a transaction is accepted 394 1/1 assign prng_en_o = kmac_data_o.valid & kmac_data_i.ready; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_kmac_if
TotalCoveredPercent
Conditions777090.91
Logical777090.91
Non-Logical00
Event00

 LINE       138
 EXPRESSION (adv_en_i | id_en_i | gen_en_i)
             ----1---   ---2---   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT1,T2,T4
100CoveredT1,T2,T3

 LINE       208
 EXPRESSION ((rounds == 5'b0) ? StTxLast : StTx)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       208
 SUB-EXPRESSION (rounds == 5'b0)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       221
 EXPRESSION (cnt == 5'(1'b1))
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       242
 EXPRESSION (kmac_data_i.ready ? StOpWait : StTxLast)
             --------1--------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       287
 EXPRESSION 
 Number  Term
      1  (start && done_o) ? ({kmac_data_i.digest_share1, kmac_data_i.digest_share0}) : ({{DecoyOutputCopies {entropy_i[1]}}, {DecoyOutputCopies {entropy_i[0]}}}))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       287
 SUB-EXPRESSION (start && done_o)
                 --1--    ---2--
-1--2-StatusTests
01CoveredT15,T10,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       301
 EXPRESSION (adv_en_i & (inputs_invalid_i[OpAdvance] | inputs_invalid_q[OpAdvance]))
             ----1---   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT20,T21,T22
10CoveredT1,T2,T3
11CoveredT23,T24,T21

 LINE       301
 SUB-EXPRESSION (inputs_invalid_i[OpAdvance] | inputs_invalid_q[OpAdvance])
                 -------------1-------------   -------------2-------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT20,T23,T24

 LINE       303
 EXPRESSION (id_en_i & (inputs_invalid_i[OpGenId] | inputs_invalid_q[OpGenId]))
             ---1---   ---------------------------2---------------------------
-1--2-StatusTests
01CoveredT20,T22,T25
10CoveredT1,T2,T4
11Not Covered

 LINE       303
 SUB-EXPRESSION (inputs_invalid_i[OpGenId] | inputs_invalid_q[OpGenId])
                 ------------1------------   ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT20,T22,T25

 LINE       305
 EXPRESSION (gen_en_i & (inputs_invalid_i[OpGenSwOut] | inputs_invalid_q[OpGenSwOut]))
             ----1---   ------------------------------2------------------------------
-1--2-StatusTests
01CoveredT15,T18,T19
10CoveredT1,T2,T3
11CoveredT19,T5,T26

 LINE       305
 SUB-EXPRESSION (inputs_invalid_i[OpGenSwOut] | inputs_invalid_q[OpGenSwOut])
                 --------------1-------------   --------------2-------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT15,T18,T19

 LINE       307
 EXPRESSION (gen_en_i & (inputs_invalid_i[OpGenHwOut] | inputs_invalid_q[OpGenHwOut]))
             ----1---   ------------------------------2------------------------------
-1--2-StatusTests
01CoveredT15,T18,T19
10CoveredT1,T2,T3
11CoveredT19,T5,T26

 LINE       307
 SUB-EXPRESSION (inputs_invalid_i[OpGenHwOut] | inputs_invalid_q[OpGenHwOut])
                 --------------1-------------   --------------2-------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT15,T18,T19

 LINE       331
 EXPRESSION (((|cmd_error_o)) || inputs_invalid_o || fsm_error_o)
             --------1-------    --------2-------    -----3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT10,T11,T12
010CoveredT19,T5,T26
100CoveredT15,T20,T27

 LINE       333
 EXPRESSION (valid && adv_en_i)
             --1--    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       335
 EXPRESSION (valid && id_en_i)
             --1--    ---2---
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       337
 EXPRESSION (valid && gen_en_i)
             --1--    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT15,T20,T27
11CoveredT1,T2,T3

 LINE       349
 EXPRESSION ((((~kmac_done_vld)) & kmac_data_i.done) | kmac_done_err_q)
             -------------------1-------------------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT1,T2,T3

 LINE       349
 SUB-EXPRESSION (((~kmac_done_vld)) & kmac_data_i.done)
                 ---------1--------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       369
 EXPRESSION ((cmd_chk & (enables_q != enables_d)) | cmd_consty_err_q)
             ------------------1-----------------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT15,T20,T27
10CoveredT15,T20,T27

 LINE       369
 SUB-EXPRESSION (cmd_chk & (enables_q != enables_d))
                 ---1---   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT15,T20,T27

 LINE       369
 SUB-EXPRESSION (enables_q != enables_d)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       375
 EXPRESSION (((|(enables_d & enables_sub))) | one_hot_err_q)
             ---------------1--------------   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T31,T32
10CoveredT22,T31,T32

 LINE       391
 EXPRESSION (one_hot_err_q | cmd_consty_err_q)
             ------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT15,T20,T27
10CoveredT22,T33,T34

 LINE       394
 EXPRESSION (kmac_data_o.valid & kmac_data_i.ready)
             --------1--------   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.u_kmac_if
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StClean 251 Covered T1,T2,T3
StError 280 Covered T10,T11,T12
StIdle 263 Covered T1,T2,T3
StOpWait 242 Covered T1,T2,T3
StTx 208 Covered T1,T2,T3
StTxLast 208 Covered T1,T2,T3


transitionsLine No.CoveredTests
StClean->StError 280 Excluded
StClean->StIdle 263 Covered T1,T2,T3
StIdle->StError 280 Covered T10,T11,T12
StIdle->StTx 208 Covered T1,T2,T3
StIdle->StTxLast 208 Excluded
StOpWait->StClean 251 Covered T1,T2,T3
StOpWait->StError 280 Excluded
StTx->StError 280 Excluded
StTx->StTxLast 222 Covered T1,T2,T3
StTxLast->StError 280 Excluded
StTxLast->StOpWait 242 Covered T1,T2,T3



Branch Coverage for Instance : tb.dut.u_kmac_if
Line No.TotalCoveredPercent
Branches 42 39 92.86
TERNARY 287 2 2 100.00
IF 161 2 2 100.00
IF 169 2 2 100.00
CASE 190 21 18 85.71
IF 279 2 2 100.00
IF 298 3 3 100.00
IF 331 5 5 100.00
IF 363 3 3 100.00
IF 379 2 2 100.00


287 assign data_o = start && done_o ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


161 if (!rst_ni) begin -1- 162 inputs_invalid_q <= '0; ==> 163 end else begin 164 inputs_invalid_q <= inputs_invalid_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


169 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, data_state_e, StIdle) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


190 unique case (state_q) -1- 191 192 StIdle: begin 193 // if for some reason multiple bits are set, adv_en has priority 194 // as the current key state will be destroyed 195 196 // cross check for commands once transaction begins 197 cmd_chk = '0; 198 if (start) begin -2- 199 cnt_set = 1'b1; 200 if (adv_en_i) begin -3- 201 rounds = LastAdvRound; ==> 202 end else if (id_en_i) begin -4- 203 rounds = LastIdRound; ==> 204 end else if (gen_en_i) begin -5- 205 rounds = LastGenRound; ==> 206 end MISSING_ELSE ==> 207 // in case we are sending only 1 entry 208 state_d = (rounds == 0) ? StTxLast : StTx; -6- ==> ==> 209 end MISSING_ELSE ==> 210 end 211 212 StTx: begin 213 valid = 1'b1; 214 strb = {IfBytes{1'b1}}; 215 216 // transaction accepted 217 if (kmac_data_i.ready) begin -7- 218 cnt_en = 1'b1; 219 220 // second to last beat 221 if (cnt == CntWidth'(1'b1)) begin -8- 222 state_d = StTxLast; ==> 223 end MISSING_ELSE ==> 224 end MISSING_ELSE ==> 225 226 end 227 228 StTxLast: begin 229 valid = 1'b1; 230 last = 1'b1; 231 232 if (adv_en_i) begin -9- 233 strb = AdvByteMask; ==> 234 end else if (id_en_i) begin -10- 235 strb = IdByteMask; ==> 236 end else if (gen_en_i) begin -11- 237 strb = GenByteMask; ==> 238 end MISSING_ELSE ==> 239 240 // transaction accepted 241 cnt_clr = kmac_data_i.ready; 242 state_d = kmac_data_i.ready ? StOpWait : StTxLast; -12- ==> ==> 243 244 end 245 246 StOpWait: begin 247 kmac_done_vld = 1'b1; 248 if (kmac_data_i.done) begin -13- 249 kmac_error_o = kmac_data_i.error; ==> 250 done_o = 1'b1; 251 state_d = StClean; 252 end MISSING_ELSE ==> 253 end 254 255 StClean: begin 256 cmd_chk = '0; 257 done_o = 1'b1; 258 259 // wait for control side to ack done by waiting start de-assertion 260 if (!start) begin -14- 261 done_o = 1'b0; ==> 262 clr_err = 1'b1; 263 state_d = StIdle; 264 end MISSING_ELSE ==> 265 end 266 267 // trigger error 268 default: begin 269 // This state is terminal 270 done_o = 1'b1; ==>

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTests
StIdle 1 1 - - - - - - - - - - - Covered T1,T2,T3
StIdle 1 0 1 - - - - - - - - - - Covered T1,T2,T4
StIdle 1 0 0 1 - - - - - - - - - Covered T1,T2,T3
StIdle 1 0 0 0 - - - - - - - - - Not Covered
StIdle 1 - - - 1 - - - - - - - - Not Covered
StIdle 1 - - - 0 - - - - - - - - Covered T1,T2,T3
StIdle 0 - - - - - - - - - - - - Covered T1,T2,T3
StTx - - - - - 1 1 - - - - - - Covered T1,T2,T3
StTx - - - - - 1 0 - - - - - - Covered T1,T2,T3
StTx - - - - - 0 - - - - - - - Covered T2,T3,T4
StTxLast - - - - - - - 1 - - - - - Covered T1,T2,T3
StTxLast - - - - - - - 0 1 - - - - Covered T1,T2,T4
StTxLast - - - - - - - 0 0 1 - - - Covered T1,T2,T3
StTxLast - - - - - - - 0 0 0 - - - Covered T15,T20,T27
StTxLast - - - - - - - - - - 1 - - Covered T1,T2,T3
StTxLast - - - - - - - - - - 0 - - Covered T2,T3,T4
StOpWait - - - - - - - - - - - 1 - Covered T1,T2,T3
StOpWait - - - - - - - - - - - 0 - Covered T1,T2,T3
StClean - - - - - - - - - - - - 1 Covered T1,T2,T3
StClean - - - - - - - - - - - - 0 Not Covered
default - - - - - - - - - - - - - Covered T10,T11,T12


279 if (cnt_err) begin -1- 280 state_d = StError; ==> 281 fsm_error_o = 1; 282 done_o = 1'b1; 283 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3


298 if (clr_err) begin -1- 299 inputs_invalid_d = '0; ==> 300 end else if (valid) begin -2- 301 inputs_invalid_d[OpAdvance] = adv_en_i & (inputs_invalid_i[OpAdvance] | ==> 302 inputs_invalid_q[OpAdvance]); 303 inputs_invalid_d[OpGenId] = id_en_i & (inputs_invalid_i[OpGenId] | 304 inputs_invalid_q[OpGenId]); 305 inputs_invalid_d[OpGenSwOut] = gen_en_i & (inputs_invalid_i[OpGenSwOut]| 306 inputs_invalid_q[OpGenSwOut]); 307 inputs_invalid_d[OpGenHwOut] = gen_en_i & (inputs_invalid_i[OpGenHwOut]| 308 inputs_invalid_q[OpGenHwOut]); 309 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


331 if (|cmd_error_o || inputs_invalid_o || fsm_error_o) begin -1- 332 kmac_data_o.data = decoy_data; ==> 333 end else if (valid && adv_en_i) begin -2- 334 kmac_data_o.data = adv_data[adv_sel]; ==> 335 end else if (valid && id_en_i) begin -3- 336 kmac_data_o.data = id_data[id_sel]; ==> 337 end else if (valid && gen_en_i) begin -4- 338 kmac_data_o.data = gen_data[gen_sel]; ==> 339 end MISSING_ELSE ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T15,T19,T10
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T2,T4
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3


363 if (!rst_ni) begin -1- 364 enables_q <= '0; ==> 365 end else if (cnt_set) begin -2- 366 enables_q <= enables_d; ==> 367 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


379 if (!rst_ni) begin -1- 380 one_hot_err_q <= '0; ==> 381 kmac_done_err_q <= '0; 382 cmd_consty_err_q <= '0; 383 end else begin 384 one_hot_err_q <= one_hot_err_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_kmac_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AdvRemBytes_A 875 875 0 0
GenRemBytes_A 875 875 0 0
IdRemBytes_A 875 875 0 0
LastStrb_A 21286633 13894069 0 0
u_state_regs_A 21705443 21550665 0 0


AdvRemBytes_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 875 875 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

GenRemBytes_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 875 875 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

IdRemBytes_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 875 875 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

LastStrb_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21286633 13894069 0 0
T1 5456 338 0 0
T2 18058 13621 0 0
T3 17046 11694 0 0
T4 5438 2296 0 0
T13 1307 0 0 0
T14 4324 0 0 0
T15 2423 102 0 0
T16 4832 338 0 0
T17 9788 4343 0 0
T18 11952 3161 0 0
T35 0 4605 0 0
T36 0 18229 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21705443 21550665 0 0
T1 5456 5398 0 0
T2 18058 17959 0 0
T3 17046 16955 0 0
T4 5438 5384 0 0
T13 1307 1207 0 0
T14 4324 4161 0 0
T15 4964 4817 0 0
T16 4832 4772 0 0
T17 9788 9733 0 0
T18 11952 11877 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%