KMAC/MASKED Simulation Results

Wednesday May 17 2023 07:05:42 UTC

GitHub Revision: `3df77bec1`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 2320738200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.523m	37.624ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.030s	21.561us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.200s	160.485us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	23.160s	2.456ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.340s	614.821us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.620s	118.881us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.200s	160.485us	20	20	100.00
		kmac_csr_aliasing	9.340s	614.821us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.800s	23.093us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.640s	168.820us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	56.254m	253.006ms	49	50	98.00
V2	burst_write	kmac_burst_write	25.377m	54.264ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	44.206m	403.212ms	50	50	100.00
		kmac_test_vectors_sha3_256	39.643m	366.698ms	50	50	100.00
		kmac_test_vectors_sha3_384	31.720m	542.569ms	49	50	98.00
		kmac_test_vectors_sha3_512	23.630m	101.545ms	49	50	98.00
		kmac_test_vectors_shake_128	1.940h	1.459s	50	50	100.00
		kmac_test_vectors_shake_256	1.596h	879.218ms	50	50	100.00
		kmac_test_vectors_kmac	7.850s	2.455ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.070s	532.179us	50	50	100.00
V2	sideload	kmac_sideload	9.414m	87.692ms	50	50	100.00
V2	app	kmac_app	7.338m	65.509ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.224m	38.948ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	6.980m	115.745ms	47	50	94.00
V2	error	kmac_error	8.459m	30.413ms	50	50	100.00
V2	key_error	kmac_key_error	8.000s	2.576ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	50.080s	3.180ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	35.180s	1.104ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.232m	26.670ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	50.750s	1.823ms	50	50	100.00
V2	stress_all	kmac_stress_all	51.387m	453.671ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.870s	24.448us	50	50	100.00
V2	alert_test	kmac_alert_test	0.960s	39.530us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.610s	445.034us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.610s	445.034us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.030s	21.561us	5	5	100.00
		kmac_csr_rw	1.200s	160.485us	20	20	100.00
		kmac_csr_aliasing	9.340s	614.821us	5	5	100.00
		kmac_same_csr_outstanding	3.080s	932.020us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.030s	21.561us	5	5	100.00
		kmac_csr_rw	1.200s	160.485us	20	20	100.00
		kmac_csr_aliasing	9.340s	614.821us	5	5	100.00
		kmac_same_csr_outstanding	3.080s	932.020us	20	20	100.00
V2		TOTAL			1039	1050	98.95
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.200s	120.848us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.200s	120.848us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.200s	120.848us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.200s	120.848us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	6.230s	1.181ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.131m	50.589ms	5	5	100.00
		kmac_tl_intg_err	5.860s	1.227ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.860s	1.227ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	50.750s	1.823ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.523m	37.624ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	9.414m	87.692ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.200s	120.848us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.131m	50.589ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.131m	50.589ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.131m	50.589ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.523m	37.624ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	50.750s	1.823ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.131m	50.589ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.644m	200.000ms	8	10	80.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.523m	37.624ms	49	50	98.00
V2S		TOTAL			73	75	97.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.082h	205.766ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			1261	1290	97.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	18	72.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.04	98.40	93.36	99.93	94.55	96.03	98.87	98.17

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 11 failures:

Test kmac_stress_all_with_rand_reset has 11 failures.

0.kmac_stress_all_with_rand_reset.2301952305
Line 251, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @   9474086 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @   9474086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.kmac_stress_all_with_rand_reset.463171846
Line 455, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8175805801 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 8175805801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 6 failures:

Test kmac_app_with_partial_data has 1 failures.

6.kmac_app_with_partial_data.1053067647
Line 292, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 14773556773 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (127 [0x7f] vs 0 [0x0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 14773556773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_mubi has 1 failures.

7.kmac_mubi.1051336205
Line 258, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_mubi/latest/run.log

  UVM_FATAL @ 1279438167 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (96 [0x60] vs 18 [0x12]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1279438167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

28.kmac_stress_all.1900764769
Line 424, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_stress_all/latest/run.log

  UVM_FATAL @ 7542022219 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (97 [0x61] vs 103 [0x67]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7542022219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 3 failures.

40.kmac_entropy_refresh.2102549067
Line 268, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 9489648379 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (162 [0xa2] vs 211 [0xd3]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 9489648379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.kmac_entropy_refresh.4013399655
Line 304, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 25334610424 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (64 [0x40] vs 3 [0x3]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 25334610424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 4 failures:

Test kmac_stress_all has 2 failures.

12.kmac_stress_all.3854697596
Line 383, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_stress_all/latest/run.log

  UVM_FATAL @ 37124717318 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 37124717318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.kmac_stress_all.3344029216
Line 599, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_stress_all/latest/run.log

  UVM_FATAL @ 217884552376 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 217884552376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all_with_rand_reset has 2 failures.

14.kmac_stress_all_with_rand_reset.940364859
Line 584, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 65335247344 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 65335247344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.kmac_stress_all_with_rand_reset.2869643836
Line 320, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 20820914211 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 20820914211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:

Test kmac_test_vectors_sha3_512 has 1 failures.

3.kmac_test_vectors_sha3_512.1506369044
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_512/latest/run.log

  UVM_ERROR @  39755159 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  39755159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_smoke has 1 failures.

26.kmac_smoke.939287673
Line 243, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_smoke/latest/run.log

  UVM_ERROR @  73347386 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  73347386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_384 has 1 failures.

28.kmac_test_vectors_sha3_384.3791307255
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_test_vectors_sha3_384/latest/run.log

  UVM_ERROR @  67252698 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  67252698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test kmac_mubi has 1 failures.

1.kmac_mubi.4075751778
Line 403, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_mubi/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_burst_write has 1 failures.

48.kmac_burst_write.1841973085
Line 339, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_test_vectors_base_vseq.sv:125) [kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (* [*] vs * [*]) Mismatch between exp_digest[*] and act_digest[*] has 2 failures:

Test kmac_stress_all_with_rand_reset has 2 failures.

4.kmac_stress_all_with_rand_reset.964081525
Line 377, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 197372069669 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (49 [0x31] vs 135 [0x87]) Mismatch between exp_digest[0] and act_digest[0]
  UVM_INFO @ 197372069669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.kmac_stress_all_with_rand_reset.1689088424
Line 1143, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 201186909607 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (49 [0x31] vs 18 [0x12]) Mismatch between exp_digest[0] and act_digest[0]
  UVM_INFO @ 201186909607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_long_msg_and_output has 1 failures.
  - 3.kmac_long_msg_and_output.110934802
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:48a91ab0-00fe-4a7d-92db-a5599c351b62
```