Unified Coverage Report :: Module :: kmac_core

Module : kmac_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.30	98.68	92.86		75.00	91.07	88.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_kmac_core	91.44	98.68	92.86		85.71	91.07	88.89

---

Module Instance : tb.dut.u_kmac_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.44	98.68	92.86		85.71	91.07	88.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.42	98.88	92.86	100.00	85.71	91.38	91.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	98.77	96.05	100.00	76.92	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_key_slicer[0].u_key_slicer	100.00	100.00					100.00
gen_key_slicer[1].u_key_slicer	100.00	100.00					100.00
u_key_index_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
TOTAL		76	75	98.68
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	3	3	100.00
ALWAYS	164	30	30	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
ALWAYS	266	6	5	83.33
CONT_ASSIGN	285	1	1	100.00
ALWAYS	305	6	6	100.00
ALWAYS	336	6	6	100.00
ALWAYS	336	6	6	100.00
CONT_ASSIGN	370	1	1	100.00
CONT_ASSIGN	373	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
ALWAYS	417	6	6	100.00
CONT_ASSIGN	428	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
151	1	1
159	3	3
164	1	1
166	1	1
167	1	1
169	1	1
171	1	1
172	1	1
174	1	1
176	1	1
178	1	1
179	1	1
181	1	1
188	1	1
189	1	1
191	1	1
192	1	1
194	1	1
195	1	1
197	1	1
199	1	1
205	1	1
206	1	1
208	1	1
210	1	1
215	1	1
216	1	1
218	1	1
224	1	1
225	1	1
238	1	1
239	1	1
			MISSING_ELSE
249	1	1
250	1	1
251	1	1
252	1	1
256	1	1
258	1	1
263	1	1
266	1	1
267	1	1
268	1	1
269	0	1
270	1	1
272	1	1
			MISSING_ELSE
285	1	1
305	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
336	1	1
339	1	1
343	1	1
347	1	1
351	1	1
356	1	1
336	1	1
339	1	1
343	1	1
347	1	1
351	1	1
356	1	1
370	1	1
373	1	1
392	1	1
417	1	1
418	1	1
419	1	1
420	1	1
421	1	1
422	1	1
428	1	1

---

Cond Coverage for Module : kmac_core

	Total	Covered	Percent
Conditions	28	26	92.86
Logical	28	26	92.86
Non-Logical	0	0
Event	0	0

 LINE       178
 EXPRESSION (kmac_en_i && start_i)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T22,T36,T30
1	1	Covered	T22,T30,T31

 LINE       205
 EXPRESSION (process_i || process_latched)
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T22,T30,T31
0	1	Not Covered
1	0	Covered	T22,T30,T31

 LINE       249
 EXPRESSION (en_kmac_datapath ? kmac_valid : fifo_valid_i)
             --------1-------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T22,T30,T31

 LINE       250
 EXPRESSION (en_kmac_datapath ? kmac_data : fifo_data_i)
             --------1-------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T22,T30,T31

 LINE       251
 EXPRESSION (en_kmac_datapath ? kmac_strb : fifo_strb_i)
             --------1-------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T22,T30,T31

 LINE       252
 EXPRESSION (en_kmac_datapath ? 1'b0 : msg_ready_i)
             --------1-------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T22,T30,T31

 LINE       256
 EXPRESSION (en_key_write ? '1 : '0)
             ------1-----

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T22,T30,T31

 LINE       258
 EXPRESSION (en_key_write ? key_sliced : ('{(*adjust*)default:'0}))
             ------1-----

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T22,T30,T31

 LINE       263
 EXPRESSION (kmac_en_i ? kmac_process : process_i)
             ----1----

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T22,T36,T30

 LINE       268
 EXPRESSION (process_i && ((!process_o)))
             ----1----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Not Covered

 LINE       392
 EXPRESSION (kmac_valid & msg_ready_i)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T22,T30,T31
1	1	Covered	T22,T30,T31

 LINE       428
 EXPRESSION (key_index == block_addr_limit)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T22,T30,T31

---

FSM Coverage for Module : kmac_core

Summary for FSM :: st

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	8	6	75.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StKey	179	Covered	T17
StKmacFlush	206	Covered	T17
StKmacIdle	181	Covered	T17
StKmacMsg	192	Covered	T17
StTerminalError	239	Covered	T17

transitions	Line No.	Covered	Tests
StKey->StKmacMsg	192	Covered	T17
StKey->StTerminalError	239	Covered	T17
StKmacFlush->StKmacIdle	216	Covered	T17
StKmacFlush->StTerminalError	239	Not Covered
StKmacIdle->StKey	179	Covered	T17
StKmacIdle->StTerminalError	239	Covered	T17
StKmacMsg->StKmacFlush	206	Covered	T17
StKmacMsg->StTerminalError	239	Not Covered

---

Branch Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
Branches		56	51	91.07
TERNARY	249	2	2	100.00
TERNARY	250	2	2	100.00
TERNARY	251	2	2	100.00
TERNARY	252	2	2	100.00
TERNARY	256	2	2	100.00
TERNARY	258	2	2	100.00
TERNARY	263	2	2	100.00
IF	159	2	2	100.00
CASE	176	10	10	100.00
IF	238	2	2	100.00
IF	266	4	3	75.00
CASE	305	6	5	83.33
CASE	417	6	5	83.33
CASE	336	6	5	83.33
CASE	336	6	5	83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	249	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T30,T31
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	250	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T30,T31
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	251	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T30,T31
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	252	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T30,T31
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	256	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T30,T31
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	258	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T30,T31
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	263	(kmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T36,T30
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	159	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	176	case (st)
-2-:	178	if ((kmac_en_i && start_i))
-3-:	191	if (sent_blocksize)
-4-:	205	if ((process_i || process_latched))
-5-:	215	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StKmacIdle	1	-	-	-	Covered	T22,T30,T31
StKmacIdle	0	-	-	-	Covered	T20,T21,T22
StKey	-	1	-	-	Covered	T22,T30,T31
StKey	-	0	-	-	Covered	T22,T30,T31
StKmacMsg	-	-	1	-	Covered	T22,T30,T31
StKmacMsg	-	-	0	-	Covered	T22,T30,T31
StKmacFlush	-	-	-	1	Covered	T22,T30,T31
StKmacFlush	-	-	-	0	Covered	T22,T30,T31
StTerminalError	-	-	-	-	Covered	T24,T25,T26
default	-	-	-	-	Covered	T27,T28,T29

	LineNo.	Expression
-1-:	238	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	266	if ((!rst_ni))
-2-:	268	if ((process_i && (!process_o)))
-3-:	270	if ((process_o || prim_mubi_pkg::mubi4_test_true_strict(done_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T20,T21,T22
0	1	-	Not Covered
0	0	1	Covered	T20,T21,T22
0	0	0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	305	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T20,T21,T22
Key192	Covered	T20,T21,T22
Key256	Covered	T20,T21,T22
Key384	Covered	T20,T21,T22
Key512	Covered	T20,T21,T22
default	Not Covered

	LineNo.	Expression
-1-:	417	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T20,T21,T22
L224	Covered	T30,T31,T23
L256	Covered	T20,T21,T22
L384	Covered	T22,T30,T31
L512	Covered	T20,T36,T30
default	Not Covered

	LineNo.	Expression
-1-:	336	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T20,T21,T22
Key192	Covered	T20,T21,T22
Key256	Covered	T20,T21,T22
Key384	Covered	T20,T21,T22
Key512	Covered	T20,T21,T22
default	Not Covered

	LineNo.	Expression
-1-:	336	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T20,T21,T22
Key192	Covered	T20,T21,T22
Key256	Covered	T20,T21,T22
Key384	Covered	T20,T21,T22
Key512	Covered	T20,T21,T22
default	Not Covered

---

Assert Coverage for Module : kmac_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	8	88.89
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	8	88.89

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckOnlyInMessageState_A	2147483647	4902090	0	0
KeyDataStable_M	2147483647	783180	0	0
KeyLengthStable_M	2147483647	271000	0	0
KmacEnStable_M	2147483647	17140	0	0
MaxKeyLenMatchToKey512_A	1025	1025	0	0
ModeStable_M	2147483647	25550	0	0
ProcessLatchedCleared_A	2147483647	0	0	0
StrengthStable_M	2147483647	31955	0	0
u_state_regs_A	2147483647	2147483647	0	0

AckOnlyInMessageState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4902090	0	0
T22	407548	2078	0	0
T23	657052	0	0	0
T24	4074	0	0	0
T30	264362	25148	0	0
T31	455721	3340	0	0
T32	830486	28155	0	0
T33	340300	1860	0	0
T34	151249	0	0	0
T35	179590	0	0	0
T36	3631	0	0	0
T47	0	28155	0	0
T48	0	1860	0	0
T49	0	34236	0	0
T50	0	28155	0	0
T51	0	3340	0	0

KeyDataStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	783180	0	0
T22	407548	824	0	0
T23	657052	0	0	0
T24	4074	32	0	0
T30	264362	5926	0	0
T31	455721	1594	0	0
T32	830486	1408	0	0
T33	340300	534	0	0
T34	151249	0	0	0
T35	179590	0	0	0
T36	3631	0	0	0
T46	0	612	0	0
T47	0	1408	0	0
T48	0	534	0	0
T49	0	1568	0	0

KeyLengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	271000	0	0
T20	321999	202	0	0
T21	151249	1811	0	0
T22	407548	74	0	0
T23	657052	317	0	0
T30	264362	226	0	0
T31	455721	61	0	0
T32	830486	45	0	0
T33	340300	82	0	0
T34	151249	1811	0	0
T36	3631	14	0	0

KmacEnStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17140	0	0
T22	407548	34	0	0
T23	657052	0	0	0
T24	4074	1	0	0
T30	264362	106	0	0
T31	455721	17	0	0
T32	830486	21	0	0
T33	340300	31	0	0
T34	151249	0	0	0
T35	179590	0	0	0
T36	3631	18	0	0
T46	0	36	0	0
T47	0	21	0	0
T48	0	31	0	0

MaxKeyLenMatchToKey512_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T36	1	1	0	0

ModeStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	25550	0	0
T21	151249	1	0	0
T22	407548	66	0	0
T23	657052	0	0	0
T24	0	1	0	0
T30	264362	154	0	0
T31	455721	28	0	0
T32	830486	21	0	0
T33	340300	70	0	0
T34	151249	1	0	0
T35	179590	1	0	0
T36	3631	34	0	0

ProcessLatchedCleared_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

StrengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	31955	0	0
T20	321999	2	0	0
T21	151249	2	0	0
T22	407548	61	0	0
T23	657052	2	0	0
T30	264362	197	0	0
T31	455721	48	0	0
T32	830486	31	0	0
T33	340300	69	0	0
T34	151249	2	0	0
T36	3631	27	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T20	321999	321993	0	0
T21	151249	151248	0	0
T22	407548	407486	0	0
T23	657052	657046	0	0
T30	264362	264291	0	0
T31	455721	455659	0	0
T32	830486	830424	0	0
T33	340300	340238	0	0
T34	151249	151248	0	0
T36	3631	3569	0	0

Line Coverage for Instance : tb.dut.u_kmac_core

	Line No.	Total	Covered	Percent
TOTAL		76	75	98.68
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	3	3	100.00
ALWAYS	164	30	30	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
ALWAYS	266	6	5	83.33
CONT_ASSIGN	285	1	1	100.00
ALWAYS	305	6	6	100.00
ALWAYS	336	6	6	100.00
ALWAYS	336	6	6	100.00
CONT_ASSIGN	370	1	1	100.00
CONT_ASSIGN	373	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
ALWAYS	417	6	6	100.00
CONT_ASSIGN	428	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
151	1	1
159	3	3
164	1	1
166	1	1
167	1	1
169	1	1
171	1	1
172	1	1
174	1	1
176	1	1
178	1	1
179	1	1
181	1	1
188	1	1
189	1	1
191	1	1
192	1	1
194	1	1
195	1	1
197	1	1
199	1	1
205	1	1
206	1	1
208	1	1
210	1	1
215	1	1
216	1	1
218	1	1
224	1	1
225	1	1
238	1	1
239	1	1
			MISSING_ELSE
249	1	1
250	1	1
251	1	1
252	1	1
256	1	1
258	1	1
263	1	1
266	1	1
267	1	1
268	1	1
269	0	1
270	1	1
272	1	1
			MISSING_ELSE
285	1	1
305	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
336	1	1
339	1	1
343	1	1
347	1	1
351	1	1
356	1	1
336	1	1
339	1	1
343	1	1
347	1	1
351	1	1
356	1	1
370	1	1
373	1	1
392	1	1
417	1	1
418	1	1
419	1	1
420	1	1
421	1	1
422	1	1
428	1	1

---

Cond Coverage for Instance : tb.dut.u_kmac_core

	Total	Covered	Percent
Conditions	28	26	92.86
Logical	28	26	92.86
Non-Logical	0	0
Event	0	0

 LINE       178
 EXPRESSION (kmac_en_i && start_i)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T22,T36,T30
1	1	Covered	T22,T30,T31

 LINE       205
 EXPRESSION (process_i || process_latched)
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T22,T30,T31
0	1	Not Covered
1	0	Covered	T22,T30,T31

 LINE       249
 EXPRESSION (en_kmac_datapath ? kmac_valid : fifo_valid_i)
             --------1-------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T22,T30,T31

 LINE       250
 EXPRESSION (en_kmac_datapath ? kmac_data : fifo_data_i)
             --------1-------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T22,T30,T31

 LINE       251
 EXPRESSION (en_kmac_datapath ? kmac_strb : fifo_strb_i)
             --------1-------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T22,T30,T31

 LINE       252
 EXPRESSION (en_kmac_datapath ? 1'b0 : msg_ready_i)
             --------1-------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T22,T30,T31

 LINE       256
 EXPRESSION (en_key_write ? '1 : '0)
             ------1-----

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T22,T30,T31

 LINE       258
 EXPRESSION (en_key_write ? key_sliced : ('{(*adjust*)default:'0}))
             ------1-----

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T22,T30,T31

 LINE       263
 EXPRESSION (kmac_en_i ? kmac_process : process_i)
             ----1----

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T22,T36,T30

 LINE       268
 EXPRESSION (process_i && ((!process_o)))
             ----1----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Not Covered

 LINE       392
 EXPRESSION (kmac_valid & msg_ready_i)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T22,T30,T31
1	1	Covered	T22,T30,T31

 LINE       428
 EXPRESSION (key_index == block_addr_limit)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T22,T30,T31

---

FSM Coverage for Instance : tb.dut.u_kmac_core

Summary for FSM :: st

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	6	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StKey	179	Covered	T17
StKmacFlush	206	Covered	T17
StKmacIdle	181	Covered	T17
StKmacMsg	192	Covered	T17
StTerminalError	239	Covered	T17

transitions	Line No.	Covered	Tests	Exclude Annotation
StKey->StKmacMsg	192	Covered	T17
StKey->StTerminalError	239	Covered	T17
StKmacFlush->StKmacIdle	216	Covered	T17
StKmacFlush->StTerminalError	239	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StKmacIdle->StKey	179	Covered	T17
StKmacIdle->StTerminalError	239	Covered	T17
StKmacMsg->StKmacFlush	206	Covered	T17
StKmacMsg->StTerminalError	239	Not Covered

---

Branch Coverage for Instance : tb.dut.u_kmac_core

	Line No.	Total	Covered	Percent
Branches		56	51	91.07
TERNARY	249	2	2	100.00
TERNARY	250	2	2	100.00
TERNARY	251	2	2	100.00
TERNARY	252	2	2	100.00
TERNARY	256	2	2	100.00
TERNARY	258	2	2	100.00
TERNARY	263	2	2	100.00
IF	159	2	2	100.00
CASE	176	10	10	100.00
IF	238	2	2	100.00
IF	266	4	3	75.00
CASE	305	6	5	83.33
CASE	417	6	5	83.33
CASE	336	6	5	83.33
CASE	336	6	5	83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	249	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T30,T31
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	250	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T30,T31
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	251	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T30,T31
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	252	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T30,T31
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	256	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T30,T31
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	258	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T30,T31
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	263	(kmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T36,T30
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	159	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	176	case (st)
-2-:	178	if ((kmac_en_i && start_i))
-3-:	191	if (sent_blocksize)
-4-:	205	if ((process_i || process_latched))
-5-:	215	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StKmacIdle	1	-	-	-	Covered	T22,T30,T31
StKmacIdle	0	-	-	-	Covered	T20,T21,T22
StKey	-	1	-	-	Covered	T22,T30,T31
StKey	-	0	-	-	Covered	T22,T30,T31
StKmacMsg	-	-	1	-	Covered	T22,T30,T31
StKmacMsg	-	-	0	-	Covered	T22,T30,T31
StKmacFlush	-	-	-	1	Covered	T22,T30,T31
StKmacFlush	-	-	-	0	Covered	T22,T30,T31
StTerminalError	-	-	-	-	Covered	T24,T25,T26
default	-	-	-	-	Covered	T27,T28,T29

	LineNo.	Expression
-1-:	238	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	266	if ((!rst_ni))
-2-:	268	if ((process_i && (!process_o)))
-3-:	270	if ((process_o || prim_mubi_pkg::mubi4_test_true_strict(done_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T20,T21,T22
0	1	-	Not Covered
0	0	1	Covered	T20,T21,T22
0	0	0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	305	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T20,T21,T22
Key192	Covered	T20,T21,T22
Key256	Covered	T20,T21,T22
Key384	Covered	T20,T21,T22
Key512	Covered	T20,T21,T22
default	Not Covered

	LineNo.	Expression
-1-:	417	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T20,T21,T22
L224	Covered	T30,T31,T23
L256	Covered	T20,T21,T22
L384	Covered	T22,T30,T31
L512	Covered	T20,T36,T30
default	Not Covered

	LineNo.	Expression
-1-:	336	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T20,T21,T22
Key192	Covered	T20,T21,T22
Key256	Covered	T20,T21,T22
Key384	Covered	T20,T21,T22
Key512	Covered	T20,T21,T22
default	Not Covered

	LineNo.	Expression
-1-:	336	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T20,T21,T22
Key192	Covered	T20,T21,T22
Key256	Covered	T20,T21,T22
Key384	Covered	T20,T21,T22
Key512	Covered	T20,T21,T22
default	Not Covered

---

Assert Coverage for Instance : tb.dut.u_kmac_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	8	88.89
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	8	88.89

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckOnlyInMessageState_A	2147483647	4902090	0	0
KeyDataStable_M	2147483647	783180	0	0
KeyLengthStable_M	2147483647	271000	0	0
KmacEnStable_M	2147483647	17140	0	0
MaxKeyLenMatchToKey512_A	1025	1025	0	0
ModeStable_M	2147483647	25550	0	0
ProcessLatchedCleared_A	2147483647	0	0	0
StrengthStable_M	2147483647	31955	0	0
u_state_regs_A	2147483647	2147483647	0	0

AckOnlyInMessageState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4902090	0	0
T22	407548	2078	0	0
T23	657052	0	0	0
T24	4074	0	0	0
T30	264362	25148	0	0
T31	455721	3340	0	0
T32	830486	28155	0	0
T33	340300	1860	0	0
T34	151249	0	0	0
T35	179590	0	0	0
T36	3631	0	0	0
T47	0	28155	0	0
T48	0	1860	0	0
T49	0	34236	0	0
T50	0	28155	0	0
T51	0	3340	0	0

KeyDataStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	783180	0	0
T22	407548	824	0	0
T23	657052	0	0	0
T24	4074	32	0	0
T30	264362	5926	0	0
T31	455721	1594	0	0
T32	830486	1408	0	0
T33	340300	534	0	0
T34	151249	0	0	0
T35	179590	0	0	0
T36	3631	0	0	0
T46	0	612	0	0
T47	0	1408	0	0
T48	0	534	0	0
T49	0	1568	0	0

KeyLengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	271000	0	0
T20	321999	202	0	0
T21	151249	1811	0	0
T22	407548	74	0	0
T23	657052	317	0	0
T30	264362	226	0	0
T31	455721	61	0	0
T32	830486	45	0	0
T33	340300	82	0	0
T34	151249	1811	0	0
T36	3631	14	0	0

KmacEnStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17140	0	0
T22	407548	34	0	0
T23	657052	0	0	0
T24	4074	1	0	0
T30	264362	106	0	0
T31	455721	17	0	0
T32	830486	21	0	0
T33	340300	31	0	0
T34	151249	0	0	0
T35	179590	0	0	0
T36	3631	18	0	0
T46	0	36	0	0
T47	0	21	0	0
T48	0	31	0	0

MaxKeyLenMatchToKey512_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T36	1	1	0	0

ModeStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	25550	0	0
T21	151249	1	0	0
T22	407548	66	0	0
T23	657052	0	0	0
T24	0	1	0	0
T30	264362	154	0	0
T31	455721	28	0	0
T32	830486	21	0	0
T33	340300	70	0	0
T34	151249	1	0	0
T35	179590	1	0	0
T36	3631	34	0	0

ProcessLatchedCleared_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

StrengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	31955	0	0
T20	321999	2	0	0
T21	151249	2	0	0
T22	407548	61	0	0
T23	657052	2	0	0
T30	264362	197	0	0
T31	455721	48	0	0
T32	830486	31	0	0
T33	340300	69	0	0
T34	151249	2	0	0
T36	3631	27	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T20	321999	321993	0	0
T21	151249	151248	0	0
T22	407548	407486	0	0
T23	657052	657046	0	0
T30	264362	264291	0	0
T31	455721	455659	0	0
T32	830486	830424	0	0
T33	340300	340238	0	0
T34	151249	151248	0	0
T36	3631	3569	0	0