Unified Coverage Report :: Module :: kmac

Module : kmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.72	98.77	96.05	100.00	76.92	96.55	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.72	98.77	96.05	100.00	76.92	96.55	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.72	98.77	96.05	100.00	76.92	96.55	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.00	98.10	88.18	99.93	80.00	95.24	96.52

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_entropy.u_entropy	95.99	99.75	90.96	100.00	87.50	97.73	100.00
gen_entropy.u_prim_sync_reqack_data	95.83	100.00	83.33			100.00	100.00
intr_fifo_empty	93.75	100.00	75.00			100.00	100.00
intr_kmac_done	93.75	100.00	75.00			100.00	100.00
intr_kmac_err	93.75	100.00	75.00			100.00	100.00
kmac_csr_assert	7.14						7.14
sha3pad_assert_cov_if	100.00						100.00
tlul_assert_device	95.00	100.00				85.71	99.30
u_app_intf	95.70	96.60	89.80		94.44	97.65	100.00
u_errchk	91.75	93.83	93.24		80.00	91.67	100.00
u_kmac_core	93.42	98.88	92.86	100.00	85.71	91.38	91.67
u_msgfifo	97.32	100.00	95.16	94.52	100.00	94.23	100.00
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_reg	97.97	99.41	91.49	100.00		98.94	100.00
u_sha3	93.24	98.57	95.67	100.00	69.05	96.12	100.00
u_sha3_done_sender	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00
u_staterd	85.34	88.14	69.17			84.04	100.00
u_tlul_adapter_msgfifo	76.20	85.90	64.49			73.17	81.25

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac

	Line No.	Total	Covered	Percent
TOTAL		163	161	98.77
ALWAYS	346	0	0
ALWAYS	346	2	2	100.00
ALWAYS	352	1	0	0.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
ALWAYS	429	9	9	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
ALWAYS	488	6	6	100.00
ALWAYS	501	6	6	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	528	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	537	1	1	100.00
CONT_ASSIGN	539	1	1	100.00
CONT_ASSIGN	541	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
ALWAYS	563	5	5	100.00
CONT_ASSIGN	573	1	1	100.00
CONT_ASSIGN	580	1	1	100.00
CONT_ASSIGN	581	1	1	100.00
CONT_ASSIGN	582	1	1	100.00
CONT_ASSIGN	592	1	1	100.00
ALWAYS	612	3	3	100.00
CONT_ASSIGN	616	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	643	7	7	100.00
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	684	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	701	1	1	100.00
ALWAYS	721	3	3	100.00
ALWAYS	725	28	28	100.00
ALWAYS	863	3	3	100.00
CONT_ASSIGN	871	1	1	100.00
CONT_ASSIGN	871	1	1	100.00
CONT_ASSIGN	942	1	1	100.00
CONT_ASSIGN	944	1	1	100.00
CONT_ASSIGN	974	1	1	100.00
CONT_ASSIGN	979	1	1	100.00
CONT_ASSIGN	980	1	1	100.00
CONT_ASSIGN	982	1	1	100.00
CONT_ASSIGN	985	0	0
ALWAYS	1103	0	0
ALWAYS	1103	2	2	100.00
CONT_ASSIGN	1189	1	1	100.00
CONT_ASSIGN	1331	1	1	100.00
CONT_ASSIGN	1345	1	1	100.00
CONT_ASSIGN	1352	1	1	100.00
CONT_ASSIGN	1357	1	1	100.00
ALWAYS	1363	6	5	83.33
CONT_ASSIGN	1372	1	1	100.00
CONT_ASSIGN	1374	1	1	100.00
ALWAYS	1386	4	4	100.00
CONT_ASSIGN	1392	1	1	100.00
ALWAYS	1415	4	4	100.00
ALWAYS	1425	3	3	100.00
CONT_ASSIGN	1436	1	1	100.00
CONT_ASSIGN	1440	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
346	1	1
347	1	1
352	0	1
421	1	1
422	1	1
426	1	1
429	1	1
430	1	1
431	1	1
432	1	1
434	1	1
436	1	1
440	1	1
444	1	1
448	1	1
464	1	1
465	1	1
466	1	1
469	1	1
473	1	1
474	1	1
478	1	1
481	1	1
488	1	1
489	1	1
490	1	1
491	1	1
492	1	1
493	1	1
			MISSING_ELSE
			MISSING_ELSE
501	1	1
502	1	1
503	1	1
504	1	1
505	1	1
506	1	1
			MISSING_ELSE
			MISSING_ELSE
518	1	1
525	1	1
528	1	1
529	1	1
530	1	1
533	5	5
534	5	5
537	1	1
539	1	1
541	1	1
545	1	1
547	1	1
548	1	1
551	1	1
552	1	1
555	1	1
563	1	1
564	1	1
565	1	1
566	1	1
568	1	1
573	1	1
580	1	1
581	1	1
582	1	1
592	1	1
612	2	2
613	1	1
616	1	1
635	1	1
640	1	1
643	1	1
645	1	1
650	1	1
654	1	1
658	1	1
662	1	1
666	1	1
679	1	1
684	1	1
691	1	1
701	1	1
721	3	3
725	1	1
727	1	1
728	1	1
730	1	1
732	1	1
734	1	1
735	1	1
738	1	1
741	1	1
747	1	1
748	1	1
750	1	1
755	1	1
756	1	1
757	1	1
759	1	1
765	1	1
770	1	1
771	1	1
773	1	1
775	1	1
781	1	1
782	1	1
784	1	1
790	1	1
791	1	1
803	1	1
804	1	1
			MISSING_ELSE
863	1	1
864	1	1
866	1	1
871	2	2
942	1	1
944	1	1
974	1	1
979	1	1
980	1	1
982	1	1
985		unreachable
1103	1	1
1104	1	1
1189	1	1
1331	1	1
1345	1	1
1352	1	1
1357	1	1
1363	1	1
1364	1	1
1365	1	1
1366	0	1
1367	1	1
1368	1	1
			MISSING_ELSE
1372	1	1
1374	1	1
1386	1	1
1387	1	1
1388	1	1
1389	1	1
			MISSING_ELSE
1392	1	1
1415	1	1
1416	1	1
1417	1	1
1419	1	1
			MISSING_ELSE
1425	1	1
1426	1	1
1429	1	1
1436	1	1
1440	1	1
1442	6	6

---

Cond Coverage for Module : kmac

	Total	Covered	Percent
Conditions	76	73	96.05
Logical	76	73	96.05
Non-Logical	0	0
Event	0	0

 LINE       426
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T21,T22

 LINE       464
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T21,T22

 LINE       465
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T21,T22

 LINE       466
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T21,T22

 LINE       478
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T21,T22

 LINE       530
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T59,T60,T61

 LINE       541
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T59,T60,T61

 LINE       545
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T46,T53
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

 LINE       552
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T20,T21,T22
1	0	1	Covered	T20,T21,T22
1	1	0	Covered	T20,T21,T22
1	1	1	Covered	T20,T21,T22

 LINE       565
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T27,T28,T29
1	1	Covered	T20,T21,T22

 LINE       565
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T21,T22

 LINE       565
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T20,T21,T22
1	-	Covered	T20,T21,T22

 LINE       573
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T36,T46,T53
1	1	Covered	T36,T46,T53

 LINE       616
 EXPRESSION (((~msgfifo_empty_q)) & msgfifo_empty)
             ----------1---------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

 LINE       635
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T20,T21,T22
0	0	0	1	Covered	T31,T51,T52
0	0	1	0	Covered	T36,T53,T65
0	1	0	0	Covered	T31,T24,T46
1	0	0	0	Covered	T30,T37,T38

 LINE       679
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T20,T21,T22
0	0	0	1	Covered	T27,T28,T29
0	0	1	0	Covered	T27,T28,T29
0	1	0	0	Covered	T27,T28,T29
1	0	0	0	Covered	T27,T28,T29

 LINE       691
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T20,T21,T22
0	0	0	0	0	1	Covered	T27,T28,T29
0	0	0	0	1	0	Covered	T27,T28,T29
0	0	0	1	0	0	Covered	T27,T28,T29
0	0	1	0	0	0	Covered	T27,T28,T29
0	1	0	0	0	0	Covered	T27,T28,T29
1	0	0	0	0	0	Covered	T27,T28,T29

 LINE       732
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T21,T22

 LINE       734
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T22,T30,T31

 LINE       748
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T22,T30,T31
1	Covered	T22,T30,T31

 LINE       974
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Not Covered
1	1	Covered	T20,T21,T22

 LINE       1104
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T21,T22

 LINE       1345
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T73,T74,T75
1	0	Covered	T20,T21,T22
1	1	Covered	T73,T74,T75

 LINE       1345
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T73,T74,T75
1	0	Covered	T20,T21,T22
1	1	Covered	T73,T74,T75

 LINE       1374
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T20,T21,T22
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T27,T28,T29
0	0	1	0	0	Covered	T24,T25,T26
0	1	0	0	0	Covered	T27,T28,T29
1	0	0	0	0	Not Covered

---

Toggle Coverage for Module : kmac

	Total	Covered	Percent
Totals	71	71	100.00
Total Bits	6534	6534	100.00
Total Bits 0->1	3267	3267	100.00
Total Bits 1->0	3267	3267	100.00

Ports	71	71	100.00
Port Bits	6534	6534	100.00
Port Bits 0->1	3267	3267	100.00
Port Bits 1->0	3267	3267	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T71,T3,T13	Yes	T17,T18,T19	INPUT
rst_shadowed_ni	Yes	Yes	T71,T3,T13	Yes	T17,T18,T19	INPUT
clk_edn_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_edn_ni	Yes	Yes	T71,T3,T13	Yes	T17,T18,T19	INPUT
tl_i.d_ready	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_i.a_address[31:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_i.a_source[7:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_i.a_size[1:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_i.a_valid	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_o.a_ready	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T17,*T18,*T19	Yes	T17,T18,T19	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T17,T19,T66	Yes	T17,T19,T66	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T17,*T18,*T19	Yes	T17,T18,T19	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T19,T66	Yes	T18,T19,T66	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T18,T69,T71	Yes	T18,T69,T71	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T19,T66	Yes	T18,T19,T66	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T18,T69,T71	Yes	T18,T69,T71	OUTPUT
keymgr_key_i.key[1:0][255:0]	Yes	Yes	T22,T30,T31	Yes	T22,T30,T31	INPUT
keymgr_key_i.valid	Yes	Yes	T22,T30,T31	Yes	T22,T30,T31	INPUT
app_i[0].last	Yes	Yes	T22,T30,T31	Yes	T22,T30,T31	INPUT
app_i[0].strb[7:0]	Yes	Yes	T22,T59,T60	Yes	T22,T59,T60	INPUT
app_i[0].data[63:0]	Yes	Yes	T22,T30,T31	Yes	T22,T30,T31	INPUT
app_i[0].valid	Yes	Yes	T22,T30,T31	Yes	T22,T30,T31	INPUT
app_i[1].last	Yes	Yes	T22,T30,T33	Yes	T22,T30,T31	INPUT
app_i[1].strb[7:0]	Yes	Yes	T22,T59,T60	Yes	T22,T59,T60	INPUT
app_i[1].data[63:0]	Yes	Yes	T22,T30,T31	Yes	T22,T30,T31	INPUT
app_i[1].valid	Yes	Yes	T22,T30,T31	Yes	T22,T30,T31	INPUT
app_i[2].last	Yes	Yes	T22,T30,T33	Yes	T22,T30,T33	INPUT
app_i[2].strb[7:0]	Yes	Yes	T22,T59,T60	Yes	T22,T59,T60	INPUT
app_i[2].data[63:0]	Yes	Yes	T22,T30,T33	Yes	T22,T30,T33	INPUT
app_i[2].valid	Yes	Yes	T22,T30,T33	Yes	T22,T30,T33	INPUT
app_o[0].error	Yes	Yes	T71,T3,T13	Yes	T71,T3,T13	OUTPUT
app_o[0].digest_share1[383:0]	Yes	Yes	T22,T30,T31	Yes	T22,T30,T31	OUTPUT
app_o[0].digest_share0[383:0]	Yes	Yes	T22,T30,T31	Yes	T22,T30,T31	OUTPUT
app_o[0].done	Yes	Yes	T22,T30,T31	Yes	T22,T30,T31	OUTPUT
app_o[0].ready	Yes	Yes	T22,T30,T31	Yes	T22,T30,T31	OUTPUT
app_o[1].error	Yes	Yes	T30,T37,T38	Yes	T30,T37,T38	OUTPUT
app_o[1].digest_share1[383:0]	Yes	Yes	T22,T30,T31	Yes	T22,T30,T31	OUTPUT
app_o[1].digest_share0[383:0]	Yes	Yes	T22,T30,T33	Yes	T22,T30,T33	OUTPUT
app_o[1].done	Yes	Yes	T22,T30,T31	Yes	T22,T30,T31	OUTPUT
app_o[1].ready	Yes	Yes	T22,T30,T31	Yes	T22,T30,T31	OUTPUT
app_o[2].error	Yes	Yes	T30,T37,T38	Yes	T30,T37,T38	OUTPUT
app_o[2].digest_share1[383:0]	Yes	Yes	T22,T33,T48	Yes	T22,T33,T48	OUTPUT
app_o[2].digest_share0[383:0]	Yes	Yes	T22,T30,T33	Yes	T22,T30,T33	OUTPUT
app_o[2].done	Yes	Yes	T22,T30,T33	Yes	T22,T30,T33	OUTPUT
app_o[2].ready	Yes	Yes	T22,T30,T33	Yes	T22,T30,T33	OUTPUT
entropy_o.edn_req	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
entropy_i.edn_bus[31:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
entropy_i.edn_fips	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
entropy_i.edn_ack	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
intr_kmac_done_o	Yes	Yes	T17,T67,T11	Yes	T17,T67,T11	OUTPUT
intr_fifo_empty_o	Yes	Yes	T17,T67,T11	Yes	T17,T67,T11	OUTPUT
intr_kmac_err_o	Yes	Yes	T3,T14,T5	Yes	T3,T14,T5	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T71,T3,T13	Yes	T71,T3,T13	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : kmac

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	10	76.92
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	773	Covered	T17
KmacIdle	741	Covered	T17
KmacKeyBlock	748	Covered	T17
KmacMsgFeed	738	Covered	T17
KmacPrefix	735	Covered	T17
KmacTerminalError	790	Covered	T17

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	782	Covered	T17
KmacDigest->KmacTerminalError	804	Not Covered
KmacIdle->KmacMsgFeed	738	Covered	T17
KmacIdle->KmacPrefix	735	Covered	T17
KmacIdle->KmacTerminalError	804	Covered	T17
KmacKeyBlock->KmacMsgFeed	757	Covered	T17
KmacKeyBlock->KmacTerminalError	804	Covered	T17
KmacMsgFeed->KmacDigest	773	Covered	T17
KmacMsgFeed->KmacIdle	770	Covered	T17
KmacMsgFeed->KmacTerminalError	804	Not Covered
KmacPrefix->KmacKeyBlock	748	Covered	T17
KmacPrefix->KmacMsgFeed	748	Covered	T17
KmacPrefix->KmacTerminalError	804	Not Covered

---

Branch Coverage for Module : kmac

	Line No.	Total	Covered	Percent
Branches		58	56	96.55
TERNARY	426	2	2	100.00
CASE	434	6	5	83.33
IF	488	3	3	100.00
IF	563	3	3	100.00
IF	612	2	2	100.00
CASE	645	6	6	100.00
IF	721	2	2	100.00
CASE	730	15	15	100.00
IF	803	2	2	100.00
TERNARY	1104	2	2	100.00
IF	1363	4	3	75.00
IF	1386	3	3	100.00
IF	1415	3	3	100.00
IF	1425	2	2	100.00
IF	501	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	426	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	434	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T20,T21,T22
CmdProcess	Covered	T20,T21,T22
CmdManualRun	Covered	T21,T22,T30
CmdDone	Covered	T20,T21,T22
CmdNone	Covered	T20,T21,T22
default	Not Covered

	LineNo.	Expression
-1-:	488	if ((!rst_ni))
-2-:	490	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T21,T22
0	1	Covered	T20,T21,T22
0	0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	563	if ((!rst_ni))
-2-:	565	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T21,T22
0	1	Covered	T20,T21,T22
0	0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	612	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	645	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T31,T24,T46
errchecker_err.valid	Covered	T31,T51,T52
sha3_err.valid	Covered	T30,T37,T38
entropy_err.valid	Covered	T36,T53,T65
msgfifo_err.valid	Covered	T27,T28,T29
default	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	721	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	730	case (kmac_st)
-2-:	732	if ((kmac_cmd == CmdStart))
-3-:	734	if ((CShake == app_sha3_mode))
-4-:	747	if (sha3_block_processed)
-5-:	748	(app_kmac_en) ? 
-6-:	756	if (sha3_block_processed)
-7-:	765	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	771	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	781	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T22,T30,T31
KmacIdle	1	0	-	-	-	-	-	-	Covered	T20,T21,T22
KmacIdle	0	-	-	-	-	-	-	-	Covered	T20,T21,T22
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T22,T30,T31
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T22,T30,T31
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T22,T30,T31
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T22,T30,T31
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T22,T30,T31
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T22,T30,T31
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T20,T21,T22
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T20,T21,T22
KmacDigest	-	-	-	-	-	-	-	1	Covered	T20,T21,T22
KmacDigest	-	-	-	-	-	-	-	0	Covered	T20,T21,T22
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T24,T25,T26
default	-	-	-	-	-	-	-	-	Covered	T27,T28,T29

	LineNo.	Expression
-1-:	803	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	1104	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	1363	if ((!rst_ni))
-2-:	1365	if (alert_recov_operation)
-3-:	1367	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T20,T21,T22
0	1	-	Not Covered
0	0	1	Covered	T36,T46,T53
0	0	0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	1386	if ((!rst_ni))
-2-:	1388	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T21,T22
0	1	Covered	T24,T25,T26
0	0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	1415	if ((!rst_ni))
-2-:	1417	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T21,T22
0	1	Covered	T24,T25,T26
0	0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	1425	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	501	if ((!rst_ni))
-2-:	503	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T21,T22
0	1	Covered	T20,T21,T22
0	0	Covered	T20,T21,T22

---

Assert Coverage for Module : kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	2147483647	2147483647	0	0
CmdSparse_M	2147483647	1197160	0	0
EnMaskingKnown_A	2147483647	2147483647	0	0
EntropyReadyLatched_A	2147483647	328420	0	0
EntrySizeRegSameToEntrySizePkg_A	1025	1025	0	0
ErrProcessedLatched_A	2147483647	1620	0	0
FifoEmpty_A	2147483647	2147483647	0	0
FpvSecCmErrorCheckFsmCheck_A	2147483647	50	0	0
FpvSecCmKeccackFsmCheck_A	2147483647	50	0	0
FpvSecCmKeyIndexCountCheck_A	2147483647	50	0	0
FpvSecCmKmacAppFsmCheck_A	2147483647	50	0	0
FpvSecCmKmacCoreFsmCheck_A	2147483647	50	0	0
FpvSecCmKmacFsmCheck_A	2147483647	50	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	50	0	0
FpvSecCmRoundCountCheck_A	2147483647	50	0	0
FpvSecCmSHA3FsmCheck_A	2147483647	50	0	0
FpvSecCmSHA3padFsmCheck_A	2147483647	50	0	0
FpvSecCmSentMsgCountCheck_A	2147483647	50	0	0
KmacCmd_A	2147483647	2147483647	0	0
KmacDone_A	2147483647	2147483647	0	0
KmacErr_A	2147483647	2147483647	0	0
KmacStKnown_A	2147483647	2147483647	0	0
NumAlerts2_A	1025	1025	0	0
NumEntriesRegSameToNumEntriesPkg_A	1025	1025	0	0
PrefixRegSameToPrefixPkg_A	1025	1025	0	0
SecretKeyDivideBy32_A	1025	1025	0	0
Sha3AbsorbedPulse_A	2147483647	335200	0	0
TlOAReadyKnown_A	2147483647	2147483647	0	0
TlODValidKnown_A	2147483647	2147483647	0	0
g_testassertion.FpvSecCmEntropyFsmCheck_A	2147483647	50	0	0
g_testassertion.FpvSecCmHashCountCheck_A	2147483647	50	0	0
g_testassertion.FpvSecCmMsgFifoRptrCheck_A	2147483647	50	0	0
g_testassertion.FpvSecCmMsgFifoWptrCheck_A	2147483647	50	0	0
g_testassertion.FpvSecCmPackerCountCheck_A	2147483647	50	0	0
g_testassertion.FpvSecCmSeedIdxCountCheck_A	2147483647	50	0	0
u_state_regs_A	2147483647	2147483647	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T20	321999	321993	0	0
T21	151249	151248	0	0
T22	407548	407486	0	0
T23	657052	657046	0	0
T30	264362	264291	0	0
T31	455721	455659	0	0
T32	830486	830424	0	0
T33	340300	340238	0	0
T34	151249	151248	0	0
T36	3631	3569	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1197160	0	0
T20	321999	790	0	0
T21	151249	7918	0	0
T22	407548	279	0	0
T23	657052	1247	0	0
T30	264362	1579	0	0
T31	455721	414	0	0
T32	830486	406	0	0
T33	340300	290	0	0
T34	151249	7918	0	0
T36	3631	3	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T20	321999	321993	0	0
T21	151249	151248	0	0
T22	407548	407486	0	0
T23	657052	657046	0	0
T30	264362	264291	0	0
T31	455721	455659	0	0
T32	830486	830424	0	0
T33	340300	340238	0	0
T34	151249	151248	0	0
T36	3631	3569	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	328420	0	0
T20	321999	241	0	0
T21	151249	2205	0	0
T22	407548	60	0	0
T23	657052	371	0	0
T30	264362	317	0	0
T31	455721	60	0	0
T32	830486	60	0	0
T33	340300	60	0	0
T34	151249	2205	0	0
T36	3631	18	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T36	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1620	0	0
T23	657052	0	0	0
T24	4074	0	0	0
T30	264362	0	0	0
T31	455721	0	0	0
T32	830486	0	0	0
T33	340300	0	0	0
T34	151249	0	0	0
T35	179590	0	0	0
T36	3631	18	0	0
T46	88478	18	0	0
T53	0	18	0	0
T54	0	18	0	0
T55	0	18	0	0
T65	0	18	0	0
T76	0	18	0	0
T77	0	18	0	0
T78	0	18	0	0
T79	0	18	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T20	321999	321993	0	0
T21	151249	151248	0	0
T22	407548	407486	0	0
T23	657052	657046	0	0
T30	264362	264291	0	0
T31	455721	455659	0	0
T32	830486	830424	0	0
T33	340300	340238	0	0
T34	151249	151248	0	0
T36	3631	3569	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T27	359270	10	0	0
T28	0	10	0	0
T29	0	10	0	0
T80	0	10	0	0
T81	0	10	0	0
T82	455721	0	0	0
T83	4074	0	0	0
T84	179590	0	0	0
T85	405376	0	0	0
T86	405376	0	0	0
T87	1182	0	0	0
T88	107823	0	0	0
T89	264362	0	0	0
T90	17318	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T27	359270	10	0	0
T28	0	10	0	0
T29	0	10	0	0
T80	0	10	0	0
T81	0	10	0	0
T82	455721	0	0	0
T83	4074	0	0	0
T84	179590	0	0	0
T85	405376	0	0	0
T86	405376	0	0	0
T87	1182	0	0	0
T88	107823	0	0	0
T89	264362	0	0	0
T90	17318	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T27	359270	10	0	0
T28	0	10	0	0
T29	0	10	0	0
T80	0	10	0	0
T81	0	10	0	0
T82	455721	0	0	0
T83	4074	0	0	0
T84	179590	0	0	0
T85	405376	0	0	0
T86	405376	0	0	0
T87	1182	0	0	0
T88	107823	0	0	0
T89	264362	0	0	0
T90	17318	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T27	359270	10	0	0
T28	0	10	0	0
T29	0	10	0	0
T80	0	10	0	0
T81	0	10	0	0
T82	455721	0	0	0
T83	4074	0	0	0
T84	179590	0	0	0
T85	405376	0	0	0
T86	405376	0	0	0
T87	1182	0	0	0
T88	107823	0	0	0
T89	264362	0	0	0
T90	17318	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T27	359270	10	0	0
T28	0	10	0	0
T29	0	10	0	0
T80	0	10	0	0
T81	0	10	0	0
T82	455721	0	0	0
T83	4074	0	0	0
T84	179590	0	0	0
T85	405376	0	0	0
T86	405376	0	0	0
T87	1182	0	0	0
T88	107823	0	0	0
T89	264362	0	0	0
T90	17318	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T27	359270	10	0	0
T28	0	10	0	0
T29	0	10	0	0
T80	0	10	0	0
T81	0	10	0	0
T82	455721	0	0	0
T83	4074	0	0	0
T84	179590	0	0	0
T85	405376	0	0	0
T86	405376	0	0	0
T87	1182	0	0	0
T88	107823	0	0	0
T89	264362	0	0	0
T90	17318	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T27	359270	10	0	0
T28	0	10	0	0
T29	0	10	0	0
T80	0	10	0	0
T81	0	10	0	0
T82	455721	0	0	0
T83	4074	0	0	0
T84	179590	0	0	0
T85	405376	0	0	0
T86	405376	0	0	0
T87	1182	0	0	0
T88	107823	0	0	0
T89	264362	0	0	0
T90	17318	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T27	359270	10	0	0
T28	0	10	0	0
T29	0	10	0	0
T80	0	10	0	0
T81	0	10	0	0
T82	455721	0	0	0
T83	4074	0	0	0
T84	179590	0	0	0
T85	405376	0	0	0
T86	405376	0	0	0
T87	1182	0	0	0
T88	107823	0	0	0
T89	264362	0	0	0
T90	17318	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T27	359270	10	0	0
T28	0	10	0	0
T29	0	10	0	0
T80	0	10	0	0
T81	0	10	0	0
T82	455721	0	0	0
T83	4074	0	0	0
T84	179590	0	0	0
T85	405376	0	0	0
T86	405376	0	0	0
T87	1182	0	0	0
T88	107823	0	0	0
T89	264362	0	0	0
T90	17318	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T27	359270	10	0	0
T28	0	10	0	0
T29	0	10	0	0
T80	0	10	0	0
T81	0	10	0	0
T82	455721	0	0	0
T83	4074	0	0	0
T84	179590	0	0	0
T85	405376	0	0	0
T86	405376	0	0	0
T87	1182	0	0	0
T88	107823	0	0	0
T89	264362	0	0	0
T90	17318	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T27	359270	10	0	0
T28	0	10	0	0
T29	0	10	0	0
T80	0	10	0	0
T81	0	10	0	0
T82	455721	0	0	0
T83	4074	0	0	0
T84	179590	0	0	0
T85	405376	0	0	0
T86	405376	0	0	0
T87	1182	0	0	0
T88	107823	0	0	0
T89	264362	0	0	0
T90	17318	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T20	321999	321993	0	0
T21	151249	151248	0	0
T22	407548	407486	0	0
T23	657052	657046	0	0
T30	264362	264291	0	0
T31	455721	455659	0	0
T32	830486	830424	0	0
T33	340300	340238	0	0
T34	151249	151248	0	0
T36	3631	3569	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T20	321999	321993	0	0
T21	151249	151248	0	0
T22	407548	407486	0	0
T23	657052	657046	0	0
T30	264362	264291	0	0
T31	455721	455659	0	0
T32	830486	830424	0	0
T33	340300	340238	0	0
T34	151249	151248	0	0
T36	3631	3569	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T20	321999	321993	0	0
T21	151249	151248	0	0
T22	407548	407486	0	0
T23	657052	657046	0	0
T30	264362	264291	0	0
T31	455721	455659	0	0
T32	830486	830424	0	0
T33	340300	340238	0	0
T34	151249	151248	0	0
T36	3631	3569	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T20	321999	321993	0	0
T21	151249	151248	0	0
T22	407548	407486	0	0
T23	657052	657046	0	0
T30	264362	264291	0	0
T31	455721	455659	0	0
T32	830486	830424	0	0
T33	340300	340238	0	0
T34	151249	151248	0	0
T36	3631	3569	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T36	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T36	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T36	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T36	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	335200	0	0
T20	321999	246	0	0
T21	151249	2265	0	0
T22	407548	60	0	0
T23	657052	390	0	0
T30	264362	319	0	0
T31	455721	56	0	0
T32	830486	60	0	0
T33	340300	60	0	0
T34	151249	2265	0	0
T35	0	2337	0	0
T36	3631	0	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T20	321999	321993	0	0
T21	151249	151248	0	0
T22	407548	407486	0	0
T23	657052	657046	0	0
T30	264362	264291	0	0
T31	455721	455659	0	0
T32	830486	830424	0	0
T33	340300	340238	0	0
T34	151249	151248	0	0
T36	3631	3569	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T20	321999	321993	0	0
T21	151249	151248	0	0
T22	407548	407486	0	0
T23	657052	657046	0	0
T30	264362	264291	0	0
T31	455721	455659	0	0
T32	830486	830424	0	0
T33	340300	340238	0	0
T34	151249	151248	0	0
T36	3631	3569	0	0

g_testassertion.FpvSecCmEntropyFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T27	359270	10	0	0
T28	0	10	0	0
T29	0	10	0	0
T80	0	10	0	0
T81	0	10	0	0
T82	455721	0	0	0
T83	4074	0	0	0
T84	179590	0	0	0
T85	405376	0	0	0
T86	405376	0	0	0
T87	1182	0	0	0
T88	107823	0	0	0
T89	264362	0	0	0
T90	17318	0	0	0

g_testassertion.FpvSecCmHashCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T27	359270	10	0	0
T28	0	10	0	0
T29	0	10	0	0
T80	0	10	0	0
T81	0	10	0	0
T82	455721	0	0	0
T83	4074	0	0	0
T84	179590	0	0	0
T85	405376	0	0	0
T86	405376	0	0	0
T87	1182	0	0	0
T88	107823	0	0	0
T89	264362	0	0	0
T90	17318	0	0	0

g_testassertion.FpvSecCmMsgFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T27	359270	10	0	0
T28	0	10	0	0
T29	0	10	0	0
T80	0	10	0	0
T81	0	10	0	0
T82	455721	0	0	0
T83	4074	0	0	0
T84	179590	0	0	0
T85	405376	0	0	0
T86	405376	0	0	0
T87	1182	0	0	0
T88	107823	0	0	0
T89	264362	0	0	0
T90	17318	0	0	0

g_testassertion.FpvSecCmMsgFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T27	359270	10	0	0
T28	0	10	0	0
T29	0	10	0	0
T80	0	10	0	0
T81	0	10	0	0
T82	455721	0	0	0
T83	4074	0	0	0
T84	179590	0	0	0
T85	405376	0	0	0
T86	405376	0	0	0
T87	1182	0	0	0
T88	107823	0	0	0
T89	264362	0	0	0
T90	17318	0	0	0

g_testassertion.FpvSecCmPackerCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T27	359270	10	0	0
T28	0	10	0	0
T29	0	10	0	0
T80	0	10	0	0
T81	0	10	0	0
T82	455721	0	0	0
T83	4074	0	0	0
T84	179590	0	0	0
T85	405376	0	0	0
T86	405376	0	0	0
T87	1182	0	0	0
T88	107823	0	0	0
T89	264362	0	0	0
T90	17318	0	0	0

g_testassertion.FpvSecCmSeedIdxCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50	0	0
T27	359270	10	0	0
T28	0	10	0	0
T29	0	10	0	0
T80	0	10	0	0
T81	0	10	0	0
T82	455721	0	0	0
T83	4074	0	0	0
T84	179590	0	0	0
T85	405376	0	0	0
T86	405376	0	0	0
T87	1182	0	0	0
T88	107823	0	0	0
T89	264362	0	0	0
T90	17318	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T20	321999	321993	0	0
T21	151249	151248	0	0
T22	407548	407486	0	0
T23	657052	657046	0	0
T30	264362	264291	0	0
T31	455721	455659	0	0
T32	830486	830424	0	0
T33	340300	340238	0	0
T34	151249	151248	0	0
T36	3631	3569	0	0