Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	60690	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

133025

1

T1

942

T2

6

T3

10563

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	114460	1			T1	726		T2	11		T3	7221
values[0x0]	38616	1			T1	311		T2	6		T3	3738
values[0x1]	40639	1			T1	295		T2	5		T3	3726

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45650	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

148065

1

T1

1064

T2

7

T3

11310

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	666	1			T1	1		T3	80		T6	2
valid_sources[0x01]	791	1			T1	6		T3	26		T6	3
valid_sources[0x02]	820	1			T1	3		T3	19		T6	1
valid_sources[0x03]	619	1			T1	5		T3	56		T6	1
valid_sources[0x04]	665	1			T1	7		T3	36		T20	1
valid_sources[0x05]	703	1			T1	3		T3	34		T6	1
valid_sources[0x06]	835	1			T1	1		T3	29		T6	2
valid_sources[0x07]	688	1			T3	45		T18	4		T19	1
valid_sources[0x08]	801	1			T1	2		T3	67		T6	1
valid_sources[0x09]	1013	1			T1	3		T3	67		T6	1
valid_sources[0x0a]	738	1			T1	4		T3	90		T6	2
valid_sources[0x0b]	706	1			T1	6		T3	100		T6	2
valid_sources[0x0c]	898	1			T1	7		T3	60		T18	1
valid_sources[0x0d]	715	1			T1	3		T3	64		T6	4
valid_sources[0x0e]	538	1			T1	7		T2	1		T3	75
valid_sources[0x0f]	800	1			T1	2		T3	46		T6	2
valid_sources[0x10]	775	1			T1	10		T3	10		T7	7
valid_sources[0x11]	933	1			T1	9		T3	36		T6	2
valid_sources[0x12]	1053	1			T1	4		T3	96		T6	3
valid_sources[0x13]	769	1			T1	3		T3	76		T6	1
valid_sources[0x14]	792	1			T1	13		T3	39		T6	1
valid_sources[0x15]	604	1			T1	6		T3	40		T20	1
valid_sources[0x16]	708	1			T1	3		T3	95		T6	2
valid_sources[0x17]	708	1			T1	3		T3	90		T6	1
valid_sources[0x18]	814	1			T1	1		T3	66		T4	87
valid_sources[0x19]	833	1			T1	1		T3	40		T6	1
valid_sources[0x1a]	740	1			T1	3		T2	5		T3	104
valid_sources[0x1b]	909	1			T1	6		T3	79		T6	1
valid_sources[0x1c]	663	1			T1	7		T3	37		T6	3
valid_sources[0x1d]	808	1			T1	3		T3	33		T14	1
valid_sources[0x1e]	730	1			T1	2		T3	102		T6	3
valid_sources[0x1f]	961	1			T1	5		T3	34		T18	15
valid_sources[0x20]	668	1			T1	11		T3	103		T18	2
valid_sources[0x21]	751	1			T1	6		T3	42		T18	3
valid_sources[0x22]	703	1			T1	9		T3	37		T6	1
valid_sources[0x23]	644	1			T1	6		T3	66		T14	1
valid_sources[0x24]	893	1			T1	2		T3	84		T6	1
valid_sources[0x25]	557	1			T1	3		T3	41		T6	2
valid_sources[0x26]	921	1			T1	5		T3	80		T37	27
valid_sources[0x27]	827	1			T1	3		T3	59		T18	6
valid_sources[0x28]	752	1			T1	5		T3	71		T6	1
valid_sources[0x29]	980	1			T1	4		T3	39		T6	2
valid_sources[0x2a]	577	1			T1	1		T3	54		T6	2
valid_sources[0x2b]	786	1			T1	1		T3	81		T6	1
valid_sources[0x2c]	737	1			T1	7		T3	39		T6	1
valid_sources[0x2d]	625	1			T1	9		T3	51		T18	3
valid_sources[0x2e]	862	1			T1	6		T3	58		T6	4
valid_sources[0x2f]	651	1			T1	10		T3	62		T6	2
valid_sources[0x30]	827	1			T1	3		T3	84		T6	1
valid_sources[0x31]	667	1			T1	4		T3	82		T6	3
valid_sources[0x32]	947	1			T1	5		T3	65		T6	1
valid_sources[0x33]	712	1			T1	3		T2	1		T3	36
valid_sources[0x34]	666	1			T1	5		T3	29		T18	5
valid_sources[0x35]	783	1			T3	56		T14	1		T18	3
valid_sources[0x36]	601	1			T1	4		T3	34		T19	2
valid_sources[0x37]	798	1			T1	11		T3	64		T18	5
valid_sources[0x38]	636	1			T1	7		T3	40		T19	1
valid_sources[0x39]	1117	1			T1	6		T3	56		T18	4
valid_sources[0x3a]	663	1			T1	10		T3	55		T6	1
valid_sources[0x3b]	744	1			T1	4		T3	24		T18	4
valid_sources[0x3c]	740	1			T1	8		T3	62		T6	1
valid_sources[0x3d]	871	1			T1	7		T3	63		T6	1
valid_sources[0x3e]	630	1			T3	46		T18	4		T7	1
valid_sources[0x3f]	912	1			T1	4		T3	39		T6	1
valid_sources[0x40]	632	1			T1	2		T3	32		T18	1
valid_sources[0x41]	661	1			T1	5		T3	91		T6	1
valid_sources[0x42]	848	1			T1	7		T3	38		T18	1
valid_sources[0x43]	775	1			T3	46		T6	2		T19	7
valid_sources[0x44]	708	1			T1	5		T3	50		T6	1
valid_sources[0x45]	678	1			T1	5		T3	56		T18	1
valid_sources[0x46]	562	1			T1	8		T3	68		T6	2
valid_sources[0x47]	730	1			T3	58		T6	1		T18	4
valid_sources[0x48]	858	1			T1	9		T3	91		T6	1
valid_sources[0x49]	837	1			T1	4		T3	54		T19	5
valid_sources[0x4a]	1111	1			T1	8		T3	31		T18	1
valid_sources[0x4b]	849	1			T1	3		T3	66		T6	1
valid_sources[0x4c]	907	1			T1	8		T3	97		T20	1
valid_sources[0x4d]	728	1			T1	13		T3	45		T18	8
valid_sources[0x4e]	639	1			T1	7		T3	57		T18	2
valid_sources[0x4f]	752	1			T1	5		T3	47		T18	21
valid_sources[0x50]	703	1			T3	35		T6	1		T18	6
valid_sources[0x51]	869	1			T1	7		T3	95		T19	6
valid_sources[0x52]	751	1			T1	2		T3	60		T6	3
valid_sources[0x53]	726	1			T1	2		T3	38		T18	4
valid_sources[0x54]	615	1			T1	1		T3	61		T18	1
valid_sources[0x55]	759	1			T1	2		T3	61		T6	3
valid_sources[0x56]	812	1			T1	9		T3	102		T6	1
valid_sources[0x57]	727	1			T1	8		T3	75		T18	6
valid_sources[0x58]	923	1			T1	5		T3	59		T6	1
valid_sources[0x59]	803	1			T1	6		T3	40		T6	6
valid_sources[0x5a]	862	1			T1	5		T3	81		T6	5
valid_sources[0x5b]	674	1			T1	8		T2	1		T3	25
valid_sources[0x5c]	876	1			T1	5		T3	68		T6	3
valid_sources[0x5d]	746	1			T1	4		T3	26		T18	3
valid_sources[0x5e]	902	1			T1	8		T3	88		T6	1
valid_sources[0x5f]	761	1			T1	3		T3	23		T4	31
valid_sources[0x60]	730	1			T1	5		T2	2		T3	36
valid_sources[0x61]	840	1			T1	3		T3	72		T6	1
valid_sources[0x62]	726	1			T1	5		T2	1		T3	61
valid_sources[0x63]	715	1			T1	2		T3	50		T18	1
valid_sources[0x64]	682	1			T1	7		T3	47		T18	7
valid_sources[0x65]	649	1			T1	10		T3	69		T18	3
valid_sources[0x66]	772	1			T1	11		T3	73		T20	1
valid_sources[0x67]	761	1			T1	7		T3	53		T18	6
valid_sources[0x68]	724	1			T1	1		T3	60		T20	1
valid_sources[0x69]	726	1			T1	9		T3	87		T18	4
valid_sources[0x6a]	783	1			T1	2		T3	65		T6	5
valid_sources[0x6b]	793	1			T1	8		T2	1		T3	20
valid_sources[0x6c]	693	1			T1	3		T2	1		T3	56
valid_sources[0x6d]	620	1			T1	1		T3	36		T6	3
valid_sources[0x6e]	848	1			T1	6		T3	45		T18	2
valid_sources[0x6f]	723	1			T1	4		T3	73		T5	69
valid_sources[0x70]	547	1			T1	5		T3	38		T6	1
valid_sources[0x71]	806	1			T1	3		T3	38		T6	1
valid_sources[0x72]	793	1			T1	3		T3	52		T6	2
valid_sources[0x73]	682	1			T1	3		T3	90		T7	1
valid_sources[0x74]	817	1			T1	8		T3	55		T6	1
valid_sources[0x75]	836	1			T1	2		T2	1		T3	70
valid_sources[0x76]	803	1			T1	4		T3	79		T6	2
valid_sources[0x77]	587	1			T1	4		T3	48		T6	1
valid_sources[0x78]	764	1			T1	4		T3	110		T6	1
valid_sources[0x79]	719	1			T1	4		T3	92		T6	1
valid_sources[0x7a]	700	1			T1	5		T3	55		T6	1
valid_sources[0x7b]	874	1			T1	2		T3	82		T4	57
valid_sources[0x7c]	825	1			T1	7		T3	55		T20	1
valid_sources[0x7d]	639	1			T1	4		T3	40		T19	5
valid_sources[0x7e]	825	1			T1	9		T3	54		T19	4
valid_sources[0x7f]	688	1			T1	3		T3	60		T6	4
valid_sources[0x80]	896	1			T1	5		T3	51		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63444

1

T1

380

T2

4

T3

3630

values[0x0]

all_enables

biggest_size

35273

1

T1

294

T2

1

T3

3512

values[0x1]

all_enables

biggest_size

34308

1

T1

268

T2

1

T3

3421