Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

73121

1

T1

391

T2

16

T3

4122

full_word

133825

1

T1

942

T2

6

T3

10563

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	206676	1			T1	1323		T2	22		T3	14685
auto[TlIntgErrCmd]	102	1			T1	5		T33	9		T71	3
auto[TlIntgErrData]	93	1			T1	3		T33	6		T71	5
auto[TlIntgErrBoth]	75	1			T1	2		T33	5		T71	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116816

1

T1

727

T2

11

T3

7221

auto[1]

90130

1

T1

606

T2

11

T3

7464

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	53072	1			T1	343		T2	7		T3	3591
auto[TlIntgErrNone]	partial	auto[1]	19800	1			T1	39		T2	9		T3	531
auto[TlIntgErrNone]	full_word	auto[0]	63620	1			T1	380		T2	4		T3	3630
auto[TlIntgErrNone]	full_word	auto[1]	70184	1			T1	561		T2	2		T3	6933
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T1	2		T33	4		T38	1
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T1	2		T33	5		T71	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T79	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T1	1		T80	1		T81	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T1	1		T33	4		T71	3
auto[TlIntgErrData]	partial	auto[1]	40	1			T1	2		T33	2		T38	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T71	1		T39	1		T82	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T71	1		T39	2		T34	1
auto[TlIntgErrBoth]	partial	auto[0]	29	1			T1	1		T33	3		T71	1
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T1	1		T33	2		T71	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T82	1		T83	1		-	-