Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_packer
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_msgfifo.u_packer 0.00 0.00 0.00 0.00


Module Instance : tb.dut.u_msgfifo.u_packer

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 u_msgfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_pos_dupcnt.u_pos 0.00 0.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_packer
Line No.TotalCoveredPercent
TOTAL6200.00
ALWAYS65300.00
CONT_ASSIGN72100.00
CONT_ASSIGN110100.00
CONT_ASSIGN111100.00
CONT_ASSIGN112100.00
CONT_ASSIGN115100.00
ALWAYS120300.00
ALWAYS156400.00
CONT_ASSIGN164100.00
CONT_ASSIGN165100.00
CONT_ASSIGN169100.00
CONT_ASSIGN170100.00
CONT_ASSIGN173100.00
CONT_ASSIGN174100.00
CONT_ASSIGN177100.00
CONT_ASSIGN179100.00
ALWAYS184900.00
ALWAYS213800.00
ALWAYS234300.00
ALWAYS2421400.00
CONT_ASSIGN278100.00
CONT_ASSIGN282100.00
CONT_ASSIGN29000
CONT_ASSIGN293100.00
CONT_ASSIGN294100.00
CONT_ASSIGN295100.00
CONT_ASSIGN29800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 0 1
66 0 1
67 0 1
72 0 1
110 0 1
111 0 1
112 0 1
115 0 1
120 0 1
122 0 1
124 0 1
==> MISSING_ELSE
156 0 1
157 0 1
158 0 1
159 0 1
==> MISSING_ELSE
164 0 1
165 0 1
169 0 1
170 0 1
173 0 1
174 0 1
177 0 1
179 0 1
184 0 1
186 0 1
187 0 1
191 0 1
192 0 1
196 0 1
197 0 1
201 0 1
202 0 1
213 0 1
214 0 1
215 0 1
216 0 1
217 0 1
218 0 1
220 0 1
221 0 1
234 0 1
235 0 1
237 0 1
242 0 1
244 0 1
245 0 1
247 0 1
249 0 1
250 0 1
252 0 1
257 0 1
258 0 1
260 0 1
261 0 1
263 0 1
265 0 1
266 0 1
278 0 1
282 0 1
290 unreachable
293 0 1
294 0 1
295 0 1
298 unreachable

Cond Coverage for Module : prim_packer
TotalCoveredPercent
Conditions2500.00
Logical2500.00
Non-Logical00
Event00

 LINE       110
 EXPRESSION (ack_in && ((!ack_out)))
             ---1--    ------2-----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       111
 EXPRESSION (((!ack_in)) && ack_out)
             -----1-----    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       112
 EXPRESSION (ack_in && ack_out)
             ---1--    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       115
 EXPRESSION (g_pos_dupcnt.cnt_incr_en ? (8'(inmask_ones)) : (8'(OutW)))
             ------------1-----------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       158
 EXPRESSION (mask_i[i] == 1'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       164
 EXPRESSION (valid_i & ready_o)
             ---1---   ---2---
-1--2-StatusTests
01Not Covered
10Unreachable
11Not Covered 

 LINE       165
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       169
 EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
             ---1---
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       170
 EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
             ---1---
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       257
 EXPRESSION (pos_q == '0)
            ------1------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       282
 EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
             ----------1----------
-1-StatusTests
0Not Covered
1Unreachable
Branch Coverage for Module : prim_packer
Line No.TotalCoveredPercent
Branches 26 0 0.00
TERNARY 169 2 0 0.00
TERNARY 170 2 0 0.00
TERNARY 282 1 0 0.00
TERNARY 115 2 0 0.00
IF 158 2 0 0.00
CASE 184 5 0 0.00
IF 213 3 0 0.00
IF 234 2 0 0.00
CASE 247 5 0 0.00
IF 122 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	169	(valid_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	170	(valid_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	282	((int'(pos_q) >= OutW)) ?

Branches:
-1-StatusTests
1 Unreachable
0 Not Covered 



	LineNo.	Expression
-1-:	115	(g_pos_dupcnt.cnt_incr_en) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	158	if ((mask_i[i] == 1'b1))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	184	case ({ack_in, ack_out})

Branches:
-1-StatusTests
2'b00 Not Covered
2'b01 Not Covered
2'b10 Not Covered
2'b11 Not Covered
default Not Covered 



	LineNo.	Expression
-1-:	213	if ((!rst_ni))
-2-:	216	if (flush_done)

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	234	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	247	case (flush_st)
-2-:	249	if (flush_i)
-3-:	257	if ((pos_q == '0))

Branches:
-1--2--3-StatusTests
FlushIdle 1 - Not Covered
FlushIdle 0 - Not Covered
FlushSend - 1 Not Covered
FlushSend - 0 Not Covered
default - - Not Covered 



	LineNo.	Expression
-1-:	122	if ((pos_with_input > 8'(OutW)))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%