Unified Coverage Report :: Module :: kmac_entropy

Module : kmac_entropy

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_entropy.u_entropy	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.gen_entropy.u_entropy

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
1.32	0.00	0.00	6.61	0.00	0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_lfsrs[0].u_lfsr_chunk	0.00			0.00
gen_lfsrs[10].u_lfsr_chunk	0.00			0.00
gen_lfsrs[11].u_lfsr_chunk	0.00			0.00
gen_lfsrs[12].u_lfsr_chunk	0.00			0.00
gen_lfsrs[13].u_lfsr_chunk	0.00			0.00
gen_lfsrs[14].u_lfsr_chunk	0.00			0.00
gen_lfsrs[15].u_lfsr_chunk	0.00			0.00
gen_lfsrs[16].u_lfsr_chunk	0.00			0.00
gen_lfsrs[17].u_lfsr_chunk	0.00			0.00
gen_lfsrs[18].u_lfsr_chunk	0.00			0.00
gen_lfsrs[19].u_lfsr_chunk	0.00			0.00
gen_lfsrs[1].u_lfsr_chunk	0.00			0.00
gen_lfsrs[20].u_lfsr_chunk	0.00			0.00
gen_lfsrs[21].u_lfsr_chunk	0.00			0.00
gen_lfsrs[22].u_lfsr_chunk	0.00			0.00
gen_lfsrs[23].u_lfsr_chunk	0.00			0.00
gen_lfsrs[24].u_lfsr_chunk	0.00			0.00
gen_lfsrs[2].u_lfsr_chunk	0.00			0.00
gen_lfsrs[3].u_lfsr_chunk	0.00			0.00
gen_lfsrs[4].u_lfsr_chunk	0.00			0.00
gen_lfsrs[5].u_lfsr_chunk	0.00			0.00
gen_lfsrs[6].u_lfsr_chunk	0.00			0.00
gen_lfsrs[7].u_lfsr_chunk	0.00			0.00
gen_lfsrs[8].u_lfsr_chunk	0.00			0.00
gen_lfsrs[9].u_lfsr_chunk	0.00			0.00
u_entropy_configured	0.00	0.00				0.00
u_hash_count	0.00			0.00
u_seed_idx_count	0.00			0.00
u_state_regs	0.00	0.00				0.00

Line Coverage for Module : kmac_entropy

	Line No.	Total	Covered	Percent
TOTAL		1610	0	0.00
ALWAYS	241	4	0	0.00
ALWAYS	250	4	0	0.00
ALWAYS	259	8	0	0.00
CONT_ASSIGN	270	1	0	0.00
ALWAYS	273	6	0	0.00
ALWAYS	284	8	0	0.00
CONT_ASSIGN	295	1	0	0.00
ALWAYS	304	3	0	0.00
CONT_ASSIGN	308	1	0	0.00
CONT_ASSIGN	311	1	0	0.00
CONT_ASSIGN	314	1	0	0.00
CONT_ASSIGN	336	1	0	0.00
ALWAYS	339	6	0	0.00
ALWAYS	345	4	0	0.00
CONT_ASSIGN	392	1	0	0.00
CONT_ASSIGN	400	1	0	0.00
CONT_ASSIGN	400	1	0	0.00
CONT_ASSIGN	400	1	0	0.00
CONT_ASSIGN	400	1	0	0.00
CONT_ASSIGN	400	1	0	0.00
CONT_ASSIGN	408	1	0	0.00
CONT_ASSIGN	408	1	0	0.00
CONT_ASSIGN	408	1	0	0.00
CONT_ASSIGN	408	1	0	0.00
CONT_ASSIGN	408	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
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CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	457	1	0	0.00
CONT_ASSIGN	462	1	0	0.00
ALWAYS	465	3	0	0.00
CONT_ASSIGN	475	1	0	0.00
ALWAYS	480	3	0	0.00
CONT_ASSIGN	490	1	0	0.00
CONT_ASSIGN	491	1	0	0.00
ALWAYS	495	6	0	0.00
CONT_ASSIGN	505	1	0	0.00
CONT_ASSIGN	523	1	0	0.00
CONT_ASSIGN	524	1	0	0.00
ALWAYS	526	3	0	0.00
CONT_ASSIGN	536	1	0	0.00
ALWAYS	545	3	0	0.00
ALWAYS	550	78	0	0.00
ALWAYS	788	3	0	0.00
CONT_ASSIGN	797	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
241	0	1
242	0	1
243	0	1
244	0	1
			==> MISSING_ELSE
250	0	1
251	0	1
252	0	1
253	0	1
			==> MISSING_ELSE
259	0	1
260	0	1
261	0	1
262	0	1
263	0	1
264	0	1
265	0	1
266	0	1
			==> MISSING_ELSE
270	0	1
273	0	1
274	0	1
275	0	1
276	0	1
277	0	1
278	0	1
			==> MISSING_ELSE
284	0	1
285	0	1
286	0	1
287	0	1
288	0	1
289	0	1
290	0	1
291	0	1
			==> MISSING_ELSE
295	0	1
304	0	2
305	0	1
308	0	1
311	0	1
314	0	1
336	0	1
339	0	2
340	0	2
341	0	2
			==> MISSING_ELSE
345	0	2
346	0	2
			==> MISSING_ELSE
392	0	1
400	0	5
408	0	5
414	0	640
451	0	1
453	0	800
457	0	1
462	0	1
465	0	1
466	0	1
468	0	1
475	0	1
480	0	1
481	0	1
483	0	1
490	0	1
491	0	1
495	0	1
496	0	1
497	0	1
498	0	1
499	0	1
500	0	1
			==> MISSING_ELSE
505	0	1
523	0	1
524	0	1
526	0	1
527	0	1
529	0	1
536	0	1
545	0	3
550	0	1
551	0	1
554	0	1
555	0	1
557	0	1
560	0	1
568	0	1
569	0	1
572	0	1
576	0	1
580	0	1
583	0	1
586	0	1
589	0	1
591	0	1
593	0	1
596	0	1
598	0	1
600	0	1
602	0	1
606	0	1
609	0	1
619	0	1
624	0	1
629	0	1
631	0	1
633	0	1
642	0	1
643	0	1
645	0	1
646	0	1
648	0	1
650	0	1
652	0	1
654	0	1
657	0	1
660	0	1
662	0	1
668	0	1
671	0	1
673	0	1
675	0	1
677	0	1
678	0	1
680	0	1
681	0	1
683	0	1
684	0	1
685	0	1
			==> MISSING_ELSE
688	0	1
690	0	1
697	0	1
699	0	1
700	0	1
702	0	1
707	0	1
709	0	1
710	0	1
712	0	1
714	0	1
716	0	1
722	0	1
726	0	1
727	0	1
729	0	1
733	0	1
735	0	1
742	0	1
744	0	1
752	0	1
755	0	1
757	0	1
758	0	1
761	0	1
768	0	1
769	0	1
781	0	1
782	0	1
			==> MISSING_ELSE
788	0	1
789	0	1
791	0	1
797	0	1

---

Cond Coverage for Module : kmac_entropy

	Total	Covered	Percent
Conditions	188	0	0.00
Logical	188	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       265
 EXPRESSION (timer_enable && timer_pulse && ((|timer_value)))
             ------1-----    -----2-----    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       277
 EXPRESSION (timer_enable && (timer_value == '0))
             ------1-----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       277
 SUB-EXPRESSION (timer_value == '0)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       288
 EXPRESSION (timer_enable && (prescaler_cnt == '0))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       288
 SUB-EXPRESSION (prescaler_cnt == '0)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       295
 EXPRESSION (timer_enable && (prescaler_cnt == '0))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       295
 SUB-EXPRESSION (prescaler_cnt == '0)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       311
 EXPRESSION (hash_cnt_clr_i || threshold_hit || entropy_refresh_req_i)
             -------1------    ------2------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       314
 EXPRESSION (hash_progress_q && ((!hash_progress_d)))
             -------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       336
 EXPRESSION (((|hash_threshold_i)) && (hash_threshold_i <= hash_cnt_o))
             ----------1----------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       408
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[0] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       408
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       408
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[1] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       408
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       408
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[2] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       408
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       408
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[3] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       408
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       408
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[4] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       408
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       462
 EXPRESSION (aux_update ? lfsr_data_permuted[(kmac_pkg::EntropyLfsrW - 1)] : aux_rand_q)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       475
 EXPRESSION (aux_update ? lfsr_data_permuted[(kmac_pkg::EntropyLfsrW - 2)-:4] : ({1'b0, lfsr_en_rand_q[3:1]}))
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       523
 EXPRESSION (entropy_req | entropy_req_hold_q)
             -----1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       524
 EXPRESSION ((entropy_req_hold_q | entropy_req) & ((~entropy_ack_i)))
             -----------------1----------------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       524
 SUB-EXPRESSION (entropy_req_hold_q | entropy_req)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       536
 EXPRESSION (hash_count_error | seed_idx_count_error)
             --------1-------   ----------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       633
 EXPRESSION (rand_consumed_i && ((fast_process_i && in_keyblock_i) || ((!fast_process_i))))
             -------1-------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       633
 SUB-EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
                 ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       633
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       652
 EXPRESSION ((mode_q == EntropyModeEdn) && (entropy_refresh_req_i || threshold_hit_q))
             -------------1------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       652
 SUB-EXPRESSION (mode_q == EntropyModeEdn)
                -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       652
 SUB-EXPRESSION (entropy_refresh_req_i || threshold_hit_q)
                 ----------1----------    -------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       673
 EXPRESSION (timer_expired && non_zero_wait_timer_limit)
             ------1------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       683
 EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
             ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       683
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       690
 EXPRESSION (rand_consumed_i && ((fast_process_i && in_keyblock_i) || ((!fast_process_i))))
             -------1-------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       690
 SUB-EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
                 ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       690
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       755
 EXPRESSION (rand_consumed_i & ((fast_process_i & in_keyblock_i) | ((~fast_process_i))))
             -------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       755
 SUB-EXPRESSION ((fast_process_i & in_keyblock_i) | ((~fast_process_i)))
                 ----------------1---------------   ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       755
 SUB-EXPRESSION (fast_process_i & in_keyblock_i)
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       797
 EXPRESSION ((st != StRandReset) ? MuBi4True : MuBi4False)
             ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       797
 SUB-EXPRESSION (st != StRandReset)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Module : kmac_entropy

Summary for FSM :: st

	Total	Covered	Percent
States	9	0	0.00	(Not included in score)
Transitions	20	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StRandEdn	606	Not Covered
StRandErr	733	Not Covered
StRandErrIncorrectMode	615	Not Covered
StRandErrWaitExpired	675	Not Covered
StRandGenerate	646	Not Covered
StRandReady	650	Not Covered
StRandReset	619	Not Covered
StSwSeedWait	602	Not Covered
StTerminalError	782	Not Covered

transitions	Line No.	Covered	Tests
StRandEdn->StRandErrWaitExpired	675	Not Covered
StRandEdn->StRandGenerate	681	Not Covered
StRandEdn->StTerminalError	782	Not Covered
StRandErr->StRandReset	758	Not Covered
StRandErr->StTerminalError	782	Not Covered
StRandErrIncorrectMode->StRandErr	742	Not Covered
StRandErrIncorrectMode->StTerminalError	782	Not Covered
StRandErrWaitExpired->StRandErr	733	Not Covered
StRandErrWaitExpired->StTerminalError	782	Not Covered
StRandGenerate->StRandReady	729	Not Covered
StRandGenerate->StTerminalError	782	Not Covered
StRandReady->StRandEdn	654	Not Covered
StRandReady->StRandGenerate	646	Not Covered
StRandReady->StTerminalError	782	Not Covered
StRandReset->StRandEdn	606	Not Covered
StRandReset->StRandErrIncorrectMode	615	Not Covered
StRandReset->StSwSeedWait	602	Not Covered
StRandReset->StTerminalError	782	Not Covered
StSwSeedWait->StRandGenerate	710	Not Covered
StSwSeedWait->StTerminalError	782	Not Covered

---

Branch Coverage for Module : kmac_entropy

	Line No.	Total	Covered	Percent
Branches		84	0	0.00
TERNARY	462	2	0	0.00
TERNARY	475	2	0	0.00
TERNARY	797	2	0	0.00
TERNARY	408	2	0	0.00
TERNARY	408	2	0	0.00
TERNARY	408	2	0	0.00
TERNARY	408	2	0	0.00
TERNARY	408	2	0	0.00
IF	241	3	0	0.00
IF	250	3	0	0.00
IF	259	5	0	0.00
IF	273	4	0	0.00
IF	284	5	0	0.00
IF	304	2	0	0.00
IF	339	4	0	0.00
IF	345	3	0	0.00
IF	465	2	0	0.00
IF	480	2	0	0.00
IF	495	4	0	0.00
IF	526	2	0	0.00
IF	545	2	0	0.00
CASE	591	23	0	0.00
IF	781	2	0	0.00
IF	788	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	462	(aux_update) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	475	(aux_update) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	797	((st != StRandReset)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	408	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	408	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	408	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	408	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	408	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	241	if ((!rst_ni))
-2-:	243	if (timer_update)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	250	if ((!rst_ni))
-2-:	252	if (timer_update)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	259	if ((!rst_ni))
-2-:	261	if (timer_update)
-3-:	263	if (timer_expired)
-4-:	265	if (((timer_enable && timer_pulse) && (|timer_value)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Not Covered
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	273	if ((!rst_ni))
-2-:	275	if (timer_update)
-3-:	277	if ((timer_enable && (timer_value == '0)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	284	if ((!rst_ni))
-2-:	286	if (timer_update)
-3-:	288	if ((timer_enable && (prescaler_cnt == '0)))
-4-:	290	if (timer_enable)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Not Covered
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	304	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	339	if ((!rst_ni))
-2-:	340	if (threshold_hit_clr)
-3-:	341	if (threshold_hit)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	345	if ((!rst_ni))
-2-:	346	if (mode_latch)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	465	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	480	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	495	if ((!rst_ni))
-2-:	497	if (rand_valid_set)
-3-:	499	if (rand_valid_clear)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	526	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	545	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	591	case (st)
-2-:	593	if (entropy_ready_i)
-3-:	600	case (mode_i)
-4-:	633	if ((rand_consumed_i && ((fast_process_i && in_keyblock_i) || (!fast_process_i))))
-5-:	645	if (ready_phase_q)
-6-:	652	if (((mode_q == EntropyModeEdn) && (entropy_refresh_req_i || threshold_hit_q)))
-7-:	673	if ((timer_expired && non_zero_wait_timer_limit))
-8-:	677	if (entropy_ack_i)
-9-:	680	if (lfsr_seed_done)
-10-:	683	if (((fast_process_i && in_keyblock_i) || (!fast_process_i)))
-11-:	690	if ((rand_consumed_i && ((fast_process_i && in_keyblock_i) || (!fast_process_i))))
-12-:	709	if (lfsr_seed_done)
-13-:	757	if (err_processed_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StRandReset	1	EntropyModeSw	-	-	-	-	-	-	-	-	-	-	Not Covered
StRandReset	1	EntropyModeEdn	-	-	-	-	-	-	-	-	-	-	Not Covered
StRandReset	1	default	-	-	-	-	-	-	-	-	-	-	Not Covered
StRandReset	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StRandReady	-	-	1	1	-	-	-	-	-	-	-	-	Not Covered
StRandReady	-	-	1	0	-	-	-	-	-	-	-	-	Not Covered
StRandReady	-	-	0	-	1	-	-	-	-	-	-	-	Not Covered
StRandReady	-	-	0	-	0	-	-	-	-	-	-	-	Not Covered
StRandEdn	-	-	-	-	-	1	-	-	-	-	-	-	Not Covered
StRandEdn	-	-	-	-	-	0	1	1	1	-	-	-	Not Covered
StRandEdn	-	-	-	-	-	0	1	1	0	-	-	-	Not Covered
StRandEdn	-	-	-	-	-	0	1	0	-	-	-	-	Not Covered
StRandEdn	-	-	-	-	-	0	0	-	-	1	-	-	Not Covered
StRandEdn	-	-	-	-	-	0	0	-	-	0	-	-	Not Covered
StSwSeedWait	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
StSwSeedWait	-	-	-	-	-	-	-	-	-	-	0	-	Not Covered
StRandGenerate	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StRandErrWaitExpired	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StRandErrIncorrectMode	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StRandErr	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
StRandErr	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	781	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	788	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.gen_entropy.u_entropy

	Line No.	Total	Covered	Percent
TOTAL		1610	0	0.00
ALWAYS	241	4	0	0.00
ALWAYS	250	4	0	0.00
ALWAYS	259	8	0	0.00
CONT_ASSIGN	270	1	0	0.00
ALWAYS	273	6	0	0.00
ALWAYS	284	8	0	0.00
CONT_ASSIGN	295	1	0	0.00
ALWAYS	304	3	0	0.00
CONT_ASSIGN	308	1	0	0.00
CONT_ASSIGN	311	1	0	0.00
CONT_ASSIGN	314	1	0	0.00
CONT_ASSIGN	336	1	0	0.00
ALWAYS	339	6	0	0.00
ALWAYS	345	4	0	0.00
CONT_ASSIGN	392	1	0	0.00
CONT_ASSIGN	400	1	0	0.00
CONT_ASSIGN	400	1	0	0.00
CONT_ASSIGN	400	1	0	0.00
CONT_ASSIGN	400	1	0	0.00
CONT_ASSIGN	400	1	0	0.00
CONT_ASSIGN	408	1	0	0.00
CONT_ASSIGN	408	1	0	0.00
CONT_ASSIGN	408	1	0	0.00
CONT_ASSIGN	408	1	0	0.00
CONT_ASSIGN	408	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
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CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
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CONT_ASSIGN	414	1	0	0.00
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CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
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CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
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CONT_ASSIGN	414	1	0	0.00
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CONT_ASSIGN	414	1	0	0.00
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CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
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CONT_ASSIGN	414	1	0	0.00
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CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
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CONT_ASSIGN	414	1	0	0.00
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CONT_ASSIGN	414	1	0	0.00
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CONT_ASSIGN	414	1	0	0.00
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CONT_ASSIGN	414	1	0	0.00
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CONT_ASSIGN	414	1	0	0.00
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CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
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CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
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CONT_ASSIGN	414	1	0	0.00
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CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
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CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	457	1	0	0.00
CONT_ASSIGN	462	1	0	0.00
ALWAYS	465	3	0	0.00
CONT_ASSIGN	475	1	0	0.00
ALWAYS	480	3	0	0.00
CONT_ASSIGN	490	1	0	0.00
CONT_ASSIGN	491	1	0	0.00
ALWAYS	495	6	0	0.00
CONT_ASSIGN	505	1	0	0.00
CONT_ASSIGN	523	1	0	0.00
CONT_ASSIGN	524	1	0	0.00
ALWAYS	526	3	0	0.00
CONT_ASSIGN	536	1	0	0.00
ALWAYS	545	3	0	0.00
ALWAYS	550	78	0	0.00
ALWAYS	788	3	0	0.00
CONT_ASSIGN	797	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
241	0	1
242	0	1
243	0	1
244	0	1
			==> MISSING_ELSE
250	0	1
251	0	1
252	0	1
253	0	1
			==> MISSING_ELSE
259	0	1
260	0	1
261	0	1
262	0	1
263	0	1
264	0	1
265	0	1
266	0	1
			==> MISSING_ELSE
270	0	1
273	0	1
274	0	1
275	0	1
276	0	1
277	0	1
278	0	1
			==> MISSING_ELSE
284	0	1
285	0	1
286	0	1
287	0	1
288	0	1
289	0	1
290	0	1
291	0	1
			==> MISSING_ELSE
295	0	1
304	0	2
305	0	1
308	0	1
311	0	1
314	0	1
336	0	1
339	0	2
340	0	2
341	0	2
			==> MISSING_ELSE
345	0	2
346	0	2
			==> MISSING_ELSE
392	0	1
400	0	5
408	0	5
414	0	640
451	0	1
453	0	800
457	0	1
462	0	1
465	0	1
466	0	1
468	0	1
475	0	1
480	0	1
481	0	1
483	0	1
490	0	1
491	0	1
495	0	1
496	0	1
497	0	1
498	0	1
499	0	1
500	0	1
			==> MISSING_ELSE
505	0	1
523	0	1
524	0	1
526	0	1
527	0	1
529	0	1
536	0	1
545	0	3
550	0	1
551	0	1
554	0	1
555	0	1
557	0	1
560	0	1
568	0	1
569	0	1
572	0	1
576	0	1
580	0	1
583	0	1
586	0	1
589	0	1
591	0	1
593	0	1
596	0	1
598	0	1
600	0	1
602	0	1
606	0	1
609	0	1
619	0	1
624	0	1
629	0	1
631	0	1
633	0	1
642	0	1
643	0	1
645	0	1
646	0	1
648	0	1
650	0	1
652	0	1
654	0	1
657	0	1
660	0	1
662	0	1
668	0	1
671	0	1
673	0	1
675	0	1
677	0	1
678	0	1
680	0	1
681	0	1
683	0	1
684	0	1
685	0	1
			==> MISSING_ELSE
688	0	1
690	0	1
697	0	1
699	0	1
700	0	1
702	0	1
707	0	1
709	0	1
710	0	1
712	0	1
714	0	1
716	0	1
722	0	1
726	0	1
727	0	1
729	0	1
733	0	1
735	0	1
742	0	1
744	0	1
752	0	1
755	0	1
757	0	1
758	0	1
761	0	1
768	0	1
769	0	1
781	0	1
782	0	1
			==> MISSING_ELSE
788	0	1
789	0	1
791	0	1
797	0	1

---

Cond Coverage for Instance : tb.dut.gen_entropy.u_entropy

	Total	Covered	Percent
Conditions	188	0	0.00
Logical	188	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       265
 EXPRESSION (timer_enable && timer_pulse && ((|timer_value)))
             ------1-----    -----2-----    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       277
 EXPRESSION (timer_enable && (timer_value == '0))
             ------1-----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       277
 SUB-EXPRESSION (timer_value == '0)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       288
 EXPRESSION (timer_enable && (prescaler_cnt == '0))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       288
 SUB-EXPRESSION (prescaler_cnt == '0)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       295
 EXPRESSION (timer_enable && (prescaler_cnt == '0))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       295
 SUB-EXPRESSION (prescaler_cnt == '0)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       311
 EXPRESSION (hash_cnt_clr_i || threshold_hit || entropy_refresh_req_i)
             -------1------    ------2------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       314
 EXPRESSION (hash_progress_q && ((!hash_progress_d)))
             -------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       336
 EXPRESSION (((|hash_threshold_i)) && (hash_threshold_i <= hash_cnt_o))
             ----------1----------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       408
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[0] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       408
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       408
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[1] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       408
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       408
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[2] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       408
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       408
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[3] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       408
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       408
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[4] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       408
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       438
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       462
 EXPRESSION (aux_update ? lfsr_data_permuted[(kmac_pkg::EntropyLfsrW - 1)] : aux_rand_q)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       475
 EXPRESSION (aux_update ? lfsr_data_permuted[(kmac_pkg::EntropyLfsrW - 2)-:4] : ({1'b0, lfsr_en_rand_q[3:1]}))
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       523
 EXPRESSION (entropy_req | entropy_req_hold_q)
             -----1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       524
 EXPRESSION ((entropy_req_hold_q | entropy_req) & ((~entropy_ack_i)))
             -----------------1----------------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       524
 SUB-EXPRESSION (entropy_req_hold_q | entropy_req)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       536
 EXPRESSION (hash_count_error | seed_idx_count_error)
             --------1-------   ----------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       633
 EXPRESSION (rand_consumed_i && ((fast_process_i && in_keyblock_i) || ((!fast_process_i))))
             -------1-------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       633
 SUB-EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
                 ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       633
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       652
 EXPRESSION ((mode_q == EntropyModeEdn) && (entropy_refresh_req_i || threshold_hit_q))
             -------------1------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       652
 SUB-EXPRESSION (mode_q == EntropyModeEdn)
                -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       652
 SUB-EXPRESSION (entropy_refresh_req_i || threshold_hit_q)
                 ----------1----------    -------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       673
 EXPRESSION (timer_expired && non_zero_wait_timer_limit)
             ------1------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       683
 EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
             ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       683
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       690
 EXPRESSION (rand_consumed_i && ((fast_process_i && in_keyblock_i) || ((!fast_process_i))))
             -------1-------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       690
 SUB-EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
                 ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       690
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       755
 EXPRESSION (rand_consumed_i & ((fast_process_i & in_keyblock_i) | ((~fast_process_i))))
             -------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       755
 SUB-EXPRESSION ((fast_process_i & in_keyblock_i) | ((~fast_process_i)))
                 ----------------1---------------   ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       755
 SUB-EXPRESSION (fast_process_i & in_keyblock_i)
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       797
 EXPRESSION ((st != StRandReset) ? MuBi4True : MuBi4False)
             ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       797
 SUB-EXPRESSION (st != StRandReset)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Instance : tb.dut.gen_entropy.u_entropy

Summary for FSM :: st

	Total	Covered	Percent
States	9	0	0.00	(Not included in score)
Transitions	16	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StRandEdn	606	Not Covered
StRandErr	733	Not Covered
StRandErrIncorrectMode	615	Not Covered
StRandErrWaitExpired	675	Not Covered
StRandGenerate	646	Not Covered
StRandReady	650	Not Covered
StRandReset	619	Not Covered
StSwSeedWait	602	Not Covered
StTerminalError	782	Not Covered

transitions	Line No.	Covered	Tests	Exclude Annotation
StRandEdn->StRandErrWaitExpired	675	Not Covered
StRandEdn->StRandGenerate	681	Not Covered
StRandEdn->StTerminalError	782	Not Covered
StRandErr->StRandReset	758	Not Covered
StRandErr->StTerminalError	782	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StRandErrIncorrectMode->StRandErr	742	Not Covered
StRandErrIncorrectMode->StTerminalError	782	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StRandErrWaitExpired->StRandErr	733	Not Covered
StRandErrWaitExpired->StTerminalError	782	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StRandGenerate->StRandReady	729	Not Covered
StRandGenerate->StTerminalError	782	Not Covered
StRandReady->StRandEdn	654	Not Covered
StRandReady->StRandGenerate	646	Not Covered
StRandReady->StTerminalError	782	Not Covered
StRandReset->StRandEdn	606	Not Covered
StRandReset->StRandErrIncorrectMode	615	Not Covered
StRandReset->StSwSeedWait	602	Not Covered
StRandReset->StTerminalError	782	Not Covered
StSwSeedWait->StRandGenerate	710	Not Covered
StSwSeedWait->StTerminalError	782	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.

---

Branch Coverage for Instance : tb.dut.gen_entropy.u_entropy

	Line No.	Total	Covered	Percent
Branches		84	0	0.00
TERNARY	462	2	0	0.00
TERNARY	475	2	0	0.00
TERNARY	797	2	0	0.00
TERNARY	408	2	0	0.00
TERNARY	408	2	0	0.00
TERNARY	408	2	0	0.00
TERNARY	408	2	0	0.00
TERNARY	408	2	0	0.00
IF	241	3	0	0.00
IF	250	3	0	0.00
IF	259	5	0	0.00
IF	273	4	0	0.00
IF	284	5	0	0.00
IF	304	2	0	0.00
IF	339	4	0	0.00
IF	345	3	0	0.00
IF	465	2	0	0.00
IF	480	2	0	0.00
IF	495	4	0	0.00
IF	526	2	0	0.00
IF	545	2	0	0.00
CASE	591	23	0	0.00
IF	781	2	0	0.00
IF	788	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	462	(aux_update) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	475	(aux_update) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	797	((st != StRandReset)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	408	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	408	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	408	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	408	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	408	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	241	if ((!rst_ni))
-2-:	243	if (timer_update)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	250	if ((!rst_ni))
-2-:	252	if (timer_update)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	259	if ((!rst_ni))
-2-:	261	if (timer_update)
-3-:	263	if (timer_expired)
-4-:	265	if (((timer_enable && timer_pulse) && (|timer_value)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Not Covered
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	273	if ((!rst_ni))
-2-:	275	if (timer_update)
-3-:	277	if ((timer_enable && (timer_value == '0)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	284	if ((!rst_ni))
-2-:	286	if (timer_update)
-3-:	288	if ((timer_enable && (prescaler_cnt == '0)))
-4-:	290	if (timer_enable)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Not Covered
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	304	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	339	if ((!rst_ni))
-2-:	340	if (threshold_hit_clr)
-3-:	341	if (threshold_hit)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	345	if ((!rst_ni))
-2-:	346	if (mode_latch)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	465	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	480	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	495	if ((!rst_ni))
-2-:	497	if (rand_valid_set)
-3-:	499	if (rand_valid_clear)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	526	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	545	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	591	case (st)
-2-:	593	if (entropy_ready_i)
-3-:	600	case (mode_i)
-4-:	633	if ((rand_consumed_i && ((fast_process_i && in_keyblock_i) || (!fast_process_i))))
-5-:	645	if (ready_phase_q)
-6-:	652	if (((mode_q == EntropyModeEdn) && (entropy_refresh_req_i || threshold_hit_q)))
-7-:	673	if ((timer_expired && non_zero_wait_timer_limit))
-8-:	677	if (entropy_ack_i)
-9-:	680	if (lfsr_seed_done)
-10-:	683	if (((fast_process_i && in_keyblock_i) || (!fast_process_i)))
-11-:	690	if ((rand_consumed_i && ((fast_process_i && in_keyblock_i) || (!fast_process_i))))
-12-:	709	if (lfsr_seed_done)
-13-:	757	if (err_processed_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StRandReset	1	EntropyModeSw	-	-	-	-	-	-	-	-	-	-	Not Covered
StRandReset	1	EntropyModeEdn	-	-	-	-	-	-	-	-	-	-	Not Covered
StRandReset	1	default	-	-	-	-	-	-	-	-	-	-	Not Covered
StRandReset	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StRandReady	-	-	1	1	-	-	-	-	-	-	-	-	Not Covered
StRandReady	-	-	1	0	-	-	-	-	-	-	-	-	Not Covered
StRandReady	-	-	0	-	1	-	-	-	-	-	-	-	Not Covered
StRandReady	-	-	0	-	0	-	-	-	-	-	-	-	Not Covered
StRandEdn	-	-	-	-	-	1	-	-	-	-	-	-	Not Covered
StRandEdn	-	-	-	-	-	0	1	1	1	-	-	-	Not Covered
StRandEdn	-	-	-	-	-	0	1	1	0	-	-	-	Not Covered
StRandEdn	-	-	-	-	-	0	1	0	-	-	-	-	Not Covered
StRandEdn	-	-	-	-	-	0	0	-	-	1	-	-	Not Covered
StRandEdn	-	-	-	-	-	0	0	-	-	0	-	-	Not Covered
StSwSeedWait	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
StSwSeedWait	-	-	-	-	-	-	-	-	-	-	0	-	Not Covered
StRandGenerate	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StRandErrWaitExpired	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StRandErrIncorrectMode	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StRandErr	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
StRandErr	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	781	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	788	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered