Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_intr_hw
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.intr_kmac_done 0.00 0.00 0.00 0.00
tb.dut.intr_fifo_empty 0.00 0.00 0.00 0.00
tb.dut.intr_kmac_err 0.00 0.00 0.00 0.00


Module Instance : tb.dut.intr_kmac_done

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.32 0.00 0.00 6.61 0.00 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.intr_fifo_empty

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.32 0.00 0.00 6.61 0.00 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.intr_kmac_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.32 0.00 0.00 6.61 0.00 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_intr_hw
Line No.TotalCoveredPercent
TOTAL700.00
CONT_ASSIGN47100.00
CONT_ASSIGN49100.00
CONT_ASSIGN52100.00
CONT_ASSIGN54100.00
ALWAYS80300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 0 1
49 0 1
52 0 1
54 0 1
80 0 1
81 0 1
83 0 1

Cond Coverage for Module : prim_intr_hw
TotalCoveredPercent
Conditions1200.00
Logical1200.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Branch Coverage for Module : prim_intr_hw
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 80 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.intr_kmac_done
Line No.TotalCoveredPercent
TOTAL700.00
CONT_ASSIGN47100.00
CONT_ASSIGN49100.00
CONT_ASSIGN52100.00
CONT_ASSIGN54100.00
ALWAYS80300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 0 1
49 0 1
52 0 1
54 0 1
80 0 1
81 0 1
83 0 1

Cond Coverage for Instance : tb.dut.intr_kmac_done
TotalCoveredPercent
Conditions1200.00
Logical1200.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Branch Coverage for Instance : tb.dut.intr_kmac_done
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 80 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.intr_fifo_empty
Line No.TotalCoveredPercent
TOTAL700.00
CONT_ASSIGN47100.00
CONT_ASSIGN49100.00
CONT_ASSIGN52100.00
CONT_ASSIGN54100.00
ALWAYS80300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 0 1
49 0 1
52 0 1
54 0 1
80 0 1
81 0 1
83 0 1

Cond Coverage for Instance : tb.dut.intr_fifo_empty
TotalCoveredPercent
Conditions1200.00
Logical1200.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Branch Coverage for Instance : tb.dut.intr_fifo_empty
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 80 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.intr_kmac_err
Line No.TotalCoveredPercent
TOTAL700.00
CONT_ASSIGN47100.00
CONT_ASSIGN49100.00
CONT_ASSIGN52100.00
CONT_ASSIGN54100.00
ALWAYS80300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 0 1
49 0 1
52 0 1
54 0 1
80 0 1
81 0 1
83 0 1

Cond Coverage for Instance : tb.dut.intr_kmac_err
TotalCoveredPercent
Conditions1200.00
Logical1200.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Branch Coverage for Instance : tb.dut.intr_kmac_err
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 80 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

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