Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1420772	14313	0	0
DepthKnown_A	1420772	1373602	0	0
RvalidKnown_A	1420772	1373602	0	0
WreadyKnown_A	1420772	1373602	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	14313	0	0
T4	2198	119	0	0
T5	2778	0	0	0
T6	7170	458	0	0
T7	5782	0	0	0
T14	2026	0	0	0
T18	6485	0	0	0
T19	2219	717	0	0
T20	2927	0	0	0
T21	0	170	0	0
T22	0	413	0	0
T23	0	335	0	0
T24	0	492	0	0
T25	0	255	0	0
T26	0	1174	0	0
T27	0	217	0	0
T31	1323	0	0	0
T32	2175	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	1373602	0	0
T1	9954	9179	0	0
T2	1104	1037	0	0
T3	104103	104028	0	0
T4	2198	2132	0	0
T5	2778	2491	0	0
T6	7170	7095	0	0
T14	2026	1974	0	0
T18	6485	6435	0	0
T19	2219	2117	0	0
T20	2927	2872	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	1373602	0	0
T1	9954	9179	0	0
T2	1104	1037	0	0
T3	104103	104028	0	0
T4	2198	2132	0	0
T5	2778	2491	0	0
T6	7170	7095	0	0
T14	2026	1974	0	0
T18	6485	6435	0	0
T19	2219	2117	0	0
T20	2927	2872	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	1373602	0	0
T1	9954	9179	0	0
T2	1104	1037	0	0
T3	104103	104028	0	0
T4	2198	2132	0	0
T5	2778	2491	0	0
T6	7170	7095	0	0
T14	2026	1974	0	0
T18	6485	6435	0	0
T19	2219	2117	0	0
T20	2927	2872	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1420772	18637	0	0
DepthKnown_A	1420772	1373602	0	0
RvalidKnown_A	1420772	1373602	0	0
WreadyKnown_A	1420772	1373602	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	18637	0	0
T4	2198	111	0	0
T5	2778	0	0	0
T6	7170	1459	0	0
T7	5782	0	0	0
T14	2026	0	0	0
T18	6485	0	0	0
T19	2219	400	0	0
T20	2927	0	0	0
T21	0	159	0	0
T22	0	216	0	0
T23	0	181	0	0
T24	0	1724	0	0
T25	0	221	0	0
T26	0	652	0	0
T27	0	785	0	0
T31	1323	0	0	0
T32	2175	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	1373602	0	0
T1	9954	9179	0	0
T2	1104	1037	0	0
T3	104103	104028	0	0
T4	2198	2132	0	0
T5	2778	2491	0	0
T6	7170	7095	0	0
T14	2026	1974	0	0
T18	6485	6435	0	0
T19	2219	2117	0	0
T20	2927	2872	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	1373602	0	0
T1	9954	9179	0	0
T2	1104	1037	0	0
T3	104103	104028	0	0
T4	2198	2132	0	0
T5	2778	2491	0	0
T6	7170	7095	0	0
T14	2026	1974	0	0
T18	6485	6435	0	0
T19	2219	2117	0	0
T20	2927	2872	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	1373602	0	0
T1	9954	9179	0	0
T2	1104	1037	0	0
T3	104103	104028	0	0
T4	2198	2132	0	0
T5	2778	2491	0	0
T6	7170	7095	0	0
T14	2026	1974	0	0
T18	6485	6435	0	0
T19	2219	2117	0	0
T20	2927	2872	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1420772	284922	0	0
DepthKnown_A	1420772	1373602	0	0
RvalidKnown_A	1420772	1373602	0	0
WreadyKnown_A	1420772	1373602	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	284922	0	0
T1	9954	1449	0	0
T2	1104	22	0	0
T3	104103	14689	0	0
T4	2198	139	0	0
T5	2778	372	0	0
T6	7170	770	0	0
T14	2026	22	0	0
T18	6485	1485	0	0
T19	2219	354	0	0
T20	2927	581	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	1373602	0	0
T1	9954	9179	0	0
T2	1104	1037	0	0
T3	104103	104028	0	0
T4	2198	2132	0	0
T5	2778	2491	0	0
T6	7170	7095	0	0
T14	2026	1974	0	0
T18	6485	6435	0	0
T19	2219	2117	0	0
T20	2927	2872	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	1373602	0	0
T1	9954	9179	0	0
T2	1104	1037	0	0
T3	104103	104028	0	0
T4	2198	2132	0	0
T5	2778	2491	0	0
T6	7170	7095	0	0
T14	2026	1974	0	0
T18	6485	6435	0	0
T19	2219	2117	0	0
T20	2927	2872	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	1373602	0	0
T1	9954	9179	0	0
T2	1104	1037	0	0
T3	104103	104028	0	0
T4	2198	2132	0	0
T5	2778	2491	0	0
T6	7170	7095	0	0
T14	2026	1974	0	0
T18	6485	6435	0	0
T19	2219	2117	0	0
T20	2927	2872	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1420772	288633	0	0
DepthKnown_A	1420772	1373602	0	0
RvalidKnown_A	1420772	1373602	0	0
WreadyKnown_A	1420772	1373602	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	288633	0	0
T1	9954	1333	0	0
T2	1104	22	0	0
T3	104103	14685	0	0
T4	2198	127	0	0
T5	2778	896	0	0
T6	7170	2101	0	0
T14	2026	87	0	0
T18	6485	3174	0	0
T19	2219	225	0	0
T20	2927	1258	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	1373602	0	0
T1	9954	9179	0	0
T2	1104	1037	0	0
T3	104103	104028	0	0
T4	2198	2132	0	0
T5	2778	2491	0	0
T6	7170	7095	0	0
T14	2026	1974	0	0
T18	6485	6435	0	0
T19	2219	2117	0	0
T20	2927	2872	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	1373602	0	0
T1	9954	9179	0	0
T2	1104	1037	0	0
T3	104103	104028	0	0
T4	2198	2132	0	0
T5	2778	2491	0	0
T6	7170	7095	0	0
T14	2026	1974	0	0
T18	6485	6435	0	0
T19	2219	2117	0	0
T20	2927	2872	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	1373602	0	0
T1	9954	9179	0	0
T2	1104	1037	0	0
T3	104103	104028	0	0
T4	2198	2132	0	0
T5	2778	2491	0	0
T6	7170	7095	0	0
T14	2026	1974	0	0
T18	6485	6435	0	0
T19	2219	2117	0	0
T20	2927	2872	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0