Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
1.32	0.00	0.00	6.61	0.00	0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1420772	2860	0	0
entropy_period_rd_A	1420772	799	0	0
intr_enable_rd_A	1420772	1154	0	0
prefix_0_rd_A	1420772	718	0	0
prefix_10_rd_A	1420772	775	0	0
prefix_1_rd_A	1420772	701	0	0
prefix_2_rd_A	1420772	749	0	0
prefix_3_rd_A	1420772	782	0	0
prefix_4_rd_A	1420772	661	0	0
prefix_5_rd_A	1420772	735	0	0
prefix_6_rd_A	1420772	729	0	0
prefix_7_rd_A	1420772	680	0	0
prefix_8_rd_A	1420772	770	0	0
prefix_9_rd_A	1420772	816	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	2860	0	0
T1	9954	2	0	0
T2	1104	0	0	0
T3	104103	0	0	0
T4	2198	0	0	0
T5	2778	0	0	0
T6	7170	145	0	0
T14	2026	0	0	0
T18	6485	0	0	0
T19	2219	1	0	0
T20	2927	0	0	0
T21	0	59	0	0
T23	0	2	0	0
T24	0	185	0	0
T25	0	123	0	0
T26	0	40	0	0
T33	0	3	0	0
T71	0	2	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	799	0	0
T5	2778	5	0	0
T6	7170	0	0	0
T7	5782	0	0	0
T14	2026	0	0	0
T18	6485	31	0	0
T19	2219	0	0	0
T20	2927	11	0	0
T24	0	2	0	0
T31	1323	0	0	0
T32	2175	0	0	0
T37	44010	0	0	0
T41	0	83	0	0
T43	0	13	0	0
T61	0	69	0	0
T62	0	65	0	0
T74	0	11	0	0
T75	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	1154	0	0
T5	2778	7	0	0
T6	7170	0	0	0
T7	5782	0	0	0
T14	2026	5	0	0
T18	6485	0	0	0
T19	2219	0	0	0
T20	2927	12	0	0
T31	1323	0	0	0
T32	2175	0	0	0
T37	44010	0	0	0
T41	0	114	0	0
T43	0	2	0	0
T61	0	82	0	0
T62	0	81	0	0
T74	0	6	0	0
T76	0	7	0	0
T77	0	8	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	718	0	0
T5	2778	10	0	0
T6	7170	0	0	0
T7	5782	0	0	0
T14	2026	0	0	0
T18	6485	22	0	0
T19	2219	0	0	0
T20	2927	5	0	0
T31	1323	0	0	0
T32	2175	0	0	0
T37	44010	0	0	0
T41	0	136	0	0
T43	0	1	0	0
T61	0	47	0	0
T62	0	65	0	0
T63	0	38	0	0
T74	0	1	0	0
T75	0	4	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	775	0	0
T5	2778	10	0	0
T6	7170	0	0	0
T7	5782	0	0	0
T14	2026	0	0	0
T18	6485	4	0	0
T19	2219	0	0	0
T20	2927	8	0	0
T29	0	1	0	0
T31	1323	0	0	0
T32	2175	0	0	0
T37	44010	0	0	0
T41	0	186	0	0
T43	0	11	0	0
T61	0	67	0	0
T62	0	61	0	0
T63	0	29	0	0
T75	0	3	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	701	0	0
T5	2778	3	0	0
T6	7170	0	0	0
T7	5782	0	0	0
T14	2026	0	0	0
T18	6485	19	0	0
T19	2219	0	0	0
T20	2927	10	0	0
T29	0	1	0	0
T31	1323	0	0	0
T32	2175	0	0	0
T37	44010	0	0	0
T41	0	153	0	0
T43	0	2	0	0
T61	0	33	0	0
T62	0	68	0	0
T63	0	10	0	0
T74	0	5	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	749	0	0
T5	2778	3	0	0
T6	7170	0	0	0
T7	5782	0	0	0
T14	2026	0	0	0
T18	6485	15	0	0
T19	2219	0	0	0
T20	2927	2	0	0
T31	1323	0	0	0
T32	2175	0	0	0
T37	44010	0	0	0
T41	0	134	0	0
T43	0	6	0	0
T61	0	61	0	0
T62	0	51	0	0
T74	0	7	0	0
T75	0	7	0	0
T77	0	8	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	782	0	0
T5	2778	7	0	0
T6	7170	0	0	0
T7	5782	0	0	0
T14	2026	0	0	0
T18	6485	12	0	0
T19	2219	0	0	0
T20	2927	5	0	0
T31	1323	0	0	0
T32	2175	0	0	0
T37	44010	0	0	0
T41	0	152	0	0
T43	0	11	0	0
T61	0	47	0	0
T62	0	59	0	0
T74	0	4	0	0
T75	0	1	0	0
T77	0	5	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	661	0	0
T5	2778	14	0	0
T6	7170	0	0	0
T7	5782	0	0	0
T14	2026	0	0	0
T18	6485	5	0	0
T19	2219	0	0	0
T20	2927	5	0	0
T31	1323	0	0	0
T32	2175	0	0	0
T37	44010	0	0	0
T41	0	162	0	0
T43	0	5	0	0
T61	0	24	0	0
T62	0	52	0	0
T74	0	5	0	0
T75	0	5	0	0
T77	0	8	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	735	0	0
T5	2778	1	0	0
T6	7170	0	0	0
T7	5782	0	0	0
T14	2026	0	0	0
T18	6485	6	0	0
T19	2219	0	0	0
T20	2927	11	0	0
T31	1323	0	0	0
T32	2175	0	0	0
T37	44010	0	0	0
T41	0	125	0	0
T43	0	17	0	0
T61	0	43	0	0
T62	0	71	0	0
T74	0	4	0	0
T75	0	12	0	0
T77	0	7	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	729	0	0
T5	2778	11	0	0
T6	7170	0	0	0
T7	5782	0	0	0
T14	2026	0	0	0
T18	6485	21	0	0
T19	2219	0	0	0
T20	2927	5	0	0
T31	1323	0	0	0
T32	2175	0	0	0
T37	44010	0	0	0
T41	0	110	0	0
T43	0	4	0	0
T61	0	52	0	0
T62	0	52	0	0
T74	0	7	0	0
T75	0	8	0	0
T77	0	7	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	680	0	0
T5	2778	3	0	0
T6	7170	0	0	0
T7	5782	0	0	0
T14	2026	0	0	0
T18	6485	25	0	0
T19	2219	0	0	0
T20	2927	11	0	0
T31	1323	0	0	0
T32	2175	0	0	0
T37	44010	0	0	0
T41	0	116	0	0
T43	0	9	0	0
T61	0	57	0	0
T62	0	56	0	0
T63	0	19	0	0
T75	0	4	0	0
T77	0	1	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	770	0	0
T5	2778	14	0	0
T6	7170	8	0	0
T7	5782	0	0	0
T14	2026	0	0	0
T18	6485	12	0	0
T19	2219	0	0	0
T20	2927	15	0	0
T31	1323	0	0	0
T32	2175	0	0	0
T37	44010	0	0	0
T41	0	114	0	0
T43	0	5	0	0
T61	0	52	0	0
T62	0	51	0	0
T74	0	7	0	0
T77	0	1	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1420772	816	0	0
T5	2778	2	0	0
T6	7170	0	0	0
T7	5782	0	0	0
T14	2026	0	0	0
T18	6485	13	0	0
T19	2219	0	0	0
T20	2927	8	0	0
T24	0	5	0	0
T31	1323	0	0	0
T32	2175	0	0	0
T37	44010	0	0	0
T41	0	174	0	0
T43	0	5	0	0
T61	0	59	0	0
T62	0	97	0	0
T74	0	2	0	0
T77	0	9	0	0