KMAC/MASKED Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: `671f2b57e2`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.601m	49.349ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.130s	24.384us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.220s	33.649us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	23.760s	6.194ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.850s	458.830us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.330s	31.149us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.220s	33.649us	20	20	100.00
		kmac_csr_aliasing	10.850s	458.830us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	12.055us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.500s	39.204us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	58.846m	188.803ms	49	50	98.00
V2	burst_write	kmac_burst_write	24.655m	55.534ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	46.723m	1.233s	50	50	100.00
		kmac_test_vectors_sha3_256	43.911m	1.181s	50	50	100.00
		kmac_test_vectors_sha3_384	33.120m	598.655ms	50	50	100.00
		kmac_test_vectors_sha3_512	23.707m	474.787ms	50	50	100.00
		kmac_test_vectors_shake_128	1.774h	1.074s	50	50	100.00
		kmac_test_vectors_shake_256	1.595h	1.462s	50	50	100.00
		kmac_test_vectors_kmac	7.180s	265.018us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.410s	2.874ms	50	50	100.00
V2	sideload	kmac_sideload	8.527m	19.194ms	49	50	98.00
V2	app	kmac_app	6.481m	25.214ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.667m	26.660ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.846m	7.341ms	48	50	96.00
V2	error	kmac_error	8.399m	35.770ms	50	50	100.00
V2	key_error	kmac_key_error	8.650s	11.153ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	49.620s	12.665ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	48.850s	2.047ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.426m	40.544ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.046m	6.433ms	50	50	100.00
V2	stress_all	kmac_stress_all	1.045h	568.992ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.870s	41.819us	50	50	100.00
V2	alert_test	kmac_alert_test	0.960s	26.811us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.340s	942.842us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.340s	942.842us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.130s	24.384us	5	5	100.00
		kmac_csr_rw	1.220s	33.649us	20	20	100.00
		kmac_csr_aliasing	10.850s	458.830us	5	5	100.00
		kmac_same_csr_outstanding	2.770s	216.184us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.130s	24.384us	5	5	100.00
		kmac_csr_rw	1.220s	33.649us	20	20	100.00
		kmac_csr_aliasing	10.850s	458.830us	5	5	100.00
		kmac_same_csr_outstanding	2.770s	216.184us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.580s	723.440us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.580s	723.440us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.580s	723.440us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.580s	723.440us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.190s	527.828us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.780m	25.188ms	5	5	100.00
		kmac_tl_intg_err	6.140s	589.324us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.140s	589.324us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.046m	6.433ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.601m	49.349ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.527m	19.194ms	49	50	98.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.580s	723.440us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.780m	25.188ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.780m	25.188ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.780m	25.188ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.601m	49.349ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.046m	6.433ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.780m	25.188ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.755m	51.550ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.601m	49.349ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.042h	234.901ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			1266	1290	98.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.16	98.38	93.15	99.93	95.45	96.04	98.89	98.31

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 13 failures:
- Test kmac_stress_all_with_rand_reset has 13 failures.
  - 2.kmac_stress_all_with_rand_reset.24850957853732203157637732841037148500923748838059139653916814526799266009917
    Line 716, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28972157353 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 28972157353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.kmac_stress_all_with_rand_reset.25502092453365455917260766793782086975044679672584282374317939825064992988680
    Line 975, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 46039954654 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 46039954654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 5 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 1.kmac_stress_all_with_rand_reset.68627637478799277842087363107522374846715235897345333807567461231356343304970
    Line 1130, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 291039474878 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 291039474878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.kmac_stress_all_with_rand_reset.21153376534440681966901019984631160465433193081758988663251964898953943499933
    Line 528, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 85749100900 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 85749100900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test kmac_stress_all has 1 failures.
  - 27.kmac_stress_all.18703370256572407606888856537620380144248913802608096518182369244435049707554
    Line 353, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 95973025070 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 95973025070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_entropy_refresh has 2 failures.

9.kmac_entropy_refresh.1717652347525648342637521339408780790039214702342627571397333740745061591453
Line 323, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 16602973892 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (143 [0x8f] vs 189 [0xbd]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 16602973892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.kmac_entropy_refresh.85335273086642485994300693768152017995116328927545116373866170158018865702214
Line 402, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 10409373706 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (231 [0xe7] vs 36 [0x24]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10409373706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

36.kmac_app.109405889322013458135662768977781699413446815172809299098487766599604589757989
Line 339, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_app/latest/run.log

  UVM_FATAL @ 17491830069 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (183 [0xb7] vs 129 [0x81]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 17491830069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 2.kmac_shadow_reg_errors_with_csr_rw.7988990146212206920880860119386401991002362822093331293568807420176355937353
    Line 279, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  33605424 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (3062431404 [0xb688feac] vs 0 [0x0]) Regname: kmac_reg_block.prefix_8.prefix_0 reset value: 0x0
  UVM_INFO @  33605424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_sideload has 1 failures.
  - 21.kmac_sideload.108742808084318027252013461189249338623646761298132271284457717611607465995782
    Line 276, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_sideload/latest/run.log
```
  UVM_ERROR @  44808736 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  44808736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_long_msg_and_output has 1 failures.
  - 41.kmac_long_msg_and_output.49340223119279196650798445049417551023867429229103636923631310225510101097233
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:677981e5-a381-4927-80a0-ee763aac1cc4
```