Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	258983996	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

186773921

1

T1

11

T2

609

T3

140

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	230342990	1			T1	11		T2	307		T3	268
values[0x0]	103385986	1			T1	7		T2	155		T3	5
values[0x1]	112028941	1			T1	4		T2	148		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	201099676	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

244658241

1

T1

13

T2

609

T3

175

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1360862	1			T2	3		T62	8		T69	7
valid_sources[0x01]	2106441	1			T2	2		T3	5		T69	2
valid_sources[0x02]	2007565	1			T55	2		T59	9		T62	8
valid_sources[0x03]	1366571	1			T2	2		T3	8		T55	1
valid_sources[0x04]	1365635	1			T2	8		T59	5		T69	5
valid_sources[0x05]	1362673	1			T2	1		T69	12		T71	56
valid_sources[0x06]	1358928	1			T69	7		T71	21		T72	3
valid_sources[0x07]	1358286	1			T2	7		T56	24		T69	2
valid_sources[0x08]	1816824	1			T2	5		T59	14		T72	6
valid_sources[0x09]	1369849	1			T58	5		T69	3		T72	5
valid_sources[0x0a]	1355696	1			T3	3		T69	3		T71	12
valid_sources[0x0b]	1508222	1			T2	3		T69	8		T71	15
valid_sources[0x0c]	1358522	1			T2	4		T3	1		T59	19
valid_sources[0x0d]	1363503	1			T2	1		T59	13		T71	18
valid_sources[0x0e]	1360579	1			T2	1		T3	1		T59	1
valid_sources[0x0f]	1351688	1			T2	5		T3	1		T55	2
valid_sources[0x10]	2100977	1			T69	5		T72	6		T85	9
valid_sources[0x11]	1359578	1			T3	1		T69	15		T61	4
valid_sources[0x12]	1366418	1			T59	10		T62	7		T69	8
valid_sources[0x13]	1355343	1			T2	1		T3	4		T59	13
valid_sources[0x14]	1408382	1			T2	2		T3	5		T59	14
valid_sources[0x15]	1893012	1			T2	1		T3	1		T59	10
valid_sources[0x16]	1426764	1			T2	3		T72	5		T85	1
valid_sources[0x17]	1359285	1			T55	1		T57	2		T62	11
valid_sources[0x18]	2262596	1			T3	1		T59	35		T61	2
valid_sources[0x19]	1542640	1			T59	17		T69	4		T71	10
valid_sources[0x1a]	1367815	1			T2	1		T59	15		T62	4
valid_sources[0x1b]	1427262	1			T2	2		T62	2		T69	9
valid_sources[0x1c]	1361703	1			T2	2		T59	1		T69	6
valid_sources[0x1d]	3360829	1			T1	3		T2	3		T56	9
valid_sources[0x1e]	1359972	1			T2	4		T3	6		T59	11
valid_sources[0x1f]	1358302	1			T2	3		T69	2		T71	3
valid_sources[0x20]	1354176	1			T2	2		T55	1		T59	6
valid_sources[0x21]	1360020	1			T2	5		T59	30		T62	14
valid_sources[0x22]	2196281	1			T2	1		T59	4		T72	4
valid_sources[0x23]	3698855	1			T2	2		T69	10		T72	4
valid_sources[0x24]	2008968	1			T3	4		T56	67		T59	9
valid_sources[0x25]	1357638	1			T2	3		T59	9		T69	4
valid_sources[0x26]	1357255	1			T2	1		T59	4		T69	1
valid_sources[0x27]	1450511	1			T3	4		T57	4		T59	5
valid_sources[0x28]	1362713	1			T2	1		T62	3		T69	5
valid_sources[0x29]	3304812	1			T69	5		T71	16		T61	1
valid_sources[0x2a]	1358901	1			T2	1		T3	2		T59	10
valid_sources[0x2b]	1360624	1			T2	2		T59	10		T71	14
valid_sources[0x2c]	1358867	1			T2	2		T3	3		T59	15
valid_sources[0x2d]	2254313	1			T2	4		T69	5		T61	2
valid_sources[0x2e]	1362311	1			T2	6		T3	4		T69	5
valid_sources[0x2f]	3341353	1			T71	29		T72	5		T63	3
valid_sources[0x30]	2017227	1			T2	3		T57	5		T59	4
valid_sources[0x31]	1363418	1			T59	30		T62	5		T69	5
valid_sources[0x32]	1368101	1			T2	5		T3	1		T59	25
valid_sources[0x33]	4303955	1			T2	3		T3	5		T59	11
valid_sources[0x34]	1363195	1			T2	1		T3	1		T59	24
valid_sources[0x35]	1357636	1			T2	4		T3	7		T59	4
valid_sources[0x36]	1809122	1			T2	3		T59	17		T69	6
valid_sources[0x37]	3698824	1			T2	5		T69	4		T72	3
valid_sources[0x38]	1365751	1			T2	5		T3	2		T55	2
valid_sources[0x39]	3689012	1			T2	3		T62	15		T69	11
valid_sources[0x3a]	1358889	1			T2	9		T3	7		T59	4
valid_sources[0x3b]	1355971	1			T2	2		T59	5		T69	3
valid_sources[0x3c]	1419812	1			T2	3		T58	113		T59	10
valid_sources[0x3d]	1362420	1			T2	3		T3	12		T59	2
valid_sources[0x3e]	1367613	1			T2	5		T3	2		T69	23
valid_sources[0x3f]	2136530	1			T2	2		T57	3		T69	1
valid_sources[0x40]	1370932	1			T2	4		T59	19		T69	6
valid_sources[0x41]	3684078	1			T2	7		T3	9		T56	1
valid_sources[0x42]	2205641	1			T2	2		T59	8		T69	3
valid_sources[0x43]	1381096	1			T1	4		T2	1		T59	5
valid_sources[0x44]	1361348	1			T2	4		T69	2		T71	3
valid_sources[0x45]	2351532	1			T2	4		T3	1		T59	11
valid_sources[0x46]	2288458	1			T2	1		T59	10		T69	7
valid_sources[0x47]	1360445	1			T2	2		T3	1		T72	4
valid_sources[0x48]	1366861	1			T59	3		T69	2		T71	16
valid_sources[0x49]	1520235	1			T2	4		T59	30		T62	11
valid_sources[0x4a]	1424146	1			T2	3		T3	1		T57	5
valid_sources[0x4b]	1438821	1			T2	1		T60	1		T71	43
valid_sources[0x4c]	1356906	1			T59	1		T71	7		T72	5
valid_sources[0x4d]	1361875	1			T2	1		T69	11		T71	12
valid_sources[0x4e]	1362818	1			T59	1		T60	2		T69	12
valid_sources[0x4f]	1368864	1			T1	1		T2	1		T3	1
valid_sources[0x50]	1363542	1			T2	1		T59	9		T69	3
valid_sources[0x51]	1520648	1			T2	4		T3	3		T59	8
valid_sources[0x52]	1359094	1			T2	2		T3	8		T60	1
valid_sources[0x53]	1356135	1			T59	7		T69	4		T61	5
valid_sources[0x54]	1354210	1			T2	2		T59	7		T69	3
valid_sources[0x55]	1368618	1			T2	9		T57	1		T59	9
valid_sources[0x56]	1365074	1			T2	6		T59	4		T60	1
valid_sources[0x57]	1367551	1			T2	2		T59	3		T69	2
valid_sources[0x58]	1360760	1			T2	1		T69	2		T72	5
valid_sources[0x59]	3299532	1			T2	5		T59	14		T69	13
valid_sources[0x5a]	1898045	1			T2	3		T55	4		T69	5
valid_sources[0x5b]	1364032	1			T2	1		T3	6		T59	5
valid_sources[0x5c]	1509179	1			T2	3		T69	2		T72	6
valid_sources[0x5d]	1801457	1			T2	1		T69	12		T61	3
valid_sources[0x5e]	3541845	1			T2	5		T58	10		T59	10
valid_sources[0x5f]	1366106	1			T2	2		T3	6		T55	1
valid_sources[0x60]	1355997	1			T2	4		T59	3		T69	5
valid_sources[0x61]	1362139	1			T2	2		T59	3		T62	1
valid_sources[0x62]	1358918	1			T2	2		T3	3		T59	13
valid_sources[0x63]	2154713	1			T2	1		T59	10		T69	10
valid_sources[0x64]	1364570	1			T2	4		T3	1		T56	54
valid_sources[0x65]	1359317	1			T2	4		T59	1		T62	5
valid_sources[0x66]	1548863	1			T2	1		T59	20		T60	2
valid_sources[0x67]	1358064	1			T62	7		T69	2		T71	2
valid_sources[0x68]	1361972	1			T2	8		T69	6		T71	9
valid_sources[0x69]	1363546	1			T3	3		T59	8		T69	3
valid_sources[0x6a]	1376219	1			T2	2		T55	1		T56	7
valid_sources[0x6b]	1361535	1			T2	1		T59	7		T69	4
valid_sources[0x6c]	1360775	1			T56	5		T69	15		T72	8
valid_sources[0x6d]	3830484	1			T2	3		T59	8		T62	5
valid_sources[0x6e]	2046730	1			T55	2		T56	36		T59	3
valid_sources[0x6f]	1362941	1			T2	1		T59	10		T62	4
valid_sources[0x70]	1358043	1			T2	1		T69	1		T71	14
valid_sources[0x71]	1354236	1			T2	8		T55	11		T69	15
valid_sources[0x72]	1826702	1			T2	4		T55	1		T59	3
valid_sources[0x73]	1803834	1			T2	2		T69	7		T72	4
valid_sources[0x74]	1360062	1			T2	1		T59	8		T62	7
valid_sources[0x75]	1471418	1			T2	4		T3	1		T58	23
valid_sources[0x76]	1391969	1			T2	2		T3	2		T58	9
valid_sources[0x77]	1362357	1			T2	1		T59	6		T62	3
valid_sources[0x78]	2249913	1			T2	3		T59	3		T69	4
valid_sources[0x79]	2190949	1			T2	4		T59	13		T69	5
valid_sources[0x7a]	1398973	1			T2	4		T57	2		T59	1
valid_sources[0x7b]	1535742	1			T2	3		T59	2		T69	6
valid_sources[0x7c]	1421149	1			T2	3		T3	4		T69	5
valid_sources[0x7d]	1366830	1			T2	3		T58	111		T59	8
valid_sources[0x7e]	2019439	1			T1	14		T2	5		T55	3
valid_sources[0x7f]	2187512	1			T2	4		T69	6		T61	1
valid_sources[0x80]	1363609	1			T2	3		T69	6		T72	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72239605

1

T1

6

T2

306

T3

128

values[0x0]

all_enables

biggest_size

61482533

1

T1

4

T2

155

T3

5

values[0x1]

all_enables

biggest_size

53051783

1

T1

1

T2

148

T3

7